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2023-06-12arm64: versal-net: Add support for SPP production versionMichal Simek
Production version restarting platform version field from 0 that's why add new calculation to be able to use different DT for these platforms. Requested DT names for production silicons for IPP/SPP and EMU platform are versal-net-ipp-rev2.0.dts and versal-net-emu-rev2.0.dts. If platform version increase numbers revision can be even higher. As of today platform version is 2 that's why expected is rev2.2. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/691e166b3cf2643d7edf482bda5500163eecb35a.1684311689.git.michal.simek@amd.com
2023-06-12mach-zynqmp: handoff: Add missing headerAlgapally Santosh Sagar
Add missing prototype to fix the sparse warning. warning: no previous prototype for 'bl2_plat_get_bl31_params' [-Wmissing-prototypes] Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Link: https://lore.kernel.org/r/20230519113816.22083-3-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-06-12arm64: versal-net: Detect and display bootmodeAshok Reddy Soma
Read boodmode register using versal_net_get_bootmode() in board_late_init and prepare corresponding distro boot command sequence based on it. versal_net_get_bootmode() will be changed to use smc calls later, but for now directly reads the register. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230516144753.30869-1-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-06-08ARM: rmobile: Identify R-Car D3 R8A77995 r1.1 SoCHai Pham
Add support to identify R8A77995 r1.1 SoC. Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> [Marek: Slight update to commit message, spell out the SoC model]
2023-06-08ARM: rmobile: Identify R-Car M3-W R8A7796 r1.1/1.2 SoCHiroyuki Yokoyama
r8a7796 cpu revision v1.2 has the same information as revision v1.1. This patch fixes revision display at startup to "rev 1.1/1.2". Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> [Marek: Slight update to commit message, spell out the SoC model]
2023-06-07sunxi: Fix typo in include guardSam Edwards
Signed-off-by: Sam Edwards <CFSworks@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2023-06-07sunxi: dts: arm/arm64: update devicetree files from Linux-v6.4-rc2Andre Przywara
Sync the devicetree files from the official Linux kernel tree, v6.4-rc2. This is covering both 64-bit and 32-bit Allwinner SoCs with Arm Ltd. cores, we skip the new RISC-V bits for now, as sunxi RISC-V support is still work in progress. Among smaller cosmetic changes, this adds a SATA regulator node which we need in U-Boot to get rid of hard-coded GPIOs. Also this updates the Allwinner F1C100s DTs, enabling USB support, and also adds the DTs for two new boards. As before, this omits the non-backwards compatible changes to the R_INTC controller, to remain compatible with older kernels. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-05-30arm: apple: Add initial Apple M2 Pro/Max supportMark Kettenis
Apple's M2 Pro/Max SoC are somewhat similar to the M1 Pro/Max but need a tweaked memory map. USB, NVMe, UART and WDT are working with the existing drivers. Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2023-05-30arm: mach-k3: security: separate out validating binary logicManorit Chawdhry
K3 GP devices allows booting the secure binaries on them by bypassing the x509 header on them. ATF and OPTEE firewalling required the rproc_load to be called before authentication. This change caused the failure for GP devices that strips off the headers. The boot vector had been set before the headers were stripped off causing the runtime stripping to fail and stripping becoming in-effective. Separate out the secure binary check on GP/HS devices so that the boot_vector could be stripped before calling rproc_load. This allows keeping the authentication later when the cluster is on along with allowing the stripping of the binaries in case of gp devices. Fixes: 1e00e9be62e5 ("arm: mach-k3: common: re-locate authentication for atf/optee") Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-05-30arm: mach-k3: Increase SYSFW max image sizeDave Gerlach
When booting with HS silicon, the system firmware image is 278270, which is slightly larger than currently allocated amount. This can cause unexpected behavior if this overlap interferes with other things in memory, so increase this with a slightly margin added as well to avoid any boot issues that can appear after system firmware gets loaded. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com> Reviewed-by: Dhruva Gole <d-gole@ti.com>
2023-05-30Kconfig: j721e: Change K3_MCU_SCRATCHPAD_BASE to non firewalled regionManorit Chawdhry
In non-combined boot flow for K3, all the firewalls are locked by default until sysfw comes up. Rom configures some of the firewall for its usage along with the SRAM for R5 but the PSRAM region is still locked. The K3 MCU Scratchpad for j721e was set to a PSRAM region triggering the firewall exception before sysfw came up. The exception started happening after adding multi dtb support that accesses the scratchpad for reading EEPROM contents. The commit changes R5 MCU scratchpad for j721e to an SRAM region. Old Map: ┌─────────────────────────────────────┐ 0x41c00000 │ SPL │ ├─────────────────────────────────────┤ 0x41c40000 (approx) │ STACK │ ├─────────────────────────────────────┤ 0x41c85b20 │ Global data │ │ sizeof(struct global_data) = 0xd8 │ ├─────────────────────────────────────┤ gd->malloc_base = 0x41c85bfc │ HEAP │ │ CONFIG_SYS_MALLOC_F_LEN = 0x70000 │ ├─────────────────────────────────────┤ CONFIG_SPL_BSS_START_ADDR │ SPL BSS │ (0x41cf5bfc) │ CONFIG_SPL_BSS_MAX_SIZE = 0xA000 │ └─────────────────────────────────────┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX                 (0x41cffbfc) New Map: ┌─────────────────────────────────────┐ 0x41c00000 │ SPL │ ├─────────────────────────────────────┤ 0x41c40000 (approx) │ EMPTY │ ├─────────────────────────────────────┤ 0x41c81920 │ STACK │ │ SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000 │ ├─────────────────────────────────────┤ 0x41c85920 │ Global data │ │ sizeof(struct global_data) = 0xd8 │ ├─────────────────────────────────────┤ gd->malloc_base = 0x41c859f0 │ HEAP │ │ CONFIG_SYS_MALLOC_F_LEN = 0x70000 │ ├─────────────────────────────────────┤ CONFIG_SPL_BSS_START_ADDR │ SPL BSS │ (0x41cf59f0) │ CONFIG_SPL_BSS_MAX_SIZE = 0xA000 │ ├─────────────────────────────────────┤ 0x41cff9fc │ NEW MCU SCRATCHPAD │ │ SYS_K3_MCU_SCRATCHPAD_SIZE = 0x200 │ └─────────────────────────────────────┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX                 (0x41cffbfc) Fixes: ab977c8b91b4 ("configs: j721s2_evm_r5: Enable support for building multiple dtbs into FIT") Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com> [n-francis@ti.com: SRAM allocation addressing diagram] Signed-off-by: Neha Francis <n-francis@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com>
2023-05-30arm: k3: config.mk: Add missing dependencies on tispl.bin HSAndrew Davis
When building for secure devices using non-buildman based image generation the signed tispl.bin file is called tispl.bin_HS. Also build the unsigned tispl.bin file as expected. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-05-25Merge tag 'u-boot-imx-20230525' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20230525 ------------------- - i.MX93 series - Fixes CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/16412
2023-05-21imx9: Calculate DDR size from DDRC settingYe Li
To avoid using static setting for ECC enabled DDR size, switch to calculate DDR size from DDRC setting Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21ddr: imx93: update the ddr init to support mult setpointsJacky Bai
Update the DDR init flow for multi-setpoint support on i.MX93. A new fsp_cfg struct need to be added in the timing file to store the diff part of the DDRC and DRAM MR register for each setpoint. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21ddr: imx93: Add 625M bypass clock supportJacky Bai
Add 625M bypass clock that may be used DRAM 625M bypass mode support. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21ddr: imx9: Add workaround for DDRPHY rank-to-rank errataYe Li
According to DDRPHY errata, the Rank-to-Rank Spacing and tphy_rdcsgap specification does not include the Critical Delay Difference (CDD) to properly define the required rank-to-rank read command spacing after executing PHY training firmware. Following the errata workaround, at the end of data training, we get all CDD values through the MessageBlock, then re-configure the DDRC timing of WWT/WRT/RRT/RWT with comparing MAX CDD values. Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com>
2023-05-21arm: dts: imx93: add tmuPeng Fan
Add tmu nodes and thermal zone Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21arm: dts: imx93: sync device tree with LinuxPeng Fan
Sync device tree with next-20230426 Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: allow to bootaux Mcore with input addressYe Li
Currently bootaux only supports to boot M33 core from TCM. Since ATF has changed to use x2 parameter for M33 image address, update the bootaux command to use input address, so we can support boot from any possilbe address like TCM, DDR, Flexspi NOR. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: use i.MX generic rom api functionPeng Fan
There is no need to save gd with using the generic rom api function, so simplify code. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: correct coding stylePeng Fan
The end brace should be in a new line Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: add i.MX93 variants supportPeng Fan
According to datasheet, iMX93 has fused parts with CORE1 or NPU or both disabled. So update code to support it, the kernel device tree runtime update will be added in future patches. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: clock: config arm alt root to 500mhzPeng Fan
Config the A55 alt root clock to 500MHz(LD mode frequency) by default. Normally, this clock root is only used as an intermediate clock soure for A55 core/dsu when change the ARM PLL frequency. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: clock: add CONFIG_IMX9_LOW_DRIVE_MODE supportPeng Fan
Add CONFIG_IMX9_LOW_DRIVE_MODE in imx9 clk, later we will add board support Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: clock: clear HW_CTRL_SELPeng Fan
The HW_CTRL_SEL should be cleared when configuring PLL to avoid potential glitch Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: Get market segment and speed gradingPeng Fan
Get the chip's market segment and speed grading from fuse and print them in boot log as other i.MX series. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: soc: support reset causePeng Fan
Support print reset cause. Since SRSR is not accessible from non-secure world, so first save it to grp0, then read it in non-secure world. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: Change hard coded MAC to read from fuseYe Li
The MAC addresses are hard coded for bring up. Change it to support reading from fuse. Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: cut off OPTEE memory region from U-BootPeng Fan
OPTEE memory region is set secure access only in ATF with configuration to TRDC, and need to remove it from U-Boot, otherwise U-Boot and Kernel may crash when accessing the memory Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: simplify clk settingsPeng Fan
Simplify the clk root settings with an array Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: correct getting LPI2C clkPeng Fan
LPI2C_CLK_ROOT should be used instead of LPUART_CLK_ROOT for i2c Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: use parameter freq when set_arm_clkPeng Fan
The freq parameter was ignored, should use it when configuring ARM PLL Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: add more PLL settingsPeng Fan
Add more PLL settings for A55 and Display Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: configure M33 systick to 24MPeng Fan
The M33 systick should be 24M per reference mannual, so correct it. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx: move imx8 sci header file to include/firmware/imxPeng Fan
Move imx8 sci header file to include/firmware/imx, then we could use build macro to reuse some i.MX8 drivers for i.MX9, such as drivers/cpu/imx8_cpu.c. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Stefano Babic <sbabic@denx.de>
2023-05-21imx: spl_imx_romapi: typo fixPeng Fan
Unknow->Unknown Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx8ulp: build ahabPeng Fan
The ahab was missed to be compiled, so add it back. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21ARM: dts: imx7d-sdb-u-boot: Fix usdhc1 UHS operationFabio Estevam
Commit 1a7904fdfa7d ("mmc: fsl_esdhc_imx: Use esdhc_soc_data flags to set host caps") exposed the following SD card error: U-Boot 2023.04-00652-g487e42f7bc5e (Apr 05 2023 - 22:14:21 -0300) CPU: Freescale i.MX7D rev1.0 1000 MHz (running at 792 MHz) CPU: Commercial temperature grade (0C to 95C) at 35C Reset cause: POR Model: Freescale i.MX7 SabreSD Board Board: i.MX7D SABRESD in non-secure mode DRAM: 1 GiB Core: 100 devices, 19 uclasses, devicetree: separate PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x10 MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... Card did not respond to voltage select! : -110 *** Warning - No block device, using default environment The reason of the problem, as explained by Ye Li: "When UHS is enabled in defconfig, the usdhc1 node in imx7d-sdb.dts does not configure pad for VSELECT, also the data pad should be set to 100Mhz/200Mhz pin states." Apply these changes into u-boot.dtsi for now. When these changes reach the Linux mainline imx7d-sdb, they can be dropped from u-boot.dtsi. This fixes UHS mode on the imx7d-sdb board. Suggested-by: Ye Li <ye.li@nxp.com> Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-05-21thermal: imx_tmu: Move architecture code into driverMarek Vasut
Stop polluting the architecture directory with driver specific code, move it into driver where it should be. Split the code slightly so the MX8MM/MX8MN fuse readout and programming and MX8MP fuse readout and programming are in their separate functions, and called in case of matching SoC. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
2023-05-21ARM: imx: Fix parsing of ROM log event IDs on iMX8MFedor Ross
It seems like the ROM log events for the iMX8M are not fully covered by AN12853 i.MX ROMs Log Events, Rev. 0, May 2020. On iMX8M the ROM event ID 0x82 seems to use parameter0 which stops the parsing because the end of list is detected too early. This patch adds ROM event ID 0x82 and skips the next word if ID 0x82 is parsed. Fixes: a5ee05cf71 ("ARM: imx: Pick correct eMMC boot partition from ROM log") Signed-off-by: Fedor Ross <fedor.ross@ifm.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-05-19rockchip: rk3588-rock-5b: Enable boot from SPI NOR flashJonas Karlman
Add sfc and flash node to device tree and config options to enable support for booting from SPI NOR flash on Radxa ROCK 5 Model B. Similar to RK3568 the BootRom in RK3588 can read all data and look for idbloader at 0x8000, same as on SD and eMMC. Use the rksd format and modify the mkimage offset to generate a bootable u-boot-rockchip-spi.bin that can be written to 0x0 of SPI NOR flash. The FIT image is loaded from 0x60000. => sf probe SF: Detected mx25u12835f with page size 256 Bytes, erase size 4 KiB, total 16 MiB => load mmc 1:1 10000000 u-boot-rockchip-spi.bin 1492992 bytes read in 129 ms (11 MiB/s) => sf update $fileaddr 0 $filesize device 0 offset 0x0, size 0x16c800 1300480 bytes written, 192512 bytes skipped in 11.103s, speed 137694 B/s The BROM_BOOTSOURCE_ID value read back when booting from SPI flash does not match the expected value of 3 (SPINOR) used by other SoCs. Instead a value of 6 is read back, add a new enum value to handle this new bootsource id. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-05-18rockchip: rk3588-rock-5b: Add bootph prop to pinctrl for uart2 and sdhciJonas Karlman
Enable pinctrl for sdhci in SPL to support loading of FIT image from SD and eMMC storage when booting from SPI NOR flash. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18rockchip: rk3588: Select DM_RESET and DM_REGULATOR_FIXED in arch KconfigJonas Karlman
Like other Rockchip SoCs, DM_RESET and DM_REGULATOR_FIXED is useful across RK3588 platform. Select them from arch Kconfig. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18rockchip: rk3568-rock-3a: Enable boot from SPI NOR flashJonas Karlman
Add sfc and flash node to device tree and config options to enable support for booting from SPI NOR flash on Radxa ROCK 3 Model A. Unlike prior generation SoCs the BootRom in RK3568 can read all data and look for idbloader at 0x8000, same as on SD and eMMC. Use the rksd format and modify the mkimage offset to generate a bootable u-boot-rockchip-spi.bin that can be written to 0x0 of SPI NOR flash. The FIT image is loaded from 0x60000. => sf probe SF: Detected mx25u12835f with page size 256 Bytes, erase size 4 KiB, total 16 MiB => load mmc 1:1 10000000 u-boot-rockchip-spi.bin 1384448 bytes read in 119 ms (11.1 MiB/s) => sf update $fileaddr 0 $filesize device 0 offset 0x0, size 0x152000 1179648 bytes written, 204800 bytes skipped in 9.901s, speed 143185 B/s Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18rockchip: rk3568-rock-3a: Use pinctrl for sdmmc and sdhci in SPLJonas Karlman
Enable pinctrl for sdmmc and sdhci in SPL to support loading of FIT image from SD and eMMC storage when booting from SPI NOR flash. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18rockchip: rk3566-radxa-cm3-io: Use pinctrl for sdmmc and sdhci in SPLJonas Karlman
Enable pinctrl for sdmmc and sdhci in SPL to support loading of FIT image from SD and eMMC storage when booting from SPI NOR flash. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18rockchip: rk3566-radxa-cm3-io: Update defconfigJonas Karlman
Update defconfig for rk3566-radxa-cm3-io with new defaults. Also add missing supported mmc modes to sdhci node. Remove the SPL_ROCKCHIP_BACK_TO_BROM=y option, SPL is expected to load next stage from a FIT image and then jump to next stage not back to BootRom. Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash of FIT images. This help indicate if there is an issue loading any of the images to DRAM or SRAM. Extend SPL_MAX_SIZE to 0x40000, SPL is loaded to 0x0 and TF-A is loaded to 0x40000, use the space in between as SPL_MAX_SIZE. Add config option to include useful gpio cmd. Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is set based on cpuid read from OTP. Filter out assigned-clock props with CONFIG_OF_SPL_REMOVE_PROPS, U-Boot proper will read and configure assigned-clock props. Add CONFIG_SYS_NS16550_MEM32=y to use 32bit access of serial register. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18rockchip: rk356x-u-boot: Add xin24m clock node to SPLJonas Karlman
Add bootph-all prop to xin24m clock node, it is referenced by cru node. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18ARM: dts: rockchip: rock5b: enable pcie2x1l2 and associated combphyChristopher Obbard
Enable the PCIe 2x1l 2 device and associated combphy. On this bus, the Rock5B has an Ethernet transceiver connected. Signed-off-by: Christopher Obbard <chris.obbard@collabora.com> [eugen.hristev@collabora.com: minor tweaks] Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> [jonas@kwiboo.se: add PCIe pins] Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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