| Age | Commit message (Expand) | Author |
|---|---|---|
| 2023-02-17 | riscv: Rename Andes cpu and board names | Leo Yu-Chi Liang |
| 2023-02-17 | riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init() | Yu Chien Peter Lin |
| 2023-02-01 | riscv: ae350: Enable CCTL_SUEN | Rick Chen |
| 2021-10-07 | riscv: ae350: enable Coherence Manager for ae350 | Leo Yu-Chi Liang |
| 2019-12-02 | common: Move ARM cache operations out of common.h | Simon Glass |
| 2019-12-02 | common: Move some cache and MMU functions out of common.h | Simon Glass |
| 2018-11-26 | riscv: cache: Implement i/dcache [status, enable, disable] | Rick Chen |
| 2018-10-03 | riscv: Move do_reset() to a common place | Bin Meng |
| 2018-05-29 | riscv: cpu: nx25: Rename as ax25 | Rick Chen |
 |
index : u-boot-toradex.git | |
| U-Boot bootloader for Apalis and Colibri modules | Toradex |
| summaryrefslogtreecommitdiff |