u-boot-toradex.git - U-Boot bootloader for Apalis and Colibri modules

Age	Commit message (Expand)	Author
2024-10-11	arch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD	Simon Glass
2024-09-11	riscv: Add AST2700 SoC initial platform support	Chia-Wei Wang
2024-09-11	riscv: u-boot-spl.lds: Remove _image_binary_end alignment	Chia-Wei Wang
2024-05-30	andes: Use UCCTLCOMMAND instead of MCCTLCOMMAND	Leo Yu-Chi Liang
2024-05-30	riscv: remove cache enablement in start.S	Leo Yu-Chi Liang
2024-05-14	andes: Unify naming policy for Andes related source	Leo Yu-Chi Liang
2024-05-02	board: starfive: Rename spl_soc_init() to spl_dram_init()	Lukas Funke
2024-05-02	board: sifive: Rename spl_soc_init() to spl_dram_init()	Lukas Funke
2024-05-01	riscv: andesv5: Set default cache line size to 64-bytes	Yu Chien Peter Lin
2024-04-09	riscv: support extension probing using riscv, isa-extensions	Conor Dooley
2024-04-09	riscv: don't read riscv, isa in the riscv cpu's get_desc()	Conor Dooley
2024-04-09	riscv: cache: Implement dcache for cv1800b	Kongyang Liu
2024-04-09	riscv: cpu: cv1800b: Add support for cv1800b SoC	Kongyang Liu
2024-04-09	riscv: add backtrace support	Ben Dooks
2024-03-12	riscv: cpu: improve multi-letter extension detection in supports_extension()	Conor Dooley
2023-12-27	andes: cpu: Enable cache and TLB ECC support	Leo Yu-Chi Liang
2023-12-27	andes: cpu: Enable memboost feature	Leo Yu-Chi Liang
2023-12-27	andes: ae350: Implement cache switch via Kconfig	Leo Yu-Chi Liang
2023-12-21	riscv: Add a reset_cpu() function	Simon Glass
2023-11-02	riscv: Align the trap handler to 64 bytes	Samuel Holland
2023-10-24	riscv: Remove common.h usage	Tom Rini
2023-10-19	riscv: remove dram_init_banksize()	Heinrich Schuchardt
2023-10-04	riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode	Yu Chien Peter Lin
2023-10-02	Merge branch 'next'	Tom Rini
2023-09-06	riscv: Correct event usage for riscv_cpu_probe/setup	Tom Rini
2023-09-06	riscv: Rework riscv_cpu_probe for current event macros	Tom Rini
2023-09-05	riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT	Shengyu Qu
2023-09-04	Merge tag 'v2023.10-rc4' into next	Tom Rini
2023-08-31	event: Convert existing spy records to simple	Simon Glass
2023-08-22	riscv: cpu: make riscv_cpu_probe to EVT_DM_POST_INIT_R callback	Chanho Park
2023-08-15	common: return type board_get_usable_ram_top	Heinrich Schuchardt
2023-08-10	riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE	Shengyu Qu
2023-08-10	riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation	Shengyu Qu
2023-08-10	riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE	Minda Chen
2023-07-24	riscv: define a cache line size for the generic CPU	Heinrich Schuchardt
2023-07-24	riscv: setup per-hart stack earlier	Bo Gan
2023-07-12	riscv: Rename SiFive CLINT to RISC-V ALINT	Bin Meng
2023-07-12	ram: starfive: Read memory size information from EEPROM	Yanhong Wang
2023-06-27	riscv: Fix alignment of RELA sections in the linker scripts	Bin Meng
2023-05-11	dm: Emit the arch_cpu_init_dm() even only before relocation	Simon Glass
2023-04-20	riscv: Update alignment for some sections in linker scripts	Bin Meng
2023-04-20	riscv: spl: Remove relocation sections	Bin Meng
2023-04-20	riscv: Avoid updating the link register	Bin Meng
2023-04-20	riscv: Change to use positive offset to access relocation entries	Bin Meng
2023-04-20	riscv: Optimize loading relocation type	Bin Meng
2023-04-20	riscv: Optimize source end address calculation in start.S	Bin Meng
2023-04-20	riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC	Yanhong Wang
2023-04-20	riscv: cpu: jh7110: Add support for jh7110 SoC	Yanhong Wang
2023-02-17	riscv: Rename Andes cpu and board names	Leo Yu-Chi Liang
2023-02-17	configs: ae350: Enable v5l2 cache for AE350 platforms in SPL	Yu Chien Peter Lin