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path: root/arch/riscv/include
AgeCommit message (Expand)Author
2025-12-08riscv: create a custom CPU implementation for PolarFire SoCConor Dooley
2025-09-19arch/riscv: Remove unused macro in encoding.hGreentime Hu
2025-07-03riscv: byteorder: add test for big-endianBen Dooks
2025-07-03riscv: cpu: th1520: Add a routine to bring up secondary coresYao Zi
2025-06-13riscv: remove volatile from set_gd prototypeRasmus Villemoes
2025-06-02Revert "riscv: Select appropriate image type"Mayuresh Chitale
2025-05-21riscv: cpu: th1520: Initialize IOPMPs in SPLYao Zi
2025-05-21riscv: cpu: Add TH1520 CPU supportYao Zi
2025-05-21riscv: insn-def.h: Fix header guardMayuresh Chitale
2025-05-21riscv: Access gd with inline assembly when building with LTO or ClangYao Zi
2025-05-21riscv: Select appropriate image typeMayuresh Chitale
2025-03-17spl: starfive: visionfive2: Disable USB overcurrent pin by default.Minda Chen
2025-03-10common: clean up setjmp.hHeinrich Schuchardt
2025-01-16riscv: Enhance extension probingMayuresh Chitale
2024-10-29riscv: resume needs to be a globalAnton Blanchard
2024-10-28riscv: Add support for defining instructionsMayuresh Chitale
2024-10-28cmd: sbi: Add FWFT, MPXY extensionsHeinrich Schuchardt
2024-09-16Merge tag 'v2024.10-rc5' into nextTom Rini
2024-09-11ram: ast2700: Add DRAM controller initializationChia-Wei Wang
2024-09-11board: ibex_ast2700: Add FMC header supportChia-Wei Wang
2024-09-11riscv: Add AST2700 SoC initial platform supportChia-Wei Wang
2024-09-10riscv: define find_{first,next}_zero_bit in asm/bitops.hMaxim Kochetkov
2024-05-30andes: Use UCCTLCOMMAND instead of MCCTLCOMMANDLeo Yu-Chi Liang
2024-05-14board: starfive: function to read eMMC sizeHeinrich Schuchardt
2024-05-02board: starfive: Rename spl_soc_init() to spl_dram_init()Lukas Funke
2024-05-02board: sifive: Rename spl_soc_init() to spl_dram_init()Lukas Funke
2024-05-01cmd: sbi: add Supervisor Software Events extensionHeinrich Schuchardt
2024-04-09eeprom: starfive: function get_product_id_from_eeprom()Heinrich Schuchardt
2024-01-31cmd: sbi: add support for Debug Trigger ExtensionHeinrich Schuchardt
2024-01-31board: sifive: spl: Initialized the PWM setting in the SPL stageVincent Chen
2024-01-07riscv: add ACPI fields to global dataHeinrich Schuchardt
2023-12-27andes: cpu: Enable cache and TLB ECC supportLeo Yu-Chi Liang
2023-12-27andes: cpu: Enable memboost featureLeo Yu-Chi Liang
2023-12-27andes: csr.h: Clean up CSR definitionLeo Yu-Chi Liang
2023-12-21global: Rework architecture global_data.h to include <linux/types.h>Tom Rini
2023-11-28riscv: io.h: Fix signatures of reads/writes functionsIgor Prusov
2023-11-28riscv: io.h: Add defines for reads/writes functionsIgor Prusov
2023-11-02riscv: import read/write_relaxed functionsChanho Park
2023-11-02riscv: cpu: jh7110: Add gpio helper macrosChanho Park
2023-10-24riscv: Remove common.h usageTom Rini
2023-10-19riscv: Add Zbb support for building U-BootYu Chien Peter Lin
2023-10-02Merge branch 'next'Tom Rini
2023-09-22Record the position of the SMBIOS tablesSimon Glass
2023-09-05risc-v: implement DBCN write byteHeinrich Schuchardt
2023-08-31event: Convert existing spy records to simpleSimon Glass
2023-08-10cmd/sbi: display new extensionsHeinrich Schuchardt
2023-08-02acpi: Add missing RISC-V acpi_table headerHeinrich Schuchardt
2023-07-12riscv: Rename SiFive CLINT to RISC-V ALINTBin Meng
2023-07-12eeprom: starfive: Enable ID EEPROM configurationYanhong Wang
2023-07-06riscv: define test_and_{set,clear}_bit in asm/bitops.hBen Dooks