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path: root/arch/riscv/include/asm/arch-andes/csr.h
AgeCommit message (Expand)Author
2023-12-27andes: cpu: Enable cache and TLB ECC supportLeo Yu-Chi Liang
2023-12-27andes: cpu: Enable memboost featureLeo Yu-Chi Liang
2023-12-27andes: csr.h: Clean up CSR definitionLeo Yu-Chi Liang
2023-10-24riscv: Remove common.h usageTom Rini
2023-02-17riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()Yu Chien Peter Lin