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AgeCommit message (Expand)Author
2021-07-07riscv: dts: add OpenPiton RISC-V board dts supportTianrui Wei
2021-07-06riscv: dts: add dts for unmatched rev1Zong Li
2021-07-06board: sifive: Add an interface to get PCB revisionZong Li
2021-07-06riscv: sifive: fu740: Support i2c in splZong Li
2021-07-06riscv: sifive: fu740: kconfig: Enable support for Opencores I2C controllerZong Li
2021-07-06board: riscv: add openpiton-riscv64 SoC supportTianrui Wei
2021-06-28Merge tag 'v2021.07-rc5' into nextTom Rini
2021-06-17k210: dts: Set PLL1 to the same rate as PLL0Sean Anderson
2021-06-17riscv: andes_plic: Fix riscv_get_ipi() maskBin Meng
2021-06-17riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL configBin Meng
2021-06-17riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bitBin Meng
2021-06-17riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodesBin Meng
2021-06-17riscv: ae350: dts: Remove the unnecessary space in bootargsBin Meng
2021-06-17riscv: ae350: dts: Add SPDX license headerBin Meng
2021-05-31riscv: cpu: fu740: clear feature disable CSRGreen Wan
2021-05-31board: sifive: add HiFive Unmatched board supportGreen Wan
2021-05-31riscv: dts: add SiFive Unmatched board supportGreen Wan
2021-05-31riscv: dts: add fu740 supportGreen Wan
2021-05-31drivers: clk: add fu740 supportGreen Wan
2021-05-31riscv: cpu: fu740: Add support for cpu fu740Green Wan
2021-05-24treewide: Convert macro and uses of __section(foo) to __section("foo")Marek BehĂșn
2021-05-19riscv: Drop USE_SPL_FIT_GENERATORBin Meng
2021-05-19riscv: ae350: Switch to use binman to generate u-boot.itbBin Meng
2021-05-19riscv: qemu: Switch to use binman to generate u-boot.itbBin Meng
2021-05-19riscv: dts: Sort build targets in alphabetical orderBin Meng
2021-05-19riscv: sifive: unleashed: Switch to use binman to generate u-boot.itbBin Meng
2021-05-17riscv: Group assembly optimized implementation of memory routines into a submenuBin Meng
2021-05-17riscv: Fix memmove and optimise memcpy when misalignBin Meng
2021-05-17riscv: Fix arch_fixup_fdt always failing without /chosenSean Anderson
2021-05-17riscv: Split SiFive CLINT support between SPL and U-Boot properBin Meng
2021-05-14Revert "riscv: cpu: fu740: clear feature disable CSR"Bin Meng
2021-05-14riscv: Don't reserve AI ram in k210 dtsSean Anderson
2021-05-14riscv: k210: Use AI as the parent clock of aisram, not PLL1Sean Anderson
2021-05-14riscv: k210: Rename airam to aisramSean Anderson
2021-05-14riscv: Enable some devices pre-relocationSean Anderson
2021-05-05riscv: cpu: fu740: clear feature disable CSRGreen Wan
2021-05-05riscv: cpu: Add callback to init each coreGreen Wan
2021-04-22lmb: move CONFIG_LMB in KconfigPatrick Delaunay
2021-04-20Add support for stack-protectorJoel Peshkin
2021-04-08riscv: dts: mpfs-icicle-kit: Drop 'clock-frequency' in the uart nodesBin Meng
2021-04-08riscv: assembler versions of memcpy, memmove, memsetHeinrich Schuchardt
2021-04-08riscv: simplify longjmpHeinrich Schuchardt
2021-04-08riscv: sifive: Rename fu540 board to unleashedBin Meng
2021-04-08riscv: Add watchdog bindings for the k210Sean Anderson
2021-03-27cpu: Rename SPL_CPU_SUPPORT to SPL_CPUSimon Glass
2021-02-25riscv: k210: Enable QSPI for spi3Sean Anderson
2021-02-15Merge branch '2021-02-02-drop-asm_global_data-when-unused'Tom Rini
2021-02-03riscv: Change phys_addr_t and phys_size_t to 64-bitBin Meng
2021-02-03riscv: Adjust board_get_usable_ram_top() for 32-bitBin Meng
2021-02-02common: Drop asm/global_data.h from common headerSimon Glass