summaryrefslogtreecommitdiff
path: root/arch
AgeCommit message (Collapse)Author
2023-05-21ddr: imx93: Add 625M bypass clock supportJacky Bai
Add 625M bypass clock that may be used DRAM 625M bypass mode support. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21ddr: imx9: Add workaround for DDRPHY rank-to-rank errataYe Li
According to DDRPHY errata, the Rank-to-Rank Spacing and tphy_rdcsgap specification does not include the Critical Delay Difference (CDD) to properly define the required rank-to-rank read command spacing after executing PHY training firmware. Following the errata workaround, at the end of data training, we get all CDD values through the MessageBlock, then re-configure the DDRC timing of WWT/WRT/RRT/RWT with comparing MAX CDD values. Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com>
2023-05-21arm: dts: imx93: add tmuPeng Fan
Add tmu nodes and thermal zone Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21arm: dts: imx93: sync device tree with LinuxPeng Fan
Sync device tree with next-20230426 Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: allow to bootaux Mcore with input addressYe Li
Currently bootaux only supports to boot M33 core from TCM. Since ATF has changed to use x2 parameter for M33 image address, update the bootaux command to use input address, so we can support boot from any possilbe address like TCM, DDR, Flexspi NOR. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: use i.MX generic rom api functionPeng Fan
There is no need to save gd with using the generic rom api function, so simplify code. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: correct coding stylePeng Fan
The end brace should be in a new line Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: add i.MX93 variants supportPeng Fan
According to datasheet, iMX93 has fused parts with CORE1 or NPU or both disabled. So update code to support it, the kernel device tree runtime update will be added in future patches. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: clock: config arm alt root to 500mhzPeng Fan
Config the A55 alt root clock to 500MHz(LD mode frequency) by default. Normally, this clock root is only used as an intermediate clock soure for A55 core/dsu when change the ARM PLL frequency. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: clock: add CONFIG_IMX9_LOW_DRIVE_MODE supportPeng Fan
Add CONFIG_IMX9_LOW_DRIVE_MODE in imx9 clk, later we will add board support Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: clock: clear HW_CTRL_SELPeng Fan
The HW_CTRL_SEL should be cleared when configuring PLL to avoid potential glitch Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: Get market segment and speed gradingPeng Fan
Get the chip's market segment and speed grading from fuse and print them in boot log as other i.MX series. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: soc: support reset causePeng Fan
Support print reset cause. Since SRSR is not accessible from non-secure world, so first save it to grp0, then read it in non-secure world. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: Change hard coded MAC to read from fuseYe Li
The MAC addresses are hard coded for bring up. Change it to support reading from fuse. Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: cut off OPTEE memory region from U-BootPeng Fan
OPTEE memory region is set secure access only in ATF with configuration to TRDC, and need to remove it from U-Boot, otherwise U-Boot and Kernel may crash when accessing the memory Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: simplify clk settingsPeng Fan
Simplify the clk root settings with an array Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: correct getting LPI2C clkPeng Fan
LPI2C_CLK_ROOT should be used instead of LPUART_CLK_ROOT for i2c Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: use parameter freq when set_arm_clkPeng Fan
The freq parameter was ignored, should use it when configuring ARM PLL Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: add more PLL settingsPeng Fan
Add more PLL settings for A55 and Display Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: configure M33 systick to 24MPeng Fan
The M33 systick should be 24M per reference mannual, so correct it. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx: move imx8 sci header file to include/firmware/imxPeng Fan
Move imx8 sci header file to include/firmware/imx, then we could use build macro to reuse some i.MX8 drivers for i.MX9, such as drivers/cpu/imx8_cpu.c. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Stefano Babic <sbabic@denx.de>
2023-05-21imx: spl_imx_romapi: typo fixPeng Fan
Unknow->Unknown Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx8ulp: build ahabPeng Fan
The ahab was missed to be compiled, so add it back. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21ARM: dts: imx7d-sdb-u-boot: Fix usdhc1 UHS operationFabio Estevam
Commit 1a7904fdfa7d ("mmc: fsl_esdhc_imx: Use esdhc_soc_data flags to set host caps") exposed the following SD card error: U-Boot 2023.04-00652-g487e42f7bc5e (Apr 05 2023 - 22:14:21 -0300) CPU: Freescale i.MX7D rev1.0 1000 MHz (running at 792 MHz) CPU: Commercial temperature grade (0C to 95C) at 35C Reset cause: POR Model: Freescale i.MX7 SabreSD Board Board: i.MX7D SABRESD in non-secure mode DRAM: 1 GiB Core: 100 devices, 19 uclasses, devicetree: separate PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x10 MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... Card did not respond to voltage select! : -110 *** Warning - No block device, using default environment The reason of the problem, as explained by Ye Li: "When UHS is enabled in defconfig, the usdhc1 node in imx7d-sdb.dts does not configure pad for VSELECT, also the data pad should be set to 100Mhz/200Mhz pin states." Apply these changes into u-boot.dtsi for now. When these changes reach the Linux mainline imx7d-sdb, they can be dropped from u-boot.dtsi. This fixes UHS mode on the imx7d-sdb board. Suggested-by: Ye Li <ye.li@nxp.com> Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-05-21thermal: imx_tmu: Move architecture code into driverMarek Vasut
Stop polluting the architecture directory with driver specific code, move it into driver where it should be. Split the code slightly so the MX8MM/MX8MN fuse readout and programming and MX8MP fuse readout and programming are in their separate functions, and called in case of matching SoC. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
2023-05-21ARM: imx: Fix parsing of ROM log event IDs on iMX8MFedor Ross
It seems like the ROM log events for the iMX8M are not fully covered by AN12853 i.MX ROMs Log Events, Rev. 0, May 2020. On iMX8M the ROM event ID 0x82 seems to use parameter0 which stops the parsing because the end of list is detected too early. This patch adds ROM event ID 0x82 and skips the next word if ID 0x82 is parsed. Fixes: a5ee05cf71 ("ARM: imx: Pick correct eMMC boot partition from ROM log") Signed-off-by: Fedor Ross <fedor.ross@ifm.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-05-16Merge branch '2023-05-15-assorted-bugfixes'Tom Rini
- Merge in a long-standing fix for some exynos platforms, correct a Kconfig description, fix some env issues, fix an issue in devfdt_get_addr_size_index_ptr and look for "panel-timings" not "panel-timing" per upstream binding.
2023-05-16Merge tag 'xilinx-for-v2023.07-rc3' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2023.07-rc3 .mailmap - Fix Xilinx IDs ZynqMP: - Fix R5 split boot mode - DT fixes - sync with Linux Xilinx: - Enable virtio and RNG support - Enable ADI ethernet phy SPI/Zynq: - Fix dummy byte calculation
2023-05-15drivers: core: ofnode: fix typo in panel timing decodeRaphael Gallais-Pou
In case where a single timing resolution is implemented in the device-tree, the property is named "panel-timing", as specify in Linux kernel binding file: Documentation/devicetree/bindings/display/panel/panel-common.yaml # Display Timings panel-timing: description: Most display panels are restricted to a single resolution and require specific display timings. The panel-timing subnode expresses those timings. $ref: panel-timing.yaml# display-timings: description: Some display panels support several resolutions with different timings. The display-timings bindings supports specifying several timings and optionally specifying which is the native mode. $ref: display-timings.yaml# Fixes: 0347cc773270 ("drivers: core: ofnode: Add panel timing decode.") Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-05-15arm64: zynqmp: Fix User MTD partition sizeMichal Simek
The commit c8630167e0dc ("arm64: zynqmp: Add mtd partition for secure OS storage area") didn't update User partition size that's why size was beyond actual device size. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/0a56405553b87a75e066cd71697cafe7c1c97eef.1681309812.git.michal.simek@amd.com
2023-05-15arm64: zynqmp: Fix issue of apps executing from R5 core 1Ashok Reddy Soma
In current implementation, applications can execute only on R5 core 0. The boot address for R5 core 1 is not supplied. Pass TCM address for R5 core 1 based on the argument to fix the issue. Remove incomplete comment. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/da865717d26648ab7a84345ca8749712efdddee5.1680699999.git.michal.simek@amd.com
2023-05-15ARM: zynq: Sync Microzed board with Linux kernelMichal Simek
Fix model name, node locations and also add pinctrl description for usb. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/3295fde73db13a712b65f4967eb5f39ced895ad4.1679988091.git.michal.simek@amd.com
2023-05-15ARM: zynq: Switch from earlyprintk to earlyconMichal Simek
Switch to earlycon which is preffered over earlyprintk. It is also sync with Linux kernel (zynq-microzed). Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/d280fa18068f80412cf12c235c5245651e7062e2.1679987839.git.michal.simek@amd.com
2023-05-15arch: arm: zynqmp: mp.c: tcminit halt both cores in split modeNeal Frager
The "zynqmp tcminit split" command should halt both cores and not just RPU1 when configuring the TCM memory for split mode. Signed-off-by: Neal Frager <neal.frager@amd.com> Link: https://lore.kernel.org/r/20230323082506.31576-1-neal.frager@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-05-14Merge branch 'master_rzn1/rzn1' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-sh - R-Car RZN1 support
2023-05-13bootstd: Rename distro and syslinux to extlinuxSimon Glass
We use the terms 'distro' to mean extlinux but they are not really the same. 'Distro' could refer to any method of booting a distribution, whereas extlinux is a particular method. Also we sometimes use syslinux, but it is better to use the same term in all cases. Rename distro to syslinux and also update bootstd uses of syslinux to use extlinux instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-05-13board: schneider: add RZN1 board supportRalph Siemsen
Add support for Schneider Electric RZ/N1D and RZ/N1S boards, which are based on the Reneasas RZ/N1 SoC devices. The intention is to support both boards using a single defconfig, and to handle the differences at runtime. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-13ARM: rmobile: Add support for Renesas RZ/N1 SoCRalph Siemsen
The RZ/N1 is a family of SoC devices from Renesas, featuring: * ARM Cortex-A7 CPU (single/dual core) and/or Cortex-M3 * Integrated SRAM up to 6MB * Integrated gigabit ethernet switch * Optional DDR2/3 controller * I2C, SPI, UART, NAND, QSPI, SDIO, USB, CAN, RTC, LCD Add basic support for this family, modeled on the existing RZA1. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-13ARM: dts: add devicetree for Renesas RZ/N1 SoCRalph Siemsen
This is taken directly from Linux kernel 6.3 (commit 457391b0380335d5e9a5babdec90ac53928b23b4) Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-13ARM: armv7: add non-SPL enable for Cortex SMPENRalph Siemsen
Commit 2564fce7eea3 ("sunxi: move Cortex SMPEN setting into start.S") added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For platforms not using SPL boot, add the corresponding non-SPL config, so that CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) works as expected. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-11x86: samus: Don't include audio and SATA in TPLSimon Glass
These are not used in TPL so disable the drivers to save space. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11x86: Simplify cpu_jump_to_64bit_uboot()Simon Glass
This copies the cpu_call64() function to memory address and then jumps to it. This seems to work correctly even when called from SPL, which is running from SPI flash. Drop the copy as it is not needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11spl: Commit MTRRs only in board_init_f_r()Simon Glass
We don't need to commit the SPI-flash MTRR change immediately, since it is now done in the board_init_f_r(). Also this causes chromebook_link64 to hang, presumably since we are still running from CAR (Cache-as-RAM) in SPL. Coral handles this OK, perhaps since it is running from a different memory area, but it has no effect on Coral anyway. Drop the extra mtrr_commit() in the SPL implementation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11x86: spl: Avoid using init_cache_f_r() from SPLSimon Glass
This function is used by U-Boot proper. It does not set up MTRRs when SPL is enabled, but we do want this done when it is called from SPL. In fact it is confusing to use the same function from SPL, since there are quite a few conditions there. All init_cache_f_r() really does is commit the MTRRs and set up the cache. Do this in the SPL's version of this function instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11x86: Tidy up address for loading U-Boot from SPLSimon Glass
Use the binman symbols for this, to avoid hard-coding the value. We could use CONFIG_X86_OFFSET_U_BOOT for the address, but it seems better to obtain the offset and size through the same mechanism. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11x86: spl: Show debugging for BSSSimon Glass
Show the area of memory cleared for BSS, when debugging is enabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11x86: mrc: Correct SPL debug messageSimon Glass
SPL printf() does not normally support %#x so just use %x instead. Hex is expected in U-Boot anyway. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11x86: Tidy up availability of string functionsSimon Glass
For now, just enable the fast-but-large string functions in 32-boot U-Boot proper only. Avoid using them in SPL. We cannot use then in 64-bit builds since we only have 32-bit assembly. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2023-05-11x86: Support debug UART in 64-bit modeSimon Glass
The debug UART is already set up in SPL, so there is no need to do anything here. We must provide the (empty) function though. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11x86: ivybridge: Ensure LPC is available for GPIO baseSimon Glass
The bd82x6x_get_gpio_base() does not work if the LPC is not set up. Probe it early to avoid this problem. In chromebook_link64 this problem shows up as an inability to read the GPIO straps for the memory type. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-05 22:26:16 +0000