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2025-01-02mach-k3: am62a7_init: Add FS and raw mode for eMMCVignesh Raghavendra
This adds FS and raw boot mode support for eMMC similar to other K3 platforms. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-12-31Merge patch series "Fix OSPI boot for J722S"Tom Rini
Prasanth Babu Mantena <p-mantena@ti.com> says: This series fixes OSPI boot for J722S. It contains fixes for DMSC communication, R5 regmap for ospi and dma specific overrides for ospi. Test log: https://gist.github.com/PrasanthBabuMantena/ad469dd09ab7263f85f87dadda46c86d Link: https://lore.kernel.org/r/20241218131341.2073823-1-p-mantena@ti.com
2024-12-31arm: dts: k3-j721e-beagleboneai: Move to OF_UPSTREAMUdit Kumar
Move to using OF_UPSTREAM config and thus using the devicetree subtree and remove unused device tree files. Signed-off-by: Udit Kumar <u-kumar1@ti.com> Acked-by: Sumit Garg <sumit.garg@linaro.org>
2024-12-31arm: dts: k3-am62p-sk-binman: add SE security variant buildsBryan Brattlof
The Texas Instruments Foundational Security (TIFS) firmware must match the security level configured on the SoC. To boot Security Enforced (SE) variants of the AM62Px, add another tiboot3 build which packages the Security Enforced (SE) firmware variant for AM62Px SoCs. Signed-off-by: Bryan Brattlof <bb@ti.com>
2024-12-31arm: dts: k3-j722s*: Add overrides specific to OSPIVaishnav Achath
OSPI Boot requires overrides specific to R5 and also to use DMA in R5 SPL stage the DM_TIFS needs to be used. Add the corresponding overrides for R5 SPL stage. Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Signed-off-by: Prasanth Babu Mantena <p-mantena@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com>
2024-12-31arm: mach-k3: j722_spl: Add FAST XSPI boot modeVaishnav Achath
Fast XSPI boot mode is supported by J722S ROM, add that. Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Signed-off-by: Prasanth Babu Mantena <p-mantena@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com>
2024-12-31arm: dts: k3-j722s-r5-evm: Fix DM2TIFS secproxy thread IDVaishnav Achath
Fix the DM2TIFS secureproxy thread ID as per the latest TISCI documentation for J722S. https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j722s/sec_proxy.html Fixes: fc2da3a3d0d3 ("arm: dts: Introduce J722S U-Boot dts files") Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Signed-off-by: Prasanth Babu Mantena <p-mantena@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com>
2024-12-31Merge patch series "Cumulative fixes and updates for MediaTek ethernet driver"Tom Rini
Weijie Gao <weijie.gao@mediatek.com> says: This patch series contains fixes and updates for mtk_eth driver. Link: https://lore.kernel.org/r/cover.1734406967.git.weijie.gao@mediatek.com
2024-12-31arm: dts: mt7629: fix sgmii clock selection for ethernetWeijie Gao
Setup correct parent of clock CLK_TOP_SGMII_REF_1_SEL to allow sgmiisys1 work correctly. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2024-12-31Merge patch series "Select CONFIG_64BIT for sandbox64 and x86_64"Tom Rini
Andrew Goodbody <andrew.goodbody@linaro.org> says: Picking up a series from Dan Carpenter and applying requested changes for v2. I had previously set CONFIG_64BIT for arm64. This patchset does the same thing for sandbox and x86_64. (Mips and riscv were already doing it). This CONFIG option is used in the Makefile to determine if it's a 32 or 64 bit system for the CHECKER. Makefile 1052 # the checker needs the correct machine size 1053 CHECKFLAGS += $(if $(CONFIG_64BIT),-m64,-m32) Link: https://lore.kernel.org/r/20241216180736.1933807-1-andrew.goodbody@linaro.org
2024-12-31x86: select CONFIG_64BIT for X86_64Andrew Goodbody
Select CONFIG_64BIT so that we pass the -m64 option (instead of -m32) to static analysis tools. Introduce CONFIG_SPL_64BIT and select it for architectures other than x86 with 64 bit builds. Do not select it for x86 builds as x86 uses a 32 bit SPL. Ensure that when limits are set they use CONFIG_64BIT for U-Boot proper and CONFIG_SPL_64BIT for SPL. This is to allow for the 32 bit SPL build used by x86. Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2024-12-31sandbox: select CONFIG_64BIT for sandboxAndrew Goodbody
Select CONFIG_64BIT so that we pass the -m64 option (instead of -m32) to static analysis tools. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2024-12-31sandbox: Correct guard around readq/writeqAndrew Goodbody
In include/linux/io.h the declarations of ioread64 and iowrite64 which make use of readq/writeq are guarded with CONFIG_64BIT so guard the sandbox declarations of readq and writeq also with CONFIG_64BIT. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2024-12-30Merge patch series "Misc. PowerPC MPC83xx fixes/cleanups"Tom Rini
J. Neuschäfer <j.ne@posteo.net> says: This patchset contains a few small fixes/cleanups for the MPC83xx platform. Link: https://lore.kernel.org/r/20241220-mpc83xx-misc-v2-0-ff4c17ee5fa4@posteo.net
2024-12-30powerpc: mpc83xx: Use defined constant for SPCR[TBEN]J. Neuschäfer
To increase readability, use the defined constant instead of specifying SPCR[TBEN] as a number. Reviewed-by: Sinan Akman <sinan@writeme.com> Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
2024-12-30powerpc: mpc83xx: Allow including initreg.h into multiple filesJ. Neuschäfer
Globals defined in headers can result in multiple-definition errors while linking, if they are visible beyond the current translation unit. This hasn't been a problem for initreg.h so far, but would become a problem in the next patch, where I use a constant from initreg.h in a second C file. Reviewed-by: Sinan Akman <sinan@writeme.com> Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
2024-12-30Merge patch series "powerpc: Fix and enforce distinction between immediates ↵Tom Rini
and registers" J. Neuschäfer <j.ne@posteo.net> says: This patchset changes the definition r0 etc. to %r0, so that the assembler can check that registers are only used where expected, and fixes the fallout. Link: https://lore.kernel.org/r/20241212-gpr-checks-v1-0-8c084c5fc0b6@posteo.net
2024-12-30powerpc: Introduce and enforce assembler checks on GPR usageJ. Neuschäfer
PowerPC general-purpose registers are historically specified as plain numbers (0-31), which makes them hard to distinguish from immediates. For this reason, include/ppc_asm.tmpl defines aliases named r0-r31. This can still lead to uncaught mistakes if a register is used in place of a number. Instead of (e.g.) 5 use %r5, which will result in an assembler warning if used as a number. Turn these warnings into errors by passing `--fatal-warnings` to the assembler. I verified with gazerbeam_defconfig (MPC83xx) and qemu-ppce500_defconfig (MPC85xx) that this patch results in the same machine code. Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
2024-12-30powerpc: Fix 0 vs. r0 confusion in X/D-form instructionsJ. Neuschäfer
Instructions such as dcbi are in the X-form; they have RA and RB fields and the effective address (EA) is computed as (RA|0)+(RB). In words, this means that if RA is zero, the left-hand side of the addition is zero, otherwise the corresponding GPR is used. r0 can never be used on the left-hand side of a X-form instruction. For D-form instructions such as addis, the Power ISA illustrates this in the instruction pseudo-code: if RA = 0 then RT <- EXTS(SI || 0x0000) else RT <- (RA) + EXIS(SI || 0x0000) In all of these cases, RA=0 indicates the value zero, not register r0. I verified with gazerbeam_defconfig (MPC83xx) and qemu-ppce500_defconfig (MPC85xx) that this patch results in the same machine code. Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
2024-12-30lmb: Remove lmb_reserve_flags()Ilias Apalodimas
lmb_reserve() is just calling lmb_reserve_flags() with LMB_NONE. There's not much we gain from this abstraction. So let's remove the latter, add the flags argument to lmb_reserve() and make the code a bit easier to follow. Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Tested-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-12-30Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-sh ↵Tom Rini
into next
2024-12-29arm64: dts: renesas: Add R8A779G0 V4H remoteproc DT nodeMarek Vasut
Describe APMU controller as a remoteproc device capable of starting the Cortex-R52 cores in Renesas R8A779G0 V4H SoC DT. The APMU IP is in fact a power management unit capable of additional operations, but those are not used by U-Boot so far. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-29remoteproc: renesas: Add Renesas R-Car Gen4 remote processor driverMarek Vasut
Add R-Car Gen4 APMU controller remoteproc driver capable of starting the Cortex-R52 cores in Renesas R8A779G0 V4H/V4M SoC. The APMU IP is in fact a power management unit capable of additional operations, but those are not used by U-Boot so far. This requires slight adjustment to the SPL entry point code, as that is being executed on the Cortex-R52 #0 and the Cortex-R52 #0 enters an endless loop once it starts the rest of the SPL on Cortex-A76 core. The endless loop now checks for content of APMU CRBARP registers and tests whether valid VLD_BARP and BAREN_VALID bits are set, if so, the Cortex-R52 core exits the endless loop and jumps to address started in CRBARP[31:18] register in ARM mode, which is a trampoline code to jump to the final entry point. The trampoline code is in place to avoid limitation of CRBARP[31:18] address field, which limits the core start address to memory addresses aligned to 0x40000 or 256 kiB . The trampoline is placed at 0x40000 aligned address and jumps to the final entry point, which can be at an address with arbitrary alignment at instruction granularity. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-29arm64: dts: renesas: Drop OF_UPSTREAM conversion remnantMarek Vasut
This DTC_FLAGS assignment is no longer necessary as all R-Car Gen2/Gen3/Gen4 platforms have been converted to OF_UPSTREAM and matching DTC_FLAGS assignment is present in dts/upstream/src/arm64/Makefile . Drop the remnant. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-29arm64: renesas: Align configuration headersMarek Vasut
Align R-Car Gen2/Gen3/Gen4 configuration header file to look basically the same way across these three SoC generations. There are subtle difference between the remaining bits in those files across SoC generations, but the common bits are now aligned. There is not much left in those headers either, most of the configuration is now converted to Kconfig. Specifically for R-Car Gen3, GIC registers have been moved to architecture specific header file rcar-gen3-base.h , the rest of the changes here are comment changes and indentation changes. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-29arm64: renesas: Add Renesas R-Car V4H SPL implementationMarek Vasut
Add support for building U-Boot SPL for Renesas R-Car Gen4 R8A779G0 V4H SoC. The SPL initializes the DBSC5 DRAM controller, RT-VRAM and loads and starts U-Boot proper on the Cortex-A76 core. The SoC BootROM can not boot the CA76 core directly, instead the SPL starts on the CR52 core which immediately brings up the CA76 core, which in turn starts executing the actual SPL. This is achieved by placing a tiny bit of precompiled Aarch32 code at the very beginning of the SPL. The code consists of some 32 instructions, uses APMU to configure CA76 start address to offset 0x80 Bytes from start of the SPL, and uses APMU to start the CA76 core. The code parts the CR52 core in an endless loop once the CA76 core got started. The 32 instructions are completely arbitrary number, so is the offset 0x80 Bytes from start of SPL, because 0x80 = 128 decimal and 128 / 4 bytes per instruction is 32 instructions. The 32 instructions turned out to be enough to started the CA76 and 0x80 is nicely aligned. Once the SPL completes hardware initialization, the SPL loads U-Boot proper. The u-boot.itb proper fitImage contains 64bit build on u-boot-nodtb.bin and a DT for R8A779G0 V4H White Hawk board and is generated by binman. The u-boot.itb is loaded from SPI NOR offset 0x80000. In order to install this setup on an existing R8A779G0 V4H White Hawk board, build using r8a779g0_whitehawk_defconfig, generate SPI NOR image flash.bin and write flash.bin to SPI NOR offset 0x0 . Finally, configure board MD pin switches according to the R8A779G0 V4H White Hawk board documentation for 40 MHz SPI NOR boot using DMA and restart the board. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-29arm64: renesas: Make stub PSCI implementation available on 64bit R-Car SoCsMarek Vasut
Make the R-Car V3U stub PSCI implementation available on 64bit R-Car SoCs. This implementation is useful during early board bring up, where it can supplant missing fully-featured PSCI implementation. Note that this PSCI implementation is very basic and offers only SoC reset functionality. It is unable to enable or disable secondary CPU cores nor does it offer any suspend/resume functionality. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-29arm64: dts: renesas: Add R8A779G0 V4H DBSC5 and RT-VRAM DT nodesMarek Vasut
Describe DBSC5 DRAM controller and RT-VRAM configuration interface as two new DT nodes in R-Car Gen4 R8A779G0 U-Boot DT extras file. This node is used by the U-Boot SPL for R8A779G0 SoC, where the DBSC5 and RT-VRAM drivers bind to these nodes and bring up the DRAM controller and RT-VRAM settings respectively, so U-Boot proper can be loaded into DRAM and started on Cortex A76 core. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-28test/cmd/wget: fix the testMikhail Kshevetskiy
Changes: * update to new tcp stack * fix zero values for ISS and IRS issue (see RFC 9293) Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Reviewed-by: Simon Glass <sjg@chromium.org>
2024-12-27board: gateworks: venice: rename GW7905 to GW7500Tim Harvey
The GW7905 was renamed to GW7500 before release. Change the various names in the dt files and references. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2024-12-25Merge tag 'v2025.01-rc5' into nextTom Rini
Prepare v2025.01-rc5
2024-12-23imx: Use per board ddrphy_trained_csrPeng Fan
Drop global ddrphy_trained_csr which maybe different with per board ddrphy_trained_csr. DDR TOOL generates ddrphy_trained_csr for each board, using the global ddrphy_trained_csr has risk that values may be not up to date. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-12-23arm: dts: imx8mp-venice-gw7*xx: fix TPM resetTim Harvey
With an IMX8MP based SOM the SPI RST is gpio4_9 instead of gpio1_11. Fix this. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2024-12-19imx: Fix usable memory ranges for imx8m SOCsIlias Apalodimas
commit e27bddff4b97 ("imx8m: Restrict usable memory to space below 4G boundary") tried to adjust the usable memory limits on a 4GB boundary. ram_top is described as 'top address of RAM used by U-Boot' and we want to preserve that. This is defined as a phys_addr_t and unfortunately its size differs across architectures. This has lead us to a weird state where 32bit boards define it 'SZ_4GB - 1' and 64bit boards as 'SZ_4GB' unless it was otherwise defined. With some recent LMB changes and specifically commit 1a48b0be93d4 ("lmb: prohibit allocations above ram_top even from same bank") the board fails to boot properly although the commit above is correct since it's making sure that no memory above ram_top is usable -- but added to our memory map so EFI can hand it over to the booted OS. The reason for that is that during the LMB init we add all usable memory in lmb_add_memory(). In that function any memory above ram_top gets added as 'reserved' for LMB. With the current values tha's set to 0xFFFF_FFFF for this board. Later LMB is trying to protect the memory area U-Boot lives in with lmb_reserve_common(). The latter fails though since it tries to add U-Boot top (which is 0xFFFF_FFFF as well) to U-Boot 'bottom'. This call will fail since 1 byte of that memory range is already marked as 'reserved'. Since we are close to the release, LMB seems to assume that the address is rounded up and is the 'next address' and so does parsing and adding memory ranges from DT files, bump the ram_top of the board by 1byte. In the long run we should change all of the above and have 32b and 64b platforms define ram_top identically. Add a Fixes tag although the commit is correct, so people can figure out the broken scenarios in the future. Suggested-by: Sughosh Ganu <sughosh.ganu@linaro.org> Fixes: commit 1a48b0be93d4 ("lmb: prohibit allocations above ram_top even from same bank") Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reported-by: João Paulo Gonçalves <jpaulo.silvagoncalves@gmail.com> Closes: https://lore.kernel.org/all/20241216114231.qpfwug3zfqkxn3d5@joaog-nb.corp.toradex.com/ Reviewed-by: Peng Fan <peng.fan@nxp.com> Fixes: 74f88b72219e ("ARM: imx: imx8m: Fix board_get_usable_ram_top()")
2024-12-18arch: x86: lib: Add support of legacy 64-bit entry point at 0x200Paul HENRYS
Support of legacy 64-bit entry point was already present when booting a bzimage with 'zboot' but not supported with 'bootm' when the x86_64 Linux kernel is embedded in a FIT image. Signed-off-by: Paul HENRYS <paul.henrys_ext@softathome.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2024-12-18fdt: Swap the signature for board_fdt_blob_setup()Simon Glass
This returns a devicetree and updates a parameter with an error code. Swap it, since this fits better with the way U-Boot normally works. It also (more easily) allows leaving the existing pointer unchanged. No yaks were harmed in this change, but there is a very small code-size reduction. For sifive, the OF_BOARD option must be set for the function to be called, so there is no point in checking it again. Also OF_SEPARATE is defined always. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Matthias Brugger <mbrugger@suse.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> [trini: Update total_compute] Signed-off-by: Tom Rini <trini@konsulko.com>
2024-12-18Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-riscv ↵Tom Rini
into next CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/23926 - Board: Support LicheeRV Nano - Board: Support bananapi-f3 - Board: Switch to OF_UPSTREAM for StarFive JH7110 - Board: Add sdhci driver for TH1520 SoC
2024-12-18ARM: dts: stm32: Reinstate missing root oscillators on DH STM32MP15xx DHCORMarek Vasut
The root oscillators reference used to be in rcc node since 3d15245502c4 ("ARM: dts: stm32mp1: explicit clock reference needed by RCC clock driver") however this is not part of upstream stm32mp151.dtsi . The RCC driver does need this reference, reinstate it locally. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2024-12-18ARM: dts: stm32: Reinstate missing root oscillators on STM32MP15xxMarek Vasut
The root oscillators reference used to be in rcc node since 3d15245502c4 ("ARM: dts: stm32mp1: explicit clock reference needed by RCC clock driver") however this is not part of upstream stm32mp151.dtsi . The RCC driver does need this reference, reinstate it globally. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
2024-12-18riscv: spacemit: bananapi_f3: initial support addedKongyang Liu
Add basic support for SpacemiT's Banana Pi F3 board. Update the k1.dtsi align with mainline. Note that the device tree files follow the mainline Linux source[1]. Links: https://patches.linaro.org/project/linux-serial/patch/20240730-k1-01-basic-dt-v5-8-98263aae83be@gentoo.org/ [1] Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> Signed-off-by: Huan Zhou <pericycle.cc@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Yixun Lan <dlan@gentoo.org> Tested-by: Marcel Ziswiler <marcel@ziswiler.com>
2024-12-18riscv: dts: t-head: Add sdhci and emmc nodesMaksim Kiselev
Add SDHCI and EMMC controlles nodes on TH-1520 SoC. And enable them for Lichee module 4A. Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
2024-12-18riscv: cpu: jh7110: Sort the list of imply statementsHal Feng
The imply statements should be sorted in the sequence of appearance in .config. Tested-by: Anand Moon <linux.amoon@gmail.com> Tested-by: E Shattow <lucent@gmail.com> Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2024-12-18riscv: dts: jh7110: Support multiple DTBs in a Fit imageHal Feng
Support multiple DTBs for JH7110 based boards, so they can select the correct DT at runtime. Tested-by: Anand Moon <linux.amoon@gmail.com> Tested-by: E Shattow <lucent@gmail.com> Reviewed-by: E Shattow <lucent@gmail.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2024-12-18riscv: dts: jh7110: Add u-boot device tree for JH7110 based boardsHal Feng
To support the other JH7110 based boards, add u-boot device tree for them. Tested-by: Anand Moon <linux.amoon@gmail.com> Tested-by: E Shattow <lucent@gmail.com> Reviewed-by: E Shattow <lucent@gmail.com> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de> Cc: H Bell <dmoo_dv@protonmail.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2024-12-18riscv: dts: jh7110: Move common code to the new jh7110-common-u-boot.dtsiHal Feng
To support JH7110 based boards besides v1.3B, add a common dtsi and add common code to it. Tested-by: Anand Moon <linux.amoon@gmail.com> Tested-by: E Shattow <lucent@gmail.com> Reviewed-by: E Shattow <lucent@gmail.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2024-12-18riscv: dts: jh7110: Make u-boot device trees adapting to upstream DTHal Feng
Add u-boot features to the U-Boot device tree. Tested-by: Anand Moon <linux.amoon@gmail.com> Tested-by: E Shattow <lucent@gmail.com> Reviewed-by: E Shattow <lucent@gmail.com> Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2024-12-18dts: starfive: Switch to using upstream DTHal Feng
Enable OF_UPSTREAM to use upstream DT and add starfive/ prefix to the DEFAULT_DEVICE_TREE. Rename jh7110-starfive-visionfive-2-u-boot.dtsi to jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi and set the v1.3b device tree as the default device tree. Drop redundant DT files from arch/riscv/dts/ and redundant clock and reset definitions from include/dt-bindings/. Since the old clock definitions is a little different from those in upstream Linux, update the clock definitions in clock drivers accordingly. Tested-by: Anand Moon <linux.amoon@gmail.com> Tested-by: E Shattow <lucent@gmail.com> Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2024-12-18board: add support for LicheeRV NanoThomas Bonnefille
The LicheeRV Nano is a small SBC using the Sophgo SG2002 RISCV SoC. Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
2024-12-18riscv: dts: sophgo: add device tree for LicheeRV NanoThomas Bonnefille
Import a slightly modified version of the LicheeRV Nano and SG2002 device trees from the Linux Kernel. The current supported IPs are UART, MMC, Timer, PLIC and CLINT. Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
2024-12-17Merge tag 'u-boot-imx-next-20241217' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/23877 - Add support for Apalis iMX8 1300MHz version. - Don't advertise Gbit on (R)MII on the FEC controller. - Fix srktool -c usage by removing spaces.