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2022-09-20arm: mvebu: theadorable: Update eth & mdio DT nodesStefan Roese
With the recent changes in the Marvel mvneta network driver, the MDIO bus is not connected any more. This patch updates the DT nodes to use the nodes from the dtsi files instead of creating ad-hoc nodes. Signed-off-by: Stefan Roese <sr@denx.de>
2022-09-19Merge branch 'master' into nextTom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-09-19Merge tag 'u-boot-imx-20220919' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20220919 ------------------- CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/13500 - Fix imx8mn-beacon-kit-u-boot - Merged Purism - imxrt1170 (already merged in u-boot-imx) - Fixes in crypto FSL - Toradex : fixes Verdin - Serial Driver: fixes when not used as console - DH Boards : fixes + USB - Fix CONFIG_SYS_MALLOC_F_LEN (Kconfig) - Add imx6ulz_smm_m2
2022-09-19powerpc: mpc85xx: Fix incorrect application of patchMarek Behún
I messed up application of patch 5a428e751044 ("mmc: fsl_esdhc_spl: Add support for builds without CONFIG_SYS_MMC_U_BOOT_OFFS"). I took it from a work-in-progress branch where I changed usage of CONFIG_SDCARD to CONFIG_SD_BOOT and refactored SYS_MPC85XX_NO_RESETVEC mess. But these changes aren't in master yet. Fix the wrong usage of these macros. Fixes: 5a428e751044 ("mmc: fsl_esdhc_spl: Add support for builds without CONFIG_SYS_MMC_U_BOOT_OFFS") Signed-off-by: Marek Behún <kabel@kernel.org> Reviewed-by: Pali Rohár <pali@kernel.org>
2022-09-18bsh: imx6ulz_smm_m2: Add imx6ulz BSH SMM M2 boardsMichael Trimarchi
Introduce BSH SystemMaster (SMM) M2 board family, which consists of: imx6ulz SMM M2 and imx6ulz SMM M2 PRO boards. Add support for imx6ulz BSH SMM M2 board: - 128 MiB DDR3 RAM - 256MiB Nand - USBOTG1 peripheral - fastboot. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-09-18board: purism: add the Purism Librem5 phoneAngus Ainslie
Initial commit of Librem5 u-boot and SPL Signed-off-by: Angus Ainslie <angus@akkea.ca> Co-developed-by: Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm> Signed-off-by: Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm> Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-09-18ARM: dts: imx: Fix I2C5 GPIO assignment on i.MX8M Plus DHCOMMarek Vasut
Fix copy-paste error of the I2C5 bus recovery GPIO assignment, the I2C5 GPIOs are on gpio3 instead of gpio5. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: uboot-imx <uboot-imx@nxp.com>
2022-09-18ARM: dts: imx: Adjust ECSPI1 pinmux on i.MX8M Plus DHCOMMarek Vasut
The ECSPI1 is on I2C1/I2C2 pins of the SoC, update the pinmux accordingly. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: uboot-imx <uboot-imx@nxp.com>
2022-09-18ARM: dts: imx: Rename imx8mp-dhcom{-pdk2,}-boot.dtsiMarek Vasut
Rename imx8mp-dhcom-pdk2-u-boot.dtsi to imx8mp-dhcom-u-boot.dtsi, since this file is shared by PDK2, PicoITX and DRC02. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: uboot-imx <uboot-imx@nxp.com>
2022-09-18ARM: dts: imx: Add SoM compatible to i.MX8M Plus DHCOM PDK2Marek Vasut
Add SoM compatible string into i.MX8MP DHCOM PDK2 compatible strings. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: uboot-imx <uboot-imx@nxp.com>
2022-09-18ARM: dts: imx: Drop Atheros PHY header from i.MX8M Plus DHCOM PDK2Marek Vasut
This PHY is not used on PDK2, the header was added due to copy-paste error, drop it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: uboot-imx <uboot-imx@nxp.com>
2022-09-18ARM: dts: imx: Add HW variant details to i.MX8M Plus DHCOM PDK2Marek Vasut
Add information about which exact SoM variant is used on which PDK2 variant. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: uboot-imx <uboot-imx@nxp.com>
2022-09-18arm: dts: imx8mn-beacon-kit-u-boot: Fix broken bootingAdam Ford
When the imx8mm.dtsi file was pulled in from Linux, the UARTs were moved into an spba sub-node which wasn't being included in the SPL device tree. This meant the references to the UART weren't being handled properly and when booting the system would constantly reboot. Fix this by adding the spba node to the spl device tree to restore normal booting. Fixes: 4e5114daf9eb ("imx8mn: synchronise device tree with linux") Signed-off-by: Adam Ford <aford173@gmail.com>
2022-09-18imx: romapi: fix spurious ampersand in address printMarcel Ziswiler
Fix spurious ampersand in address print e.g. Find img info 0x&480331a0, size 855 Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>"
2022-09-18ARM: dts: imx: add i.MXRT1170-EVK supportJesse Taube
The NXP i.MXRT1170 Evaluation Kit (EVK) provides a platform for rapid evaluation of the i.MXRT, which features NXP's implementation of the Arm Cortex-M7 and Cortex-M4 core. The EVK provides 64 MB SDRAM, Micro SD card socket, USB 2.0 OTG. This patch aims to support the preliminary booting up features as follows: GPIO LPUART SD/MMC SDRAM Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
2022-09-18ARM: dts: imxrt11170-pinfunc: Add pinctrl binding headerJesse Taube
Add binding header for i.MXRT1170 pinctrl device tree. Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
2022-09-18imx: imxrt1170-evk: Add support for the NXP i.MXRT1170-EVKJesse Taube
This commit adds board support for i.MXRT1170-EVK from NXP. This board is an evaluation kit provided by NXP for i.MXRT117x processor family. Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
2022-09-18watchdog: Get rid of ASSEMBLY hacksStefan Roese
Only one occurance of WATCHDOG_RESET is left in one assembler file. This patch changes this occurance to a direct call to watchdog_reset and then removes all the ASSEMBLY ifdef'ery in watchdog.h, as it's not needed any more to clean this mess a bit up. Signed-off-by: Stefan Roese <sr@denx.de> Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm]
2022-09-18cyclic: Use schedule() instead of WATCHDOG_RESET()Stefan Roese
Globally replace all occurances of WATCHDOG_RESET() with schedule(), which handles the HW_WATCHDOG functionality and the cyclic infrastructure. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm]
2022-09-16mmc: fsl_esdhc_spl: Add support for builds without CONFIG_SYS_MMC_U_BOOT_OFFSPali Rohár
When fixed offset via CONFIG_SYS_MMC_U_BOOT_OFFS is not specified then expects that U-Boot proper is placed immediately after SPL without any additional padding. This allows to generate smaller SPL+U-Boot final binary as it is not required to specify fixed offset to U-Boot proper at SPL compile time. In this case offset to U-Boot proper is calculated at SPL compile time in linker script. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Marek Behún <kabel@kernel.org>
2022-09-16powerpc: mpc85xx: Fix loading U-Boot proper from SD card in SPLPali Rohár
Change 8-byte alignment of SPL binary to just 4-byte alignment as objcopy trims trailing zero bytes when converting ELF file to RAW binary. This is same fix for SPL linker script as was done fix for U-Boot linker script in commit e8c0e0064c8a ("powerpc: mpc85xx: Fix CONFIG_OF_SEPARATE support"). It is required for the patch "mmc: fsl_esdhc_spl: Add support for builds without CONFIG_SYS_MMC_U_BOOT_OFFS" which triggered this issue in SPL. Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org>
2022-09-16powerpc: mpc85xx: Fix check for CONFIG_SDCARDMarek Behún
Commit d433c74eecdc ("Convert CONFIG_SDCARD et al to Kconfig") converted SYS_EXTRA_OPTIONS=SDCARD or SPIFLASH to config options CONFIG_SDCARD and CONFIG_SPIFLASH, but left one occurance unchanged. Fix this. Fixes: d433c74eecdc ("Convert CONFIG_SDCARD et al to Kconfig") Signed-off-by: Marek Behún <kabel@kernel.org> Reviewed-by: Pali Rohár <pali@kernel.org>
2022-09-16Makefile: Reduce usage of custom mpc85xx u-boot.bin targetPali Rohár
Building of final u-boot.bin binary for mpc85xx via binman is needed only when inserting DTB binary in the middle of the u-boot ELF binary (before .bootpg and .resetvec ELF sections). These requirements are met when CONFIG_MPC85XX_HAVE_RESET_VECTOR is enabled (= generating .bootpg/.resetvec sections) and CONFIG_OF_SEPARATE is enabled (= inserting DTB binary). So in all other cases use standard build procedure instead of custom mpc85xx u-boot.bin Makefile target via binman. Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org>
2022-09-16Makefile: Build final mpc85xx non-SPL image in standard file u-boot.binPali Rohár
Currently Makefile produces final mpc85xx image when SPL is not used in custom file u-boot-with-dtb.bin. It is quite confusing name as build process produce also intermediate file standard file u-boot-dtb.bin (which is just intermediate and not bootable). Other platforms use u-boot.bin (UBOOT_BIN) as standard name for final bootable raw image. So change Makefile rules and binman to produce final bootable file for mpc85xx also into file u-boot.bin. There is just need for mpc85xx to not define default rule for u-boot.bin then instruct binman (via DTS file) to store final image into u-boot.bin (instead of u-boot-with-dtb.bin) and finally rename target u-boot-with-dtb.bin to u-boot.bin. With this change are also removed custom Makefile hacks for mpc85xx that it produced non-standard output file. And also updated documentation. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Marek Behún <kabel@kernel.org>
2022-09-16blk: Switch over to using uclass IDsSimon Glass
We currently have an if_type (interface type) and a uclass id. These are closely related and we don't need to have both. Drop the if_type values and use the uclass ones instead. Maintain the existing, subtle, one-way conversion between UCLASS_USB and UCLASS_MASS_STORAGE for now, and add a comment. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-16sandbox: Avoid defining HAVE_BLOCK_DEVICE in KonfigSimon Glass
This is not needed as it is implied or selected by other options anyway. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-16blk: Enable CONFIG_BLK for all mediaSimon Glass
Enable this option on all boards which support block devices. Drop the related depencies on BLK since these are not needed anymore. Disable BLOCK_CACHE on M5253DEMO as this causes a build error. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-15brppt1: Cleanup device treeBernhard Messerklinger
* Remove unnecessary device tree nodes which are not needed in U-Boot directly. * Move all U-Boot specific device tree properties to u-boot dtsi. Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2022-09-15brppt1: Fix SPL boot stageBernhard Messerklinger
Commit 6337d53fdf45 ("arm: dts: sync am33xx with Linux 5.9-rc7") syncs the am335x device tree with the latest linux kernel am335x device tree. That causes problems with device tree in SPL stage. To fix the issues CONFIG_SPL_OF_TRANSLATE must be set to handle the synced bus addresses correctly. A custom U-Boot device tree is also needed since the SPL build removes bus properties from bus nodes which are not explicitly marked with the u-boot,dm-spl or u-boot,dm-pre-reloc flag. Therefore all parent buses of the in the SPL needed devices must be marked with u-boot,dm-pre-reloc. Also since there is no driver for "ti,sysc" compatible property in SPL the buses marked with this compatible string must also be marked with compatible = "simple-bus" to make the underlying devices visible in SPL. Otherwise the matching device drivers aren't found and the uclass drivers are dropped. Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2022-09-15brppt1: Remove unused board variantsBernhard Messerklinger
The SPI and NAND board variants never went into production. Drop those board variants. Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2022-09-14dm: core: Add functions to read 8/16-bit integersStefan Herbrechtsmeier
Add functions to read 8/16-bit integers like the existing functions for 32/64-bit to simplify read of 8/16-bit integers from device tree properties. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-09-14Add in the ability to load and boot an uncompressed kernel image during the ↵Nathan Barrett-Morrison
Falcon Mode boot sequence. This is required for architectures which do not support compressed kernel images (i.e. ARM64). This is only used while not booting via FIT image. Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2022-09-13arm: dts: aspeed: Update SPI flash node settingsChin-Ting Kuo
For both AST2500 and AST2600, there are three SPI controllers, FMC(Firmware Memory Controller), SPI1 and SPI2. The clock source is HCLK. Following is the basic information for ASPEED SPI controller. AST2500: - FMC: CS number: 3 controller reg: 0x1e620000 - 0x1e62ffff decoded address: 0x20000000 - 0x2fffffff - SPI1: CS number: 2 controller reg: 0x1e630000 - 0x1e630fff decoded address: 0x30000000 - 0x37ffffff - SPI2: CS number: 2 controller reg: 0x1e631000 - 0x1e631fff decoded address: 0x38000000 - 0x3fffffff AST2600: - FMC: CS number: 3 controller reg: 0x1e620000 - 0x1e62ffff decoded address: 0x20000000 - 0x2fffffff - SPI1: CS number: 2 controller reg: 0x1e630000 - 0x1e630fff decoded address: 0x30000000 - 0x3fffffff - SPI2: CS number: 3 controller reg: 0x1e631000 - 0x1e631fff decoded address: 0x50000000 - 0x5fffffff Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
2022-09-13xilinx: Fix mdio bus description for vck190-scMichal Simek
Current behavior is that eth_phy_get_mdio_bus Net: FEC: can't find phy-handle ZYNQ GEM: ff0b0000, mdio bus ff0b0000, phyaddr 0, interface sgmii eth0: ethernet@ff0b0000 Net: ZYNQ GEM: ff0b0000, mdio bus ff0b0000, phyaddr 0, interface sgmii eth0: ethernet@ff0b0000 Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/5b7da5808136b3f579c0cf7a3431b56c758655e9.1662460749.git.michal.simek@amd.com
2022-09-13ARM: zynq: DT: List OCM memoryMichal Simek
Description OCM with mmio-sram driver. In 99% use cases OCM is mapped high that's why it is placed on fixed location. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/a951dbe885640197efe3e91bb9fa5caedb54b387.1662460712.git.michal.simek@amd.com
2022-09-13ARM: zynq: Align qspi node name with Linux kernelMichal Simek
Nodes should follow generic rules where compatible and reg properties should be listed on the top of node. That's why sync it up. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/922dca6227cb0aa4f79e6d3595c5f280ba020684.1662460540.git.michal.simek@amd.com
2022-09-13arm64: versal: Define zynqmp_mmio_write() for versalMichal Simek
GQSPI driver is using it but this function is never called for Versal because it is removed by linker. But function should be declared to avoid this build warning: drivers/spi/zynqmp_gqspi.c: In function 'zynqmp_qspi_set_tapdelay': drivers/spi/zynqmp_gqspi.c:378:3: warning: implicit declaration of function 'zynqmp_mmio_write' [-Wimplicit-function-declaration] 378 | zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST, Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20220825125906.11581-3-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13microblaze: add arch_print_bdinfo() implementationOvidiu Panait
Allow bdinfo command to print icache/dcache information: U-Boot-mONStR> bdinfo boot_params = 0x00000000 DRAM bank = 0x00000000 -> start = 0x04000000 -> size = 0x04000000 flashstart = 0x00000000 flashsize = 0x00000000 flashoffset = 0x00000000 baudrate = 9600 bps relocaddr = 0x07f76000 reloc off = 0x02f76000 Build = 32-bit current eth = unknown ethaddr = (not set) IP addr = <NULL> fdt_blob = 0x07fec7e0 new_fdt = 0x00000000 fdt_size = 0x00000000 lmb_dump_all: memory.cnt = 0x1 memory[0] [0x4000000-0x7ffffff], 0x04000000 bytes flags: 0 reserved.cnt = 0x1 reserved[0] [0x7e94b8c-0x7ffffff], 0x0016b474 bytes flags: 0 devicetree = embed icache = 32 KiB icache line = 4 Bytes dcache = 32 KiB dcache line = 4 Bytes Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220829170205.1274484-4-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13ARM: zynq: Align bss and end of u-boot image to 64bitsMichal Simek
The main reason is that DT memory reserved code is expecting DT to be 64bit aligned. For more information take a look at commit 5bd5ee02b23b ("xilinx: zynqmp: Check that DT is 64bit aligned"). Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/9f3688cda188d8ea0b462df2aa08a10ddcc9c149.1661938136.git.michal.simek@amd.com
2022-09-13arm64: zynqmp: add ref_clk property for REFCLKPER calculationPiyush Mehta
Added ref_clk 'ref' property for GUCTL_REFCLKPER and GFLADJ_REFCLK_FLADJ calculation. This property configure correct value for SOF/ITP counter and period of ref_clk. This patch adds 'ref' property for both dwc3_0 and dwc3_1 cores. Signed-off-by: Piyush Mehta <piyush.mehta@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/417545b948ea12a9301a5e80851f98523be2b443.1661259809.git.michal.simek@amd.com
2022-09-13arm64: zynqmp: Add missing tca6416 to zynqmp SCMichal Simek
Add missing tca6416 i2c gpio controller to SC dts file. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/a19c191d0dffb213d9dc8809d22728d79cf73a22.1661259623.git.michal.simek@amd.com
2022-09-13arm: dts: Add xlnx prefix to GEM compatible stringHarini Katakam
cdns,zynq/zynqmp were recentle deprecated in Linux in favour of xlnx prefix. Add this new compatible string and retain the existing string for compatibility with uboot drivers. Signed-off-by: Harini Katakam <harini.katakam@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/a38b1b55132fc026cc09224dba61e42fd03b1a36.1661259558.git.michal.simek@amd.com
2022-09-13arm64: zynqmp: Add mtd partition for secure OS storage areaAmit Kumar Mahapatra
Update MTD partitions of Kria device trees to allocate 128KB of QSPI memory for secure OS. Increased "SHA256" partition size & changed starting address of "User" partition to accommodate the new partition "Secure OS Storage" Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/9cc64b8c731d11439de73d0af54c65080068f00b.1661242681.git.michal.simek@amd.com
2022-09-13arm: mvebu: Fix moving internal registersPali Rohár
Commit 5bb2c550b11e ("arm: mvebu: Move internal registers in arch_very_early_init() function") moved code from file cpu.c to lowlevel.c, which moves Marvell internal registers from address INTREG_BASE_ADDR_REG to SOC_REGS_PHY_BASE. But the steps describing how to do it correctly were documented only in older U-Boot versions and commit cefd764222ee ("arm: mvebu: Fix internal register config on A38x") probably unintentionally removed important details about MMU from code comments around. Commit 5bb2c550b11e ("arm: mvebu: Move internal registers in arch_very_early_init() function") implemented code movement according to (now incomplete) comments which resulted in semi-broken code. The result is that I-cache is currently disabled for all Armada 38x boards and maybe there are some other (unreported / undetected) issues. Reimplement it correctly. First flush all caches, then disable MMU and L2 cache and then move Marvell internal registers. There is no need to explicitly disable I-cache. After this change lzmadec command with lzma image of 0x7000000 bytes is doing decompression just 5 seconds. Before this change it was 30 seconds. To make lowlevel.S code more readable, extend asm/pl310.h header file to be compatible with assembler and use macros from this file. Fixes: 5bb2c550b11e ("arm: mvebu: Move internal registers in arch_very_early_init() function") Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-09-13arm: mvebu: Enable L2 cache also on Armada 38xPali Rohár
For some unknown reason when L2 cache is disabled on Armada 385 then loadb, loadx and loady commands do not work with higher baudrates than 115200 (they just abort transfer) and lzmadec command with lzma image of size 0x7000000 (maybe even smaller, we tested this one) is doing decompression for more than 2 minutes. After enabling L2 cache decompression takes only 30s and loadb, loadx and loady are stable and working fine. git bisect identified problematic commit 3308933d2fe9 ("arm: mvebu: Avoid reading MVEBU_REG_PCIE_DEVID register too many times"). Before this commit above issues were not present. But investigation showed that above issue was possible to reproduce also by reverting that commit and forcing compiler to do inline optimization of mvebu_soc_family() function. Which seems that the root of this issue is in caches and position of instruction of segments. So currently it is unknown what is or was broken, but code movement, code inlining or other compiler optimization triggered it. Commit 3e5ce7ceeb94 ("arm: mvebu: Enable L2 cache on Armada XP") mentioned that enabling L2 cache on Armada XP improved performance and that Armada 38x has L2 disabled (which is default state) and if needed it has to be enabled in separate patch. As enabling L2 cache also improve performance on Armada 38x, enable it. Note that Aurora cache in no outer mode is available only on Armada XP, hence it is not touched for Armada 38x code. Fixes: 3308933d2fe9 ("arm: mvebu: Avoid reading MVEBU_REG_PCIE_DEVID register too many times") Reported-by: Marek Behún <kabel@kernel.org> Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-09-13arm: mvebu: lowlevel.S: Use CR_M from asm/system.hPali Rohár
Replace magic constant 1 when disabling MMU by macro CR_M from include header file asm/system.h. Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-09-13arm: mvebu: Guard non-AXP code by checking for AXPPali Rohár
Commit c86d53fd88df ("arm: mvebu: Don't disable cache at startup on Armada XP at all") introduced branch for non-AXP code which was guarded by A38X condition. Fix this issue by checking for AXP platform, not by A38X. Fixes: c86d53fd88df ("arm: mvebu: Don't disable cache at startup on Armada XP at all") Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-09-13arm: mvebu: Fix function enable_cachesPali Rohár
Commit 3308933d2fe9 ("arm: mvebu: Avoid reading MVEBU_REG_PCIE_DEVID register too many times") broke support for caches on all Armada SoCs. Before that commit there was code: if (mvebu_soc_family() != MVEBU_SOC_A375) { dcache_enable(); } And after that commit there is code: if (IS_ENABLED(CONFIG_ARMADA_375)) { dcache_enable(); } Comment above this code says that d-cache should be disabled on Armada 375. But new code inverted logic and broke Armada 375 and slowed down all other Armada SoCs (including A38x). Fix this issue by changing logic to: if (!IS_ENABLED(CONFIG_ARMADA_375)) { dcache_enable(); } Which matches behavior prior that commit. Fixes: 3308933d2fe9 ("arm: mvebu: Avoid reading MVEBU_REG_PCIE_DEVID register too many times") Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-09-13arm: mvebu: Mark constant data with const keywordPali Rohár
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-09-12zynq: Convert arm twd timer to DM driverStefan Herbrechtsmeier
Move arm twd timer driver from zynq to generic location. DM timer drivers are designed differently to original driver. Timer is counting up and not down. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220805061629.1207-1-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
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