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2021-06-18stm32mp: stm32prog: solve compilation with CONFIG_FIT_SIGNATUREPatrick Delaunay
When CONFIG_FIT_SIGNATURE is activated, CONFIG_LEGACY_IMAGE_FORMAT is deactivated and the define IMAGE_FORMAT_LEGACY don't exist with include/image.h: #if defined(CONFIG_LEGACY_IMAGE_FORMAT) #define IMAGE_FORMAT_LEGACY 0x01 /* legacy image_header based format */ #endif This patch adds the needed check on compilation flag CONFIG_LEGACY_IMAGE_FORMAT to avoid the compilation error for command stm32prog: cmd_stm32prog.c:81:8: error: ‘IMAGE_FORMAT_LEGACY’ undeclared (first use in this function); did you mean ‘IMAGE_FORMAT_FIT’? 81 | if (IMAGE_FORMAT_LEGACY == | ^~~~~~~~~~~~~~~~~~~ | IMAGE_FORMAT_FIT Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18stm32mp: stm32prog: add support of initrd in flashlayoutPatrick Delaunay
Add the support in command stm32prog of kernel load and start with initrd file, identify by the partition Type "Binary" in the flashlayout.tsv, for example: - 0x01 fsbl Binary none 0x0 tfa.stm32 - 0x03 fip Binary none 0x0 fip.bin P 0x10 kernel System ram0 0xC2000000 uImage.bin P 0x11 dtb FileSystem ram0 0xC4000000 board.dtb P 0x12 initrd Binary ram0 0xC4400000 <initrd> The <initrd> file can be a legacy image "uInitrd", generated with mkimage, or a RAW initrd image "initrd.gz". After a DFU detach the bootm command with be executed with the associated address, for example: $> bootm 0xC2000000 0xC4400000:<size> 0xC4000000 When the "Binary" partition type is absent, the 'bootm' command starts the kernel without ramdisk, for example: $> bootm 0xC2000000 - 0xC4000000 With this paths, it is no more mandatory to generate FIT including the kernel, DT and initrd: - 0x01 fsbl Binary none 0x0 tfa.stm32 - 0x03 fip Binary none 0x0 fip.bin P 0x10 fit System ram0 0xC2000000 fit.bin Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18stm32mp: stm32prog: add timeout in stm32prog_serial_get_bufferPatrick Delaunay
Handle timeout in stm32prog_serial_get_buffer to sent NACK to STM32CubeProgrammer when the buffer is not fully received. This patch avoids to reach the STM32CubeProgrammer timeout and the associated unrecoverable error. Timeout error occurred while waiting for acknowledgment. Error: Write Operation fails at packet number 4165 at address 0x1044FF Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18stm32mp: stm32prog: remove all the header check for UART downloadPatrick Delaunay
This patch removes the header check for UART download; the check of checksum is not mandatory with even parity and chuck checksum for each 256 received bytes and it is only done for STM32 image (FSBL = TF-A BL2), not for FIT image. This patch solve issue of duplicated 0x100 byte written with FIP header. Fixes: 4fb7b3e10891 ("stm32mp: stm32prog: add FIP header support") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18board: rockchip: Add rk3568 evb supportJoseph Chen
Add support for rk3568 evaluation board. Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-18rockchip: Add rk3568 architecture coreJoseph Chen
RK3568 is a high-performance and low power quad-core application processor designed for personal mobile internet device and AIoT equipments. Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-18arm: dts: rockchip: Add dts for rk3568 evbJoseph Chen
Add dts for rk3568 evb, sync from the linux kernel upstream list [0]. [0] https://patchwork.kernel.org/project/linux-rockchip/list/?series=474969 Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-18arm: dts: Sync rockchip-pinconf.dtsi from kernelJoseph Chen
Sync from linux kernel: https://patchwork.kernel.org/project/linux-rockchip/list/?series=474969 Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-18rockchip: rk3568: add clock driverElaine Zhang
Add rk3568 clock driver and cru structure definition. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-18arm: dts: stm32mp157c-odyssey-som: enable SDMMC2 in SPLGrzegorz Szymaszek
Enable the SDMMC2 device tree node, as well as the pins it uses, in U-Boot SPL. Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18arm: dts: stm32mp157c-odyssey-som: enable the SDMMC2 eMMC HS DDR modeGrzegorz Szymaszek
Enable the SDMMC2 eMMC high-speed DDR mode as it is done in the corresponding Linux kernel device tree. Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18arm: dts: stm32mp157c-odyssey-som: set the SDMMC2 VQMMC supplyGrzegorz Szymaszek
Set the SDMMC2 VQMMC supply to vdd (buck3). Note that in the corresponding Linux kernel device tree, the supply is set to v3v3 (buck4), which is wrong. Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18arm: dts: stm32mp157c-odyssey-som: enable all SDMMC2 data lanesGrzegorz Szymaszek
Add the “sdmmc2_d47_pins_d” pins to the SDMMC2 pinctrls. Increase the bus width from four to eight. Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18arm: dts: stm32mp157c-odyssey-som: fix the basic SDMMC2 propertiesGrzegorz Szymaszek
The SDMMC2 interface hosts an eMMC. Replace the interface properties that would only apply to SD cards—“broken-cd” and “disable-wp”—with relevant ones: “non-removable”, “no-sd” and “no-sdio”. Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-17Merge tag 'u-boot-atmel-2021.10-a' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-atmel into next First set of u-boot-atmel features for the 2021.10 cycle: This feature set converts the boards pm9261 and pm9263 Ethernet support to DM; enables hash command for all SAM boards; fixes the NAND pmecc bit-flips correction; adds Falcon boot for sama5d3_xplained board; and other minor adjustments.
2021-06-17Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini
- fsl-qoriq: Bug fixes related pfe, eth, thermal node, vid.c, cpu release, mmc, usb, env, etc for Layerscape boards - powerpc: Update Maintainers for some boards.
2021-06-17Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini
- ae350 related dts fixes.
2021-06-17armv8: Update erratum number to align with docRan Wang
Change the USB erratum number A-050106 to A-050204 as A-050106 is a duplicate and never be published. Fixes 0cfa00cdb94 (“armv8: Add workaround for USB erratum A-050106”) Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-06-17board: freescale: t208xrdb: add a config option for rev D dts fixupsCamelia Groza
Under DM, we rely on u-boot's device tree to provide the correct PHY addresses. The board_fix_fdt callback is intended to be used for device tree fixups before relocation. Unfortunately, this isn't an option when booting from flash since the device tree isn't writable before relocation. This patch introduces the CONFIG_T2080RDB_REV_D option to signal that a board revision D or up is the target. The config option is used to set the correct Aquantia PHY address in the board's u-boot device tree. Defconfig files with the option enable explicitly are added for convenience. Signed-off-by: Camelia Groza <camelia.groza@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-06-17board/km: add support for expu1 design based on nxpAleksandar Gerasimovski
The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-06-17arm: dts: ls1021a.dtsi: Fix invalid reg on gpio nodesLasse Klok Mikkelsen
Address and size cells on SOC are set to 1. But gpio nodes are specified with 2 cells. This fixes the gpio nodes to correct cells. Signed-off-by: Lasse Klok Mikkelsen <lkmi@prevas.dk> Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-06-17arm: dts: lx2162aqds: support eMMC HS400 mode on esdhc1Yangbo Lu
Add properties related to eMMC HS400 mode for esdhc1. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-06-17armv8: ls1012a: Pass PPFE firmware to Linux through FDTChaitanya Sakinam
Read Linux PPFE firmware from flash partition and pass it to Linux through FDT entry. So that we can avoid placing PPFE firmware in Linux rootfs. (FDT may increase at max by 64KB) Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com> Signed-off-by: Anji J <anji.jagarlmudi@nxp.com> Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-06-17armv8: layerscape: enable eMMC HS400 workarounds for LX2160A/LX2162AYangbo Lu
Enable eMMC HS400 workarounds for LX2160A/LX2162A. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-06-17armv8: layerscape: add PSCI support for cpu releaseJiafei Pan
For cpu release command, check whether PSCI is supported firstly, if supported, use PSCI to kick off secondary cores, otherwise still use spin table. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> [Fixed checkpatch alignment CHECKs] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-06-17k210: dts: Set PLL1 to the same rate as PLL0Sean Anderson
Linux has had some stability issues when using AISRAM with a different frequency from SRAM. Mirror their change here now that we relocate into AISRAM. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17riscv: andes_plic: Fix riscv_get_ipi() maskBin Meng
Current logic in riscv_get_ipi() for Andes PLICSW does not look correct. The mask to test IPI pending bits for a hart should be left shifted by (8 * gd->arch.boot_hart), just the same as what is done in riscv_send_ipi(). Fixes: 8b3e97badf97 ("riscv: add functions for reading the IPI status") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Tested-by: Rick Chen <rick@andestech.com>
2021-06-17riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL configBin Meng
At present the AE350 SPL defconfig is using OF_PRIOR_STAGE. The intention was to use gdb to load device tree before running U-Boot SPL/proper from RAM. When we switch to OF_SEPARATE we will have to use our own DT but without "u-boot,dm-spl" in several essential nodes, SPL does not boot. Let's add all the required "u-boot,dm-spl" for SPL config. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-06-17riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bitBin Meng
All the device nodes that refer to plic0 as their interrupt parent have 2 cells encoded in their interrupts property, but plic0 only provides 1 cell in #interrupt-cells which is incorrect. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodesBin Meng
PLIC nodes don't have child nodes, so #address-cells is not needed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17riscv: ae350: dts: Remove the unnecessary space in bootargsBin Meng
There are two spaces before "debug' in bootargs. Drop one. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17riscv: ae350: dts: Add SPDX license headerBin Meng
The SPDX license header is currently missing. Add one. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-06-16Merge tag 'u-boot-imx-20210616' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20210616 ------------------- - imxrt : fixes, USB, imxrt1020-evk - imx8m: fix for verdin-imx8mm Add conga-QMX8 board - imx6 : documentation for pico-imx6: Add SeeedStudio NPI-IMX6ULL Support ventana: DM PCI - imx7d: added SMEGW01 board CI : https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/7765
2021-06-16board: sl28: fix RGMII clock and voltageMichael Walle
It was noticed that the clock isn't continuously enabled when there is no link. This is because the 125MHz clock is derived from the internal PLL which seems to go into some kind of power-down mode every once in a while. The LS1028A expects a contiuous clock. Thus enable the PLL all the time. Also, the RGMII pad voltage is wrong, it was configured to 2.5V (that is the VDDH regulator). The correct voltage is 1.8V, i.e. the VDDIO regulator. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-06-11ARM: dts: k3: Add cfg register space for ringacc and udmapVignesh Raghavendra
R5 SPL needs access to cfg space of Rings and UDMAP, therefore add RING CFG, TCHAN CFG and RCHAN CFG address ranges. Note that these registers are present within respective IPs but are not populated in Linux DT nodes (as they are configured via TISCI APIs) and hence are added to -u-boot.dtsi for now. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210607141753.28796-6-vigneshr@ti.com
2021-06-11ARM: dts: j72xx-r5-common-proc-board: Add DM firmware nodeVignesh Raghavendra
Add DM firmware node which will provide DM services during R5 SPL stage. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210607141753.28796-5-vigneshr@ti.com
2021-06-11Merge tag 'xilinx-for-v2021.07-rc5' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2021.07-rc5 zynqmp: - Fix ANALOG_BUS value after powerup - Disable EFI_CAPSULE_ON_DISK_EARLY zynqmp-gqspi: - Fix write issue
2021-06-11arm: dts: k3-j72xx: correct MCU timer1 frequencyTero Kristo
MCU timer1 is used as the tick timer for MCU R5 SPL, and the clock-frequency defined in DT appears to be incorrect at the moment. Actual clock source for the timer is MCU_SYSCLK0 / 4 which is 250MHz. Earlier setup of 25MHz went unnoticed, as there was a separate issue with omap-timer, which caused an error to the clock by a factor of 8 with j7 devices. This problem surfaced once the omap-timer was fixed. Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11arm: mach-k3: j721e_init: Force early probe of clk-k3 driverDave Gerlach
Force the clk-k3 driver to probe early during R5 SPL boot to ensure the default system clock configuration is completed. Many other drivers assume a default state of the clock tree and it is currently possible for them to probe before clk-k3 depending on the exact system configuration. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Reported-by: Keerthy <j-keerthy@ti.com> Tested-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11arm: mach-k3: sysfw-loader: pass boardcfg to sciserverTero Kristo
Copy the contents of the board config loaded from sysfw.itb into an EXTBOOT shared memory buffer that gets passed to sciserver. This only needs to be done if EXTBOOT area has not been populated by ROM code yet. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11arm: mach-k3: common: Drop main r5 startDave Gerlach
Only start-up the non-linux remote cores if we are running in legacy boot mode. HSM rearch is not yet supporting this. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11arm: mach-k3: do board config for PM only if supportedTero Kristo
If the raw PM support is built in, we are operating in the split firmware approach mode where PM support is not available. In this case, skip the board config for this. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11arm: mach-k3: add support for detecting firmware images from FITTero Kristo
Add callback routines for parsing the firmware info from FIT image, and use the data to boot up ATF and the MCU R5 firmware. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11arm: mach-k3: Add platform data for j721e and j7200Dave Gerlach
Add platform clock and powerdomain data for J721e and J7200. This data is used by the corresponding drivers to register all the required device clocks and powerdomains. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11tools: k3_fit_atf: add DM binary to the FIT imageTero Kristo
Add DM (device manager) firmware image to the fit image that is loaded by R5 SPL. This is needed with the HSM rearch where the firmware allocation has been changed slightly. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11common: fit: Update board_fit_image_post_process() to pass fit and node_offsetLokesh Vutla
board_fit_image_post_process() passes only start and size of the image, but type of the image is not passed. So pass fit and node_offset, to derive information about image to be processed. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11arm: mach-k3: introduce new config option for sysfw splitTero Kristo
On J7 family of SoCs (J721E and J7200), sysfw is being split to be run under two cores, TIFS portion on DMSC core, and DM firmware under MCU R5. As MCU R5 is also used to run one phase of the bootloader, we must prevent access from here towards sysfw services. To support this, add new config option which can be used to detect presence of RM/PM sysfw services. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11arm64: zynqmp: Writing correct value to ANALOG_BUSAdrian Fiergolski
The default register configuration after powerup for PSSYSMON_ANALOG_BUS register is incorrect. Hence, fix this in SPL by writing correct fixed value. It follows UG1085 chapter 'PS SYSMON Analog_Bus' and reflects commit sw_apps:zynq ("056ca65d44549ce27f716d423e8dfdefeee7440c") in Xilinx:embeddedsw[1]. [1] https://github.com/Xilinx/embeddedsw Signed-off-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-10arm: mvebu: dts: turris_mox: add nodes for SPI NOR partitionsMarek Behún
Add nodes for SPI NOR partitions to the device tree of Turris MOX, as are in Linux' device tree. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-06-10arm: mvebu: dts: turris_mox: add button and LED nodesMarek Behún
Add nodes for indicator LED and reset button so that board code can implement board factory reset mechanism. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
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