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Update the ddr phy config values to those created by the mscale_v3.10
tool. The original values were obtained using mscale_v3.10. The v3.10
tool removed ddr phy register values of 0x0.
This has no functional change but makes comparing and patching ddr
configuration easier in addition to slightly shrinking the DRAM config
size.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
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Add dram support for the MT53E1G32D2FW-046 RevC part which is a single die
32Gbit density part vs RevA/B which were dual-die parts:
- use a previously unused EEPROM byte to denote a variant of the
base config to be patched
- add a dram description string
- return the board struct from eeprom_init and pass it to the
spl_dram_init function so that it has access to the EEPROM
- move ddr_init into the spl_dram_init so that it can be patched
in the per-soc init function
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
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Add the configuration register for DDRC_ADDRMAP7 which was added in the
RAP spreadsheet v19. This has no functional change but allows DRAM
configuration to be patched in a later commit.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
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The GW7902/GW7903/GW7904 have an alternate databus layout affecting a few
of the DDRC and DDR PHY registers.
The 512MB configuration used this alternate bus layout. Change
the 512MB config to the standard bus configuration and add a generic
function to patch the DDRC/PHY configs for the alternate bus layout.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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Move the determination of the dram timings into the soc-specific files.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.
Reported-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tom Rini <trini@konsulko.com>
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When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.
This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.
Reported-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tom Rini <trini@konsulko.com>
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Remove <common.h> from this board vendor directory and when needed
add missing include files directly.
Acked-By: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
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The GW7903 is based on the i.MX 8M Mini SoC featuring:
- LPDDR4 DRAM
- eMMC FLASH
- microSD socket with voltage select support
- Gateworks System Controller
- M.2 A-E Socket with USB2.0 and PCIe
- MiniPCIe Socket with PCIe, USB2.0, and SIM
- IMX8M FEC
- RS232/RS485/RS422 serial transceiver
- LIS2DE12 3-axis accelerometer
- front panel LED's
- off-board isolated digital I/O
- Wide range DC power input
- 802.3at PoE
- PMIC
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
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The GW7902 is based on the i.MX 8M Mini / Nano SoC featuring:
- LPDDR4 DRAM
- eMMC FLASH
- Gateworks System Controller
- LTE CAT M1 modem
- USB 2.0 HUB
- M.2 Socket with USB2.0, PCIe, and dual-SIM
- IMX8M FEC
- PCIe based GbE
- RS232/RS485/RS422 serial transceiver
- GPS
- CAN bus
- WiFi / Bluetooth
- MIPI header (DSI/CSI/GPIO/PWM/I2S)
- PMIC
To add support for the i.MX8M Nano GW7902:
- Add imx8mn-venice dts/defconfig/include
- Add imx8mn-gw7902 dts
- Add imx8mn-2gb lpddr4 dram configs
- Add misc support for IMX8M Nano SoC
- rename imx8mm-venice.c to venice.c as it is no longer imx8mm specific
- update README with differences for IMX8MN vs IMX8MM
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
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