summaryrefslogtreecommitdiff
path: root/drivers/phy
AgeCommit message (Collapse)Author
2022-01-20phy: marvell: Remove unused function comphy_update_map()Pali Rohár
This weak function is not used anymore, so completely remove it. Private struct comphy_map is not used by any board code anymore, so move it into private driver header file comphy_core.h. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-20fdt_support: Add fdt_for_each_node_by_compatible() helper macroMarek Behún
Add macro fdt_for_each_node_by_compatible() to allow iterating over fdt nodes by compatible string. Convert various usages of off = fdt_node_offset_by_compatible(fdt, start, compat); while (off > 0) { code(); off = fdt_node_offset_by_compatible(fdt, off, compat); } and similar, to fdt_for_each_node_by_compatible(off, fdt, start, compat) code(); Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-19Merge tag 'xilinx-for-v2022.04-rc1' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2022.04-rc1 gpio: - Add modepin driver net: - Save random mac addresses to eth variable zynqmp gem: - Add support for mdio bus DT description - Add support for reset and SGMII phy configuration - Reduce timeout for MDIO accesses zynqmp clk: - Fix clock handling for gem and usb phy: - Add zynqmp phy/serdes driver serial: - Add one missing compatible string microblaze: - Symbol alignement - SPL fixups - Code cleanups zynqmp: - Various dt changes, DP pre-reloc, gem resets, gem clocks - Switch SOM to shared psu configuration - Move dcache handling to firmware driver - Workaround gmii2rgmii DT description issue - Enable broadcasts again - Change firmware enablement logic - Small adjustement in firmware driver versal: - Support new mmc@ DT nodes - Fix run time variable handling - Add missing I2C_PMC ID for power domain
2022-01-14phy: Track power-on and init counts in uclassAlper Nebi Yasak
On boards using the RK3399 SoC, the USB OHCI and EHCI controllers share the same PHY device instance. While these controllers are being stopped they both attempt to power-off and deinitialize it, but trying to power-off the deinitialized PHY device results in a hang. This usually happens just before booting an OS, and can be explicitly triggered by running "usb start; usb stop" in the U-Boot shell. Implement a uclass-wide counting mechanism for PHY initialization and power state change requests, so that we don't power-off/deinitialize a PHY instance until all of its users want it done. The Allwinner A10 USB PHY driver does this counting in-driver, remove those parts in favour of this in-uclass implementation. The sandbox PHY operations test needs some changes since the uclass will no longer call into the drivers for actions matching its tracked state (e.g. powering-off a powered-off PHY). Update that test, and add a new one which simulates multiple users of a single PHY. The major complication here is that PHY handles aren't deduplicated per instance, so the obvious idea of putting the counts in the PHY handles don't immediately work. It seems possible to bind a child udevice per PHY instance to the PHY provider and deduplicate the handles in each child's uclass-private areas, like in the CLK framework. An alternative approach could be to use those bound child udevices themselves as the PHY handles. Instead, to avoid the architectural changes those would require, this patch solves things by dynamically allocating a list of structs (one per instance) in the provider's uclass-private area. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Peter Robinson <pbrobinson@gmail.com> - Rock960
2022-01-13treewide: invaild -> invalidSean Anderson
Somewhere along the way, someone misspelt "invalid" and it got copied everywhere. Fix it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Alexander Dahl <ada@thorsis.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-12phy: zynqmp: Add serdes/psgtr driverMichal Simek
Add PSGTR driver for Xilinx ZynqMP. The most of configurations are taken from Linux kernel psgtr driver. USB3.0 and SGMII configurations are tested on SOM. In SGMII case also IOU_SLCR reg is updated to get proper clock setup and signal detection configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/36e6e9d3baf8511af1916e91e4887032ca2b6c20.1641458978.git.michal.simek@xilinx.com
2021-12-19phy: marvell: a3700: Convert to official DT bindings in COMPHY driverPali Rohár
Convert A3720 common PHY driver to official DT bindings. This puts us closer to be able to synchronize A3720 device-trees with those from Linux. Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Konstantin Porotchkin <kostap@marvell.com> Cc: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Marcin Wojtas <mw@semihalf.com> Cc: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-17phy: cadence: phy-cadence-torrent: Change the name of subnode searchedAswath Govindraju
Search for "phy" in the subnode names, to syncup with kernel. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2021-10-25phy: sun4i-usb: Support VBUS detection via power supplySamuel Holland
The device tree binding provides for getting VBUS state from a device referenced by phandle, as an optional alternative to using a GPIO. In U-Boot, where there is no power supply class, this VBUS detection will be implemented using a regulator device and its get_enable method. Let's hook this up to the PHY driver. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25phy: sun4i-usb: Refactor VBUS detection to match LinuxSamuel Holland
The Linux driver checks the VBUS detection GPIO first; then VBUS power supply; then finally assumes VBUS is present. When adding VBUS power supply support, we want to match that order, so we get the same behavior in case both a GPIO and a power supply are provided in the device tree. So refactor the function a bit to remove the early return, and use the same "assume VBUS is present" final fallback. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25phy: sun4i-usb: Remove a couple of debug messagesSamuel Holland
Both of these messages log the GPIO number of the ID detection GPIO, which is not terribly useful, especially in the VBUS detection function. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-12Merge tag 'u-boot-stm32-20211012' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-stm - Disable ATAGS for STM32 MCU and MPU boards - Disable bi_boot_params for STM32 MCU and MPU boards - Update stm32-usbphyc node management - Convert CONFIG_STM32_FLASH to Kconfig for STM32 MCU boards - Convert some USB config flags to Kconfig for various boards - Convert CONFIG_BOOTCOMMAND flag to Kconfig for STM32 F429 board - Remove specific CONFIG_STV0991 flags - Remove unused CONFIG_USER_LOWLEVEL_INIT flag - Add ofdata_to_platdata() callback for stm32_spi driver - Update for stm32f7_i2c driver - Remove gpio_hog_probe_all() from STM32 MP1 board - Fix bind command Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-08phy: marvell: a3700: Return correct error code when power up failsPali Rohár
Subroutines in comphy_usb2_power_up() and comphy_sgmii_power_up() functions may fail. In this case, do not continue execution of current function and instead jump to the end. Return value in 'ret' variable is already set. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-08phy: marvell: a3700: Fix configuring polarity invert bitsPali Rohár
phy_txd_inv or phy_rxd_inv needs to be set only in case when appropriate polarity is inverted. Otherwise these bits should be cleared. Same change was included in TF-A project: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/9406 Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-08phy: marvell: a3700: Set TXDCLK_2X_SEL bit during PCIe initializationPali Rohár
Marvell Armada 3700 Functional Specifications, section 52.2 PCIe Link Initialization says that TXDCLK_2X_SEL bit needs to be enabled for PCIe Root Complex mode. Same change was included in TF-A project: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/9408 Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-08phy: stm32-usbphyc: stm32: usbphyc: add protection on phy sub-nodePatrick Delaunay
Add protection on presence and order of the phy node sub node by using the mandatory reg information. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-10-08phy: stm32-usbphyc: use connector for vbus-supply with phy-stm32-usbphycPatrick Delaunay
The vbus-supply is an optional property of sub-node connector node. and no more in the usb phyc node (in first proposed binding). This regulator for USB VBUS may be needed for host mode. See the latest kernel binding for details in Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml. usbphyc_port0: usb-phy@0 { reg = <0>; phy-supply = <&vdd_usb>; #phy-cells = <0>; connector { compatible = "usb-a-connector"; vbus-supply = <&vbus_sw>; }; }; Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-09-30WS cleanup: remove trailing empty linesWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-09-27Merge tag 'v2021.10-rc5' into nextTom Rini
Prepare v2021.10-rc5
2021-09-27phy: marvell: cp110: Support SATA invert polarityDenis Odintsov
In commit b24bb99d cp110 configuration initially done in u-boot was removed and delegated to atf firmware as smc call. That commit didn't account for later introduced in d13b740c SATA invert polarity support. This patch adds support of passing SATA invert polarity flags to atf firmware during the smc call. Signed-off-by: Denis Odintsov <shiva@mail.ru> Cc: Baruch Siach <baruch@tkos.co.il> Cc: Rabeeh Khoury <rabeeh@solid-run.com> Cc: Stefan Roese <sr@denx.de> Reviewed-by: Stefan Roese <sr@denx.de>
2021-09-22phy: sun50i-usb3: Add a driver for the H6 USB3 PHYSamuel Holland
This driver is needed for XHCI to work on the Allwinner H6 SoC. The driver is copied from Linux v5.10. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-08-31Kconfig: Remove all default n/no optionsMichal Simek
default n/no doesn't need to be specified. It is default option anyway. Signed-off-by: Michal Simek <michal.simek@xilinx.com> [trini: Rework FSP_USE_UPD portion] Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-29Merge tag 'ti-v2021.10-rc2' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-ti - Add MMC High speed modes for AM64 and J7200 - Add Sierra/Torrent SERDES driver - Minor clean-ups for R5F boot from SPL
2021-07-28Makefile: Move phy rules into drivers/phySimon Glass
These don't belong in the drivers Makefile so move them down into the correct place. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup some missing dependencies this exposed] Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-27phy: meson-axg-mipi: Access parent ofnode through dev_ofnode()Alper Nebi Yasak
With commit 84a42ae36683 ("dm: core: Rename device node to indicate it is private") and commit f10643cf8a4c ("dm: core: Access device ofnode through functions") accesses to the "node" member were replaced with dev_ofnode(). Also apply that replacement here. Fixes: 4547551aa019 ("phy: Add Amlogic AXG MIPI PCIe Analog PHY driver") Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-07-27phy: meson-axg-mipi: Rename "priv_auto_alloc_size" to "priv_auto"Alper Nebi Yasak
With commit 41575d8e4c33 ("dm: treewide: Rename auto_alloc_size members to be shorter") "priv_auto_alloc_size" was renamed to "priv_auto". Apply the rename to these two drivers as well. Fixes: 4547551aa019 ("phy: Add Amlogic AXG MIPI PCIe Analog PHY driver") Fixes: 7ef19503bacf ("phy: Add Amlogic AXG MIPI D-PHY driver") Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-07-27phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoCJean-Jacques Hiblot
Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES wrapper used to configure some of the input signals to the SERDES. It is used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures three clock selects (pll0, pll1, dig) and supports resets for each of the lanes. This is an adaptation of the linux driver. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-10-kishon@ti.com
2021-07-27phy: cadence: Add driver for Torrent SERDESAswath Govindraju
Add driver for Torrent SERDES. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-9-kishon@ti.com
2021-07-27phy: cadence: Add driver for Sierra PHYAlan Douglas
Add a Sierra PHY driver with PCIe and USB support. This driver is a port from the mainline linux driver. The PHY has multiple lanes, which can be configured into groups, and a generic PHY device is created for each group. There are two resets controlling the overall PHY block, one to enable the APB interface for programming registers, and another to enable the PHY itself. Additionally there are resets for each PHY lane. The PHY can be configured in hardware to read register settings from ROM, or they can be written by the driver. The sequence of operation on startup is to enable the APB bus, write the PHY registers (if required) for each lane group, and then enable the PHY. Each group of lanes can then be individually controlled using the power_on()/ power_off() function for that generic PHY One difference with the linux driver is that the PHY is always reset after it is powered-on. This is because role switching is not supported in u-boot and the cable orientation is handled by the PHY reset. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Signed-off-by: Alan Douglas <adouglas@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-8-kishon@ti.com
2021-07-17Merge tag 'u-boot-imx-20210717' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx i.MX ---- - mx7ulp : fix WDOG - imx8 : Phytec - USB3 support for i.MX8 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/8277
2021-07-17phy: phy-imx8mq-usb: Add USB PHY driver for i.MX8MQYe Li
Add the USB PHY driver for i.MX8MQ to work with DWC3 USB controller. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Patrick Wildt <patrick@blueri.se> Tested-by: Patrick Wildt <patrick@blueri.se>
2021-07-14phy: Add driver for ST-Ericsson AB8500 USB PHYStephan Gerhold
The AB8500 PMIC contains an USB PHY that needs to be set up in device or host mode to make USB work properly. Add a simple driver for the generic PHY uclass that allows enabling it. The if (CONFIG_IS_ENABLED(USB_MUSB_HOST)) might be a bit strange. The USB PHY must be configured in either host or device mode and somehow the USB PHY driver must be made aware of the mode. Actually, the MUSB driver used together with this PHY does not support dynamic selection of host/device mode in U-Boot at the moment. Therefore, one very simple approach that works fine is to select the mode to configure at compile time. When the MUSB driver is configured in host mode the PHY is configured in host mode, and similarly when the MUSB driver is configured in device/gadget mode. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-07-14phy: socionext: Add UniPhier PCIe PHY driverKunihiko Hayashi
Add PCIe PHY driver support for Pro5, LD20 and PXs3 SoCs. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
2021-07-10phy: sun4i-usb: Fix PHY0 routing and passby configuration for MUSBPaul Kocialkowski
Recent Allwinner platforms (starting with the H3) only use the MUSB controller for peripheral mode and use HCI for host mode. As a result, extra steps need to be taken to properly route USB signals to one or the other. More precisely, the following is required: * Routing the pins to either HCI/MUSB (controlled by PHY); * Enabling USB PHY passby in HCI mode (controlled by PMU). The current code will enable passby for each PHY and reroute PHY0 to MUSB, which is inconsistent and results in broken USB peripheral support. Passby on PHY0 must only be enabled when we want to use HCI. Since host/device mode detection is not available from the PHY code and because U-Boot does not support changing the mode dynamically anyway, we can just mux the controller to MUSB if it is enabled and mux it to HCI otherwise. This fixes USB peripheral support for platforms with PHY0 dual-route, especially H3/H5 and V3s. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-07-06dm: define LOG_CATEGORY for all uclassPatrick Delaunay
Define LOG_CATEGORY for all uclass to allow filtering with log command. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-04-29phy: marvell: utmi: update utmi config which fixes usb2.0 instabilityGrzegorz Jaszczyk
- Add additional step which enables the Impedance and PLL calibration. - Enable old squelch detector instead of the new analog squelch detector circuit and update host disconnect threshold value. - Update LS TX driver strength coarse and fine adjustment values. Change-Id: Ifa0a585bfb5ecab0bfa033eed6874ff98b16a7df Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2021-04-29phy: marvell: add support for SFI1Igal Liberman
In CP115, comphy4 can be configured into SFI port1 (in addition to SFI0). This patch adds the option described above. In addition, rename all existing SFI/XFI references: COMPHY_TYPE_SFI --> COMPHY_TYPE_SFI0 No functional change for exsiting configuration. Change-Id: If9176222e0080424ba67347fe4d320215b1ba0c0 Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2021-04-29phy: marvell: fix pll initialization for second utmi portGrzegorz Jaszczyk
According to Design Reference Specification the PHY PLL and Calibration register from PHY0 are shared for multi-port PHY. PLL control registers inside other PHY channels are not used. This commit reworks utmi device tree nodes in a way that common PHY PLL registers are moved to main utmi node. Accordingly both child nodes utmi-unit range is reduced and register offsets in utmi_phy.h are updated to this change. This fixes issues in scenarios when only utmi port1 was in use, which resulted with lack of correct pll initialization. Change-Id: Icc520dfa719f43a09493ab31f671efbe88872097 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2021-04-29phy: marvell: allow to initialize up to 6 USB portsGrzegorz Jaszczyk
New products can contain up to 6 usb ports, therefore allow to initialize all relevant UTMI PHYs. Change-Id: I28c36e59fa0e3e338bb3ee0cee2240b923f39785 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
2021-04-29phy: marvell: cp110: mark u-boot power-off callsIgal Liberman
It helps ATF to determine who called power off function (U-boot/Linux) and act accordingly Change-Id: Icfc5cbfdba64754496812154272b28c0ff639f0f Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2021-04-29phy: marvell: fix handling of unconnected comphyChristine Gharzuzi
- the default value of comphy pipe selector is set to PCIe (x4) in case of unconnected comphy the default value remains 0x4 which may lead to several issues with comphy initialization. - this patch adds SMC call that powers off the comphy lane in case of unconnected comphy. Change-Id: I196b2916518dd8df3b159ffa85e2989b8e483087 Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2021-04-29phy: marvell: pass sgmii id to firmwareIgal Liberman
Currently, we don't pass id for SGMII 0/1. A bug in comphy selector configuration was found (in comphy firmware), after fixing it, SGMII0/1 have different configuration, so we need to pass the ID the firmware. Change-Id: Idcff4029cc9cf018278e493221b64b33574e0d38 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2021-04-29phy: marvell: cp110: clean up driver after it was moved to atfGrzegorz Jaszczyk
Change-Id: I358792a96c13b54e700c05227cc7a8f6bd584694 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2021-04-29phy: marvell: cp110: remove both phy and pipe selector configurationGrzegorz Jaszczyk
Now the comphy configuration is handled in atf, therefore there is no need to configure phy or pipe selector in u-boot, it is configured by atf for each particular pair: lane and mode. Change-Id: I0bebf8d5ff66dbeb6bf9ef90876195938a8eb705 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2021-04-29phy: marvell: cp110: let the firmware perform training for XFIGrzegorz Jaszczyk
Replace the XFI training with appropriate SMC call, so the firmware will perform exact initialization. Update Stefan 2021-03-23: Move comphy_smc() function to an earlier place - necessary for the mainline merge. Change-Id: I789b130b05529dc80dadcf66aef407d93595b762 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Igal Liberman <igall@marvell.com>
2021-04-29phy: marvell: cp110: let the firmware configure comphy for USBGrzegorz Jaszczyk
Replace the comphy initialization for USB with appropriate SMC call, so the firmware will execute required serdes configuration. Change-Id: I7f773c0dfac70db9dd2653de2cdcfac577e78c4e Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2021-04-29phy: marvell: cp110: let the firmware configure comphy for RXAUIGrzegorz Jaszczyk
Replace the comphy initialization for RXAUI with appropriate SMC call, so the firmware will execute required serdes configuration. Change-Id: Iedae0285fb283e05bb263a8b4ce46e8e7451a309 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2021-04-29phy: marvell: cp110: remove unused definitionsMarcin Wojtas
Even if comphy types of SATA2/SATA3/SGMII3 and comphy speeds of 1.5G/3G/6.25G were referenced in the driver non configuration (dts) was using it. This patch removes unused definitions. Change-Id: I53ed6f9d3a82b9d18cb4e488bc14d3cf687f9488 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2021-04-29phy: marvell: enable comphy info prints for all devicesIgal Liberman
Change-Id: I3b97253e7102a0868440a9e0200acc1c7919c743 Signed-off-by: Igal Liberman <igall@marvell.com>
2021-04-29phy: marvell: add RX training commandIgal Liberman
This patch adds support for running RX training using new command called "rx_training" Usage: rx_training - rx_training <cp id> <comphy id> RX training allows to improve link quality (for SFI mode) by running training sequence between us and the link partner, this allows to reach better link quality then using static configuration. Change-Id: I818fe67ccaf19a87af50d4c34a9db7d6802049a5 Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
generated by cgit v1.2.3 (git 2.0.4) at 2025-11-06 21:06:53 +0000