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path: root/drivers/phy
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14 hoursphy: add common PHY properties supportLucien.Jheng
Add a new PHY_COMMON_PROPS library that provides helper functions for PHY drivers to read standardized polarity properties from the device tree node: - phy_get_rx_polarity() / phy_get_tx_polarity() - phy_get_manual_rx_polarity() / phy_get_manual_tx_polarity() The dt-bindings/phy/phy.h header with PHY_POL_NORMAL, PHY_POL_INVERT, and PHY_POL_AUTO constants is provided via dts/upstream/include, which is already in the build include path. Ported from Merge tag 'phy-for-7.0': git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Link: https://git.kernel.org/linus/e7556b59ba65179612bce3fa56bb53d1b4fb20db Signed-off-by: Lucien.Jheng <lucienzx159@gmail.com>
10 daysphy: qcom: Add Milos to QMP UFS PHY driverLuca Weiss
Import the configuration for the Milos SoC from Linux (tag v7.0-rc4). Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://patch.msgid.link/20260318-milos-bringup-v2-3-650b91dd75d8@fairphone.com Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
10 daysdrivers: phy: qcom: Add QMP USB3-DP Combo PHY driverBalaji Selvanathan
Add support for the Qualcomm QMP USB3-DP Combo PHY found on SC7280 and QCM6490 platforms. This driver currently implements USB3 super-speed functionality of the combo PHY. The QMP Combo PHY is a dual-mode PHY that can operate in either USB3 mode or DisplayPort mode. This initial implementation focuses on USB3 mode to enable Super-Speed USB support. Taken from Linux commit 3d25d46a255a ("pmdomain: qcom: rpmhpd: Add rpmhpd support for SM8750") This patch is dependent on this patch: https://lore.kernel.org/u-boot/20251112164204.1557934-1-aswin.murugan@oss.qualcomm.com/ Enabled and tested the driver on Qualcomm RB3 Gen2 (QCS6490) board. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> Reviewed-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> Link: https://patch.msgid.link/20251203110735.1959862-4-balaji.selvanathan@oss.qualcomm.com [casey: fix unused variable warning] Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-04-17phy: mediatek: new XS-PHY driverDavid Lechner
Add a new driver for the Mediatek XS-PHY. This is found on some newer Mediatek SoCs. Upstream devicetree bindings already exist. MAINTAINERS is already covered by drivers/phy/phy-mtk-*. Link: https://patch.msgid.link/20260401-mtk-mt8189-usb-v1-1-a4bf951aa8ad@baylibre.com Signed-off-by: David Lechner <dlechner@baylibre.com>
2026-04-17drivers: phy: phy-mtk-ufs: do not alloc priv with priv_autoJulien Stephan
When priv_auto is specified, we should not manually alloc memory for priv data. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Julien Stephan <jstephan@baylibre.com> Link: https://patch.msgid.link/20260318-mt8195-add-ufs-support-v2-5-f18eeeeb0e72@baylibre.com Signed-off-by: David Lechner <dlechner@baylibre.com>
2026-04-17drivers: phy: phy-mtk-ufs: disable clk in power_offJulien Stephan
Disable clocks in power_off(). Also define ufs_mtk_phy_set_inactive() helper function to keep consistency with power_on() and ufs_mtk_phy_set_active(). Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Julien Stephan <jstephan@baylibre.com> Link: https://patch.msgid.link/20260318-mt8195-add-ufs-support-v2-4-f18eeeeb0e72@baylibre.com Signed-off-by: David Lechner <dlechner@baylibre.com>
2026-04-17drivers: phy: phy-mtk-ufs: use clk_bulk functionsJulien Stephan
simply the driver by using clk_bulk functions Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Julien Stephan <jstephan@baylibre.com> Link: https://patch.msgid.link/20260318-mt8195-add-ufs-support-v2-3-f18eeeeb0e72@baylibre.com Signed-off-by: David Lechner <dlechner@baylibre.com>
2026-04-17drivers: phy: phy-mtk-ufs: use tab to indent definesJulien Stephan
Use tabs instead of spaces to indent defines Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Julien Stephan <jstephan@baylibre.com> Link: https://patch.msgid.link/20260318-mt8195-add-ufs-support-v2-2-f18eeeeb0e72@baylibre.com Signed-off-by: David Lechner <dlechner@baylibre.com>
2026-04-17drivers: phy: phy-mtk-ufs: cleanup headersJulien Stephan
Remove unneeded headers and sort them alphabetically Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Julien Stephan <jstephan@baylibre.com> Link: https://patch.msgid.link/20260318-mt8195-add-ufs-support-v2-1-f18eeeeb0e72@baylibre.com Signed-off-by: David Lechner <dlechner@baylibre.com>
2026-04-06Merge branch 'next'Tom Rini
2026-03-24phy: qcom: qusb2: Add QCS615 QUSB2 PHY supportBalaji Selvanathan
Add support for QCS615 QUSB2 PHY by introducing platform-specific initialization table and register layout. The implementation reuses the IPQ6018 register layout and defines QCS615-specific tuning parameters for proper USB PHY operation. Taken from Linux commit 8adbf20e0502 ("phy: qcom-qusb2: Add support for QCS615") Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260213-talos_usb-v1-3-4c4355d61437@oss.qualcomm.com Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-03-16Merge patch series "Add PCIe Boot support for TI J784S4 SoC"Tom Rini
Siddharth Vadapalli <s-vadapalli@ti.com> says: This series adds PCIe endpoint boot support for the TI J784S4 SoC. Series is based on commit f9ffeec4bdc ("board: toradex: Make A53 get RAM size from DT in K3 boards") of the master branch of U-Boot. PCIe Boot Logs (J784S4-EVM running Linux as Root-Complex transfers bootloaders to another J784S4-EVM configured for PCIe Boot): https://gist.github.com/Siddharth-Vadapalli-at-TI/2d157003818441fe79a139d0dec1058a Link: https://lore.kernel.org/r/20260216102858.2745657-1-s-vadapalli@ti.com
2026-03-16phy: ti: Add config to enable J721E WIZ SERDES wrapper at SPL stageHrushikesh Salunke
Add SPL_PHY_J721E_WIZ configuration option to enable the WIZ SERDES wrapper driver in SPL stage. This is required for PCIe boot support where SERDES configuration must be done early in the boot sequence before loading the bootloader image over PCIe. Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2026-03-16phy: cadence: Add config to enable Cadence Torrent PHY at SPL stageHrushikesh Salunke
Add SPL_PHY_CADENCE_TORRENT configuration option to enable the Cadence Torrent PHY driver in SPL stage. This is required for PCIe boot support where SERDES configuration must be done early in the boot sequence before loading the bootloader image over PCIe. Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2026-03-10Merge tag 'u-boot-rockchip-20260309' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-rockchip into next CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/29452 - New SoC support: RK3506, RK3582; - New Board support: RK3528 FriendlyElec NanoPi Zero2; - Other fixes
2026-03-10phy: rockchip-inno-usb2: Add support for RK3506Jonas Karlman
Add support for the two USB2.0 PHYs use in the RK3506 SoC. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Tested-by: Aaron Griffith <aargri@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2026-03-09Merge tag 'v2026.04-rc4' into nextTom Rini
Prepare v2026.04-rc4
2026-03-09phy: rockchip: naneng-combphy: Enable U3 port for USB3OTG on RK3568Jonas Karlman
The USB OTG U3 port may have been disabled early, add support to the COMBPHY driver to re-enable the U3 port. This matches changes made in the Linux commit 7bb14b61b7d0 ("phy: rockchip: naneng-combphy: Enable U3 OTG port for RK3568"). Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Acked-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2026-03-02phy: Add MediaTek UFS PHY DriverIgor Belwon
This UFS M-PHY driver can be used on recent MediaTek SoCs as the primary PHY for the UFS controller. Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org> Link: https://patch.msgid.link/20251011-mtk-ufs-uboot-v1-1-a05f991ee150@mentallysanemainliners.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2026-02-25Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-samsungTom Rini
- Assorted platform and video driver updates
2026-02-25phy: samsung: add support for exynos7870 USB PHYKaustabh Chakraborty
The USB PHY used by the Exynos7870 SoC has a single USB 2.0 interface. Add its dedicated variant enum, compatible, and init/exit functions. The PHY enable bit of Exynos7870's PHY is different in contrast to that of Exynos850 and most Exynos PHYs. To allow this change, a simple if condition is added in exynos_usbdrd_phy_isol() which changes the bitmask. Since the variant enum is required, the function argument is changed to accept the driver data itself. Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2026-02-25phy: samsung: add enum for variants based on SoCsKaustabh Chakraborty
The variant enum is used to uniquely identify which SoC the PHY block belongs to. It is initially set in the match table, along with the compatible string, it gets copied to driver data struct during probe. SoC specific functions must only be called if the respective variant enum is set. Add switch-case blocks wherever required. Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2026-02-17treewide: Clean up DECLARE_GLOBAL_DATA_PTR usagePeng Fan
Remove DECLARE_GLOBAL_DATA_PTR from files where gd is not used, and drop the unnecessary inclusion of asm/global_data.h. Headers should be included directly by the files that need them, rather than indirectly via global_data.h. Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> #STMicroelectronics boards and STM32MP1 ram test driver Tested-by: Anshul Dalal <anshuld@ti.com> #TI boards Acked-by: Yao Zi <me@ziyao.cc> #TH1520 Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-02-04Merge patch series "arm: k3: j722s: add PCIe support"Tom Rini
George McCollister <george.mccollister@konsulko.com> says: This patch series brings over several changes from Linux that are required to get PCIe working on the j722s and also enables PCIe in j722s_evm_a53_defconfig. This allows Linux to be booted from an NVMe drive. The J722S SoC provides pcie0 (using pcie_cdns_ti) thru serdes1 (using phy-cadence-torrent) thru serdes_wiz1 (using phy-j721e-wiz). Changes to the three drivers needed to be ported from Linux to enable the REFCLK output which is used with this SoC. These changes should be tested on other platforms using these drivers by those with the hardware available to make sure no problems were introduced. The PCIe controller in this SoC relies on the code performing the PCI scan not scanning devices which cannot exist. In Linux this is implemented as only_one_child() in probe.c. If this mechanism is not used, PCI config reads for subsequent functions will return information for device 0 resulting in U-Boot detecting 32 devices when only 1 is present. This change should be tested on other platforms with PCI to ensure the same PCI devices are enumerated before and after the patch is applied. I would like to thank Opto 22 for sponsoring the initial development and anyone that is able to contribute to testing of patches. Link: https://lore.kernel.org/r/20260130153856.2049575-1-george.mccollister@konsulko.com
2026-02-04phy: cadence-torrent: Add support to drive refclk outGeorge McCollister
cmn_refclk_<p/m> lines in Torrent SERDES are used for connecting an external reference clock. cmn_refclk_<p/m> can also be configured to output the reference clock. Model this derived reference clock as a "clock" so that platforms like AM642 EVM can enable it. This is used by PCIe to use the same refclk both in local SERDES and remote device. Add support here to drive refclk out. Based on: https://lore.kernel.org/all/20210310120840.16447-7-kishon@ti.com/ Signed-off-by: George McCollister <george.mccollister@konsulko.com> Tested-by: Bryan Brattlof <bb@ti.com>
2026-02-04phy: ti: j721e-wiz: Enable reference clock output in cmn_refclk_<p/m>George McCollister
cmn_refclk_<p/m> lines in Torrent SERDES are used for an connecting external reference clock. cmn_refclk_<p/m> can also be configured to output the reference clock. In order to drive the refclk out from the SERDES (Cadence Torrent), PHY_EN_REFCLK should be set in SERDES_RST of WIZ. Model PHY_EN_REFCLK as a clock, so that platforms like AM642 EVM can enable it. Based on: https://lore.kernel.org/r/20210310120840.16447-6-kishon@ti.com Signed-off-by: George McCollister <george.mccollister@konsulko.com> Tested-by: Bryan Brattlof <bb@ti.com>
2026-01-19Merge tag 'xilinx-for-v2026.04-rc1-v2' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze AMD/Xilinx/FPGA changes for v2026.04-rc1 v2 microblaze: - Fix spl_boot_list order versal2: - Fix EMMC distro boot setup - Align distro boot variables with memory layout zynqmp-phy: - Sync with Linux kernel driver zynqmp: - Add verify_auth command - DT sync - Add placing variables to FAT/EXT4 - Enable PCIe driver by default pcie - xilinx-nwl: - Fix Link down crash ufs: - Align clock/reset with DT binding # -----BEGIN PGP SIGNATURE----- # # iHUEABYIAB0WIQSXAixArPbWpRanWW+rB/7wTvUR9QUCaW3p3wAKCRCrB/7wTvUR # 9VkwAP4jPRALpM34VpTimNe/iwigIx8hAHxbvkUU0oJ/DW6W8AEAhCSL+ydgreuv # kKCyNiOF1sm8IrOh4TdtMIFn37d4Dwg= # =AkKK # -----END PGP SIGNATURE----- # gpg: Signature made Mon 19 Jan 2026 02:22:55 AM CST # gpg: using EDDSA key 97022C40ACF6D6A516A7596FAB07FEF04EF511F5 # gpg: Can't check signature: No public key
2026-01-14phy: Add MSM8996 support to Qualcomm QUSB2 phyBiswapriyo Nath
This change is imported from Linux driver and tested with SM6125 SoC. Note, the msm8996_phy_cfg struct is same as sdm660_phy_cfg but qusb2_phy_cfg::se_clk_scheme_default differs only. Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com> Reviewed-by: Casey Connolly <casey.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Link: https://patch.msgid.link/20251207184919.12202-1-nathbappai@gmail.com Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-01-14phy: qcom: snps-femto-v2: assert reset in probeCasey Connolly
The power on function for the phy only deasserts the reset, so the phy might be in a weird state that we don't clean up properly. Assert the reset in probe() so that when we power on we will have the phy in a clean state. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251114144722.173021-2-casey.connolly@linaro.org Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-01-12phy: zynqmp: Only wait for PLL lock "primary" instancesSean Anderson
For PCIe and DisplayPort, the phy instance represents the controller's logical lane. Wait for the instance 0 phy's PLL to lock as other instances will never lock. We do this in xpsgtr_wait_pll_lock so callers don't have to determine the correct lane themselves. The original comment is wrong about cumulative wait times. Since we are just polling a bit, all subsequent waiters will finish immediately. Signed-off-by: Sean Anderson <sean.anderson@linux.dev> Link: https://lore.kernel.org/r/20240628205540.3098010-4-sean.anderson@linux.dev Signed-off-by: Vinod Koul <vkoul@kernel.org> [ Linux commit 235d8b663ab9e6cc13f8374abfffa559f50b57b6 ] Link: https://lore.kernel.org/r/20260106215501.727524-5-sean.anderson@linux.dev Signed-off-by: Michal Simek <michal.simek@amd.com>
2026-01-12phy: zynqmp: Store instance instead of typeSean Anderson
The phy "type" is just the combination of protocol and instance, and is never used apart from that. Store the instance directly, instead of converting to a type first. No functional change intended. Signed-off-by: Sean Anderson <sean.anderson@linux.dev> Link: https://lore.kernel.org/r/20240628205540.3098010-3-sean.anderson@linux.dev Signed-off-by: Vinod Koul <vkoul@kernel.org> [ Linux commit 6959d2367bc3503ac4ba3eb4ec6584a43150d6b3 ] Link: https://lore.kernel.org/r/20260106215501.727524-4-sean.anderson@linux.dev Signed-off-by: Michal Simek <michal.simek@amd.com>
2026-01-12phy: zynqmp: Enable reference clock correctlySean Anderson
Lanes can use other lanes' reference clocks, as determined by refclk. Use refclk to determine the clock to enable/disable instead of always using the lane's own reference clock. This ensures the clock selected in xpsgtr_configure_pll is the one enabled. For the other half of the equation, always program REF_CLK_SEL even when we are selecting the lane's own clock. This ensures that Linux's idea of the reference clock matches the hardware. We use the "local" clock mux for this instead of going through the ref clock network. Signed-off-by: Sean Anderson <sean.anderson@linux.dev> Link: https://lore.kernel.org/r/20240628205540.3098010-2-sean.anderson@linux.dev Signed-off-by: Vinod Koul <vkoul@kernel.org> [ Linux commit 687d6bccb28238fcfa65f7c1badfdfeac498c428 ] Fixes: 1d78d683496 ("phy: zynqmp: Add serdes/psgtr driver") Link: https://lore.kernel.org/r/20260106215501.727524-3-sean.anderson@linux.dev Signed-off-by: Michal Simek <michal.simek@amd.com>
2026-01-12phy: zynqmp: Allow variation in refclk rateSean Anderson
Due to limited available frequency ratios, the reference clock rate may not be exactly the same as the required rate. Allow a small (100 ppm) deviation. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Link: https://lore.kernel.org/r/20230711194542.898230-1-sean.anderson@seco.com Signed-off-by: Vinod Koul <vkoul@kernel.org> [ Linux commit 76009ee76e05e30e29aade02e788aebe9ce9ffd2 ] Link: https://lore.kernel.org/r/20260106215501.727524-2-sean.anderson@linux.dev Signed-off-by: Michal Simek <michal.simek@amd.com>
2026-01-09dm: core: Default to using DEVRES outside of xPLTom Rini
The devm alloc functions that we have may follow the Linux kernel model where allocations are (almost always) automatically free()'d. However, quite often we don't enable, in full U-Boot, the tracking and free()'ing functionality. This in turn leads to memory leaks because the driver author expects that since the functions have the same name as in the Linux Kernel they have the same behavior. In turn we then get functionally correct commits such as commit 00e1fed93c8c ("firmware: ti_sci: Fix memory leaks in devm_ti_sci_get_of_resource") that manually add these calls. Rather than manually tracking allocations and implementing free()s, rework things so that we follow expectations by enabling the DEVRES functionality (outside of xPL phases). This turns DEVRES from a prompted symbol to a symbol that must be select'd, and we now remove our non-managed alloc/free functions from outside of xPL builds. Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2025-11-06phy: renesas: Add Multi-Protocol PHY driver for R-Car X5HThanh Quan
Add PHY driver for Multi-Protocol PHY present on Renesas R-Car X5H R8A78000 SoC. Currently, the PHY driver only supports configuring the MPPHY for ethernet operation. Signed-off-by: Thanh Quan <thanh.quan.xn@renesas.com> Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> #Fix License-Identifier Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> [Marek: Clean up macros, indent, clock and reset handling in probe, rename the driver and add r8a78000- into compatible string, update commit message.]
2025-11-06phy: renesas: Add PCS driver for Renesas R-Car X5H R8A78000Tam Nguyen
Add support for the Ethernet Physical Coding Sublayer (PCS) controller on R-Car Gen5 SoCs, specifically the Renesas R-Car X5H R8A78000. The controller is based on the SERDES infrastructure used in previous R-Car generations, with updates for Gen5 register layout and features. Because majority of this driver is SoC-specific register programming, the majority of this driver is different enough from R8A779F0 SerDes driver to justify its own driver. Deduplication of the remaining bits of code does not yield any improvement. Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com> Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com> Signed-off-by: Thanh Quan <thanh.quan.xn@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> [Marek: Add missing clk_bulk_disable() in fail path. Drop always-true aneg_on setting. Reduce poll delay from 100s to 100ms. Use bulk reset operations to finalize reset handling.]
2025-11-04phy: imx8mq-usb: Add SPL support for i.MX8MQ, i.MX8MP, i.MX95, and i.MX94 ↵Alice Guo
USB3.0 PHY This patch adds SPL Kconfig option (SPL_PHY_IMX8MQ_USB) for the i.MX8MQ, i.MX8MP, i.MX95, and i.MX94 USB3.0 PHY driver, allowing the driver to be compiled and probed in SPL stage. Signed-off-by: Alice Guo <alice.guo@nxp.com>
2025-10-29phy: qcom-qmp-ufs: Import SM7150 tables from LinuxDanila Tikhonov
Import the init sequence for the UFS on SM7150. Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Signed-off-by: Jens Reidel <adrian@mainlining.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250831004602.699953-4-adrian@mainlining.org Signed-off-by: Casey Connolly <kcxt@postmarketos.org>
2025-10-29phy: qcom: Add SM6350 to QMP UFS PHY driverLuca Weiss
The UFS on SM6350 can reuse the SDM845 configuration, just like in Linux. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
2025-10-29phy: qcom: Rework Kconfig logic around MSM8916_USB_PHYTom Rini
This PHY driver is required by USB_EHCI_MSM and not useful on its own. Rather than have it be a prompted option, it should (and currently is) select'd by USB_EHCI_MSM. Remove the prompt for this option and then correct the dependency chain (it must select PHY). Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Casey Connolly <casey.connolly@linaro.org> Link: https://lore.kernel.org/r/20251003203927.1030052-1-trini@konsulko.com Signed-off-by: Casey Connolly <kcxt@postmarketos.org>
2025-10-24phy: ti: phy-j721e-wiz: Allow reinitialization when SERDES is pre-configuredHrushikesh Salunke
Move the SERDES configuration check after clock and reset initialization and change it from a hard failure to a skip of WIZ initialization. This allows the driver to probe successfully when the SERDES has been pre-configured by a previous boot stage (e.g., ROM or SPL). This approach aligns with how the Linux kernel handles pre-configured SERDES, where the driver gracefully skips reinitialization rather than failing to probe. Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
2025-10-13phy: marvell: Tighten MVEBU_COMPHY_SUPPORT dependenciesTom Rini
This driver cannot link without access to functions that are defined in files that are only build on some platforms. Express those requirements in Kconfig as well. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefan Roese <stefan.roese@mailbox.org>
2025-09-16phy: Reset init count on phy exit failureMarek Vasut
In case the PHY exit callback reports failure, reset init_count to 0 anyway, so the next attempt at PHY initialization might try to reinitialize the PHY and restore it to normal operation. Signed-off-by: Marek Vasut <marek.vasut@mailbox.org> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2025-09-08Merge tag 'v2025.10-rc4' into nextTom Rini
Prepare v2025.10-rc4
2025-08-31phy: rockchip: typec: Fix improper use of UCLASS_PHYJonas Karlman
The Rockchip TypeC glue driver improperly present itself as a UCLASS_PHY driver, without ever implementing the required phy_ops. This is something that in special circumstances can lead to a NULL pointer dereference followed by a SError crash. Change the glue driver to use UCLASS_NOP to fix this. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-31phy: rockchip: inno-usb2: Fix improper use of UCLASS_PHYJonas Karlman
The Rockchip USB2PHY glue driver improperly present itself as a UCLASS_PHY driver, without ever implementing the required phy_ops. This is something that in special circumstances can lead to a NULL pointer dereference followed by a SError crash. Change the glue driver to use UCLASS_NOP to fix this. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-31phy: rockchip: naneng-combphy: Use syscon_regmap_lookup_by_phandleJonas Karlman
Change to use syscon_regmap_lookup_by_phandle() helper instead of finding the syscon udevice and making a call to syscon_get_regmap(). No runtime change is expected with this simplication. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-31phy: rockchip: naneng-combphy: Simplify init opsJonas Karlman
The init ops for Rockchip COMBPHY driver is more complex than it needs to be, e.g. declaring multiple init functions that only differ in the error message. Simplify the init ops based on code from the Linux mainline driver. This change also ensure that errors returned from combphy_cfg() and reset_deassert_bulk() is propertly propagated to the caller. No other runtime change is expected with this simplication. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-31phy: rockchip: naneng-combphy: Fix Generic PHY reference countingJonas Karlman
Generic PHY reference counting helps ensure driver ops for init/exit and power on/off are called at correct state. For this to work the PHY driver must initialize PHY-id to a persistent value in of_xlate ops. The Rockchip COMBPHY driver does not initialize the PHY-id field, this typically lead to use of unshared reference counting among different struct phy instances. Initialize the PHY-id in of_xlate ops to ensure use of shared reference counting among all struct phy instances. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-08-31phy: rockchip: usbdp: Simplify init opsJonas Karlman
With working shared reference counting for Generic PHY ops there is no need for the Rockchip USBDP PHY driver to keep its own status (reference counting) handling. Simplify the init ops now that shared reference counting is working. This also removes the unused mode_change handling as part of the simplication. No runtime change is expected with this simplication. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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