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As in Linux with d78c0ced60 ("net: ravb: Make write access to CXR35 first
before accessing other EMAC register"), configure CXR31 and CXR35 correctly
on rzg2. MII mode does not work correctly unless those registers are
properly configured.
Signed-off-by: Mathieu Othacehe <othacehe@gnu.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
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The scsi_read function incorrectly decrements the block count twice
when handling large disks that trigger the CONFIG_SYS_64BIT_LBA code
path (reads beyond block 268,435,455). The variable 'blks' was being
decremented both inside the 64-bit LBA block and after the successful
scsi_exec() call, causing incorrect block count tracking and data
abort errors on large capacity disks.
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Tested-by: Tony Dinh <mibodhi@gmail.com>
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Remove duplicate '@parent' field documentation in struct mtk_composite.
There is no need to say the same thing twice.
Also fix spelling mistake in the word "parent" while we're at it.
Signed-off-by: David Lechner <dlechner@baylibre.com>
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In the last message sent in rockchip_i2c_xfer, the controller is
disabled (see rk_i2c_disable() in rk_i2c_read()/rk_i2c_write()), then
the STOP condition is sent (see rk_i2c_send_stop_bit() in
rockchip_i2c_xfer()) and the controller is disabled once again (see
rk_i2c_disable() right after).
The issue is that re-enabling the controller just to send the STOP
condition doesn't work. When, the controller is disabled, the SCL and
SDA lanes are not driven anymore and thus enter the idle mode where they
are kept high by the external HW pull-up. To send a STOP condition, one
needs to drive the SDA line so that a rising edge happens while SCL is
high. Experimentally (on PX30 and RK3399), when enabling the controller
to send a STOP condition after it's been disabled, the controller only
drives the SDA line to trigger the rising edge for the STOP condition,
leaving SCL undriven (and thus, high). This means, that because SDA is
high before this happens and that we need a rising edge, the controller
drives the SDA line low and then releases it, meaning we trigger a START
condition followed by a STOP condition:
SCL
_________
_____...
__ _____
_____... \/
SDA
^ STOP
^ START
This is illegal in I2C protocol[1]:
5. A START condition immediately followed by a STOP condition (void
message) is an illegal format. Many devices however are designed to
operate properly under this condition.
My guess is that the I2C controller IP knows that it makes only sense to
send a STOP condition after a START condition, meaning the controller is
already driving the SCL line low and neither the device nor controller
drive the SDA line after the last ACK/NACK as there's no need to, then
it needs to drive SDA, release SCL to make it high and then release the
SDA line. However, after it's been disabled, the SCL is already released
so the controller only essentially drives SDA and then releases it.
It happens that this seems to be breaking the SE050 Secure Element after
a few transfers in the middle of a transfer where it starts clock
stretching the bus forever. It may be related to Errata 3.2[2] but the
description of the setup isn't an exact match to the current situation.
It seems to be required to disable the I2C controller between messages
as the Linux kernel states that "The HW is actually not capable of
REPEATED START. But we can get the intended effect by resetting its
internal state and issuing an ordinary START.". Between messages, this
logic seems fine as I get an Sr (repeated START condition) before
starting the next message in the transfer without a STOP condition.
However, we should NOT disable the controller after the last message in
the transfer otherwise we do this illegal START condition followed by
the STOP condition, hence the added check.
[1] https://www.nxp.com/docs/en/user-guide/UM10204.pdf 3.1.10 The target address and R/W bit point 5
[2] https://www.nxp.com/docs/en/errata/SE050_Erratasheet.pdf
Fixes: c9fca5ec8849 ("rockchip: i2c: don't sent stop bit after each message")
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Heiko Schocher <hs@nabladev.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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The I2C_CON_LASTACK is kind of a misnomer as setting it means sending a
NACK as last byte acknowledge when the controller is in receive mode. It
should therefore be used only when there's no more data to transfer
after this.
Move the comment in the proper if block.
Sync the comment with the Linux kernel's while at it so it's more
explicit.
Fixes: 5deaa530280f ("rockchip: i2c: fix >32 byte reads")
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Heiko Schocher <hs@nabladev.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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I2C_CON_STOP is a flag to be used for the con register, where it is bit
4 to send the STOP condition.
To enable the interrupt the controller sends to tell it's finished
sending the STOP condition, it's the ien register at bit 5.
Let's use the proper offset.
My hunch is that enabling the interrupt is useless as the interrupt
status register is always up-to-date and enabling the interrupt is just
so that the interrupt is available via the GIC. However, U-Boot has no
interrupt support and the logic was working well before this patch. This
is just so people aren't side-tracked when debugging I2C issues on
Rockchip by checking all writes are proper.
Fixes: 3437469985df ("rockchip: Add I2C driver")
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Heiko Schocher <hs@nabladev.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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Add support for the Renesas MFIS mailbox, which provides an interface
between the different CPU Cores, such as AP System Core domain and the
Realtime Core domain, SCP Core domain and AP System Core domain or
Realtime Core domain and AP System Core domain or Realtime Core domain.
Signed-off-by: Tuyen Dang <tuyen.dang.xa@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Update the driver
[Marek: Rename the driver to renesas-mfis, simplify the driver.
Always use only one TX channel and no RX channel, drop all
unnecessary code. Perform 1ms delay in send callback which
is perfectly fine to do in U-Boot which does RX polling]
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The current state of SCP on Renesas R-Car Gen5 is not yet final and
is still missing full clock control, the clock control is exposed as
separate enable/disable and rate controls.
Temporarily introduce custom local compound clock, which are used as
an adaptation layer between U-Boot clock tree and current state of
SCP, and which bind two SCP clock into a single compound clock, which
provides both enable/disable and rate controls.
This is mainly meant to be used by SD/eMMC controller, to allow the
driver to both turn its clock on and off, and also obtain the current
clock rate. This is going to be removed once the SCP clock protocol
solidifies.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
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https://source.denx.de/u-boot/custodians/u-boot-at91
First set of u-boot-at91 fixes for the 2026.01 cycle:
This small fixes set includes a fix on the mtd pmecc driver.
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- Assorted updates
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https://source.denx.de/u-boot/custodians/u-boot-socfpga
This pull request delivers a broad set of improvements across the
SoCFPGA family, including Agilex5, Cyclone V, SoC64, and common code.
Key updates include refined boot flows, new driver enablement, handoff
tooling enhancements, and several stability fixes.
Highlights:
* Agilex5:
- Enable FAT-based environment storage
- MMC driver restores legacy clkmgr-based clock lookup
- Cleanup of MMC raw mode enablement logic
* Cyclone V:
- SPL FAT boot support and updated bootcmd sequence
- Disable SPL SPI to prevent contention with FAT-based boot
- New board handoff script and BSP generator tooling
- Optimized Makefile support for SoCFPGA handoff workflows* New drivers:
- Cadence xSPI driver with full protocol and command support
- SPL enablement for DW APB GPIO controller
* Networking:
- xgmac MDIO now supports Clause 45 read/write operations
* NAND / SoC64:
- Enable ONFI detection in Denali NAND controller for SoC64 devices
* DTS and board updates:
- Sync common SoCFPGA U-Boot DTS with kernel sources
- Fixes for FPGA2SDRAM configuration and SoCFPGA boot stall behavior
- Vining_FPGA migrated to the modern LED framework
- Device tree relocation no longer forced off for Vining FPGA
* Tooling:
- Introduces a new Python-based Cyclone V BSP generator
covering EMIF, IOCSR, HPS, XML parsing, rendering, and documentation
to simplify board enablement and handoff regeneration workflows
Overall, this series improves boot robustness, enhances xSPI and MDIO
capabilities, modernizes board support, and introduces new tooling to
streamline SoCFPGA handoff generation.
Pipelines test passing
https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/28569
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bcm54210e_config() configures the RGMII delays and then calls
bcm5461_config(). But the latter will do a PHY soft reset and thus
resets the delay settings again. Call bcm5461_config() first to fix it.
Fixes: cba79a1b2e11 ("net: phy: broadcom: add support for BCM54210E")
Signed-off-by: Michael Walle <mwalle@kernel.org>
Reviewed-by: Rafał Miłecki <rafal@milecki.pl>
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According to the TI DP83869HM datasheet Revision D (June 2025), section
7.6.1.41 STRAP_STS Register, the STRAP_OPMODE bitmask is bit [11:9].
Fix this.
In case the PHY is auto-detected via PHY ID registers, or not described
in DT, or, in case the PHY is described in DT but the optional DT property
"ti,op-mode" is not present, then the driver reads out the PHY functional
mode (RGMII, SGMII, ...) from hardware straps.
Currently, all upstream users of this PHY specify both DT compatible string
"ethernet-phy-id2000.a0f1" and ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>
property, therefore it seems no upstream users are affected by this bug.
The driver currently interprets bits [2:0] of STRAP_STS register as PHY
functional mode. Those bits are controlled by ANEG_DIS, ANEGSEL_0 straps
and an always-zero reserved bit. Systems that use RGMII-to-Copper functional
mode are unlikely to disable auto-negotiation via ANEG_DIS strap, or change
auto-negotiation behavior via ANEGSEL_0 strap. Therefore, even with this bug
in place, the STRAP_STS register content is likely going to be interpreted
by the driver as RGMII-to-Copper mode.
However, for a system with PHY functional mode strapping set to other mode
than RGMII-to-Copper, the driver is likely to misinterpret the strapping
as RGMII-to-Copper and misconfigure the PHY.
For example, on a system with SGMII-to-Copper strapping, the STRAP_STS
register reads as 0x0c20, but the PHY ends up being configured for
incompatible RGMII-to-Copper mode.
Fixes: f3e22eea815d ("net: phy: add TI DP83869HM ethernet driver")
Signed-off-by: Thanh Quan <thanh.quan.xn@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Use FIELD_GET()
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Restore legacy implementation of retrieving clkmgr base address from
mach-socfpga/misc.c driver for our legacy devices.
Excluding Agilex7/7M from this implementation as these devices' clock
driver is already following clock driver model and is supporting
enable/disable APIs.
The legacy devices' clock driver will have to be refactored to support
driver model which enables us to support enable/disable APIs for these
devices.
Fixes: ab27182cac8f ("mmc: socfpga_dw_mmc: Enable/disable SDMMC clock via API")
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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Enable ONFI parameter page detection for SoCFPGA SoC64 devices by
selecting SYS_NAND_ONFI_DETECTION in the NAND_DENALI Kconfig entry.
This allows SoCFPGA SoC64 platforms using the Denali NAND controller
to automatically detect NAND parameters via the ONFI interface instead
of relying on hardcoded configuration values.
The selection is limited to TARGET_SOCFPGA_SOC64 to avoid affecting
non-SoC64 platforms that use legacy NAND handling.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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This patch ports the Cadence xSPI controller driver from
the Linux kernel. The controller supports three operating modes:
1. ACMD (Auto Command) mode
- Includes PIO and CDMA submodes.
- CDMA mode uses linked descriptors for high-performance,
low-overhead operation.
- PIO mode is suitable for simple, single-command transactions.
2. STIG (Software Triggered Instruction Generator) mode
- Issues low-level 128-bit instructions to memory.
- Uses the Slave DMA interface for data transfers.
3. Direct mode
- Enables direct data access through the slave interface
without commands.
Currently, only the STIG work mode is enabled. Additional modes will be
supported in future updates.
At the same time, also enabling the kconfig option for xSPI driver.
This driver has been ported and functionally verified on the Intel Simics
platform. It is intended for evaluation and experimental use at this stage.
Link: https://lore.kernel.org/all/1632038734-23999-1-git-send-email-pthombar@cadence.com/
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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Add SPL_DWAPB_GPIO configuration option to enable the Designware APB
GPIO driver in SPL builds.
Changes:
- Add SPL_DWAPB_GPIO Kconfig option with SPL_DM_GPIO dependency
- Update Makefile to use CONFIG_$(PHASE_)DWAPB_GPIO pattern for
conditional compilation in both SPL and main U-Boot builds
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
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Currently, clause-22 format is supported. This change adds
support for clause-45 format.
Signed-off-by: Nikunj Kela <nikunj.kela@sima.ai>
Reviewed-by: Boon Khai Ng <boon.khai.ng@altera.com>
Tested-by: Boon Khai Ng <boon.khai.ng@altera.com>
Reviewed-by: Boon Khai Ng <boon.khai.ng@altera.com>
Tested-by: Boon Khai Ng <boon.khai.ng@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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https://source.denx.de/u-boot/custodians/u-boot-raspberrypi
Updates for RPi for 2026.01-rc4:
- rpi: Fix DRAM size reporting to show total RAM
- rpi: Use the U-Boot control FDT for fdt_addr
- pinctrl: bcm283x: Add GPIO pull-up/down control for BCM2835 and BCM2711
- rpi: Fix compilation with larger configs
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We should avoid overwhelming users with non-essential messages.
'Register NbrPorts' is a debug message for EHCI. Do the same for XHCI.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
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CONFIG_USB_EHCI_PCI cannot work without CONFIG_PCI.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
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Currently, the bind callback of the driver namely am65_cpsw_nuss_bind()
registers all ethernet ports including the ones that have been disabled
in the device-tree. Since the ports that have been disabled are ought to
be ignored, fix the implementation to register only the enabled ports as
indicated by their 'status' in their respective device-tree node.
Fixes: 3943531a5468 ("net: ti: am65-cpsw-nuss: Define bind method for CPSW driver")
Reported-by: Wadim Egorov <w.egorov@phytec.de>
Closes: https://patch.msgid.link/8b4ac072-125c-493b-b12a-f0a4e9d56e7e@phytec.de
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
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The helper function "ti_pd_get()" is responsible for powering on a
domain if it is powered off. In the current implementation, if a power
domain is determined to be powered off - no prior users and the PDCTL
register indicates that the user desired state is OFF, then powering on
the domain constitutes setting 'PDCTL_STATE_ON' field of the PDCTL
register.
While the current implementation indeed requests the power domain to be
transition to the ON state, the helper function "ti_pd_get()" doesn't
verify that the power domain has 'transitioned' to the ON state before
returning to its caller. As a result, it is possible that the device(s)
belonging to the power domain may be accessed before it is truly powered
on, leading to a bus abort.
Fix this by waiting for the power domain to transition to the ON state
by using "ti_pd_wait()" before returning from "ti_pd_get()".
Fixes: 144464bd2c67 ("power: domain: Introduce driver for raw TI K3 PDs")
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Tested-by: Hrushikesh Salunke <h-salunke@ti.com>
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There is a condition guard which ensures that the GPIO node, indeed
describes a GPIO controller.
if (!fdtdec_get_bool(blob, node, "gpio-controller"))
continue;
Since the bank base is being incremented in the loop, it is done so
irrespective of whether the node is a GPIO controller or not. This leads
to the incorrect resolution of bank base addresses.
Move it out of the loop, and instead increment the bank base address
only if the driver successfully binds a GPIO controller.
Reviewed-by: Henrik Grimler <henrik@grimler.se>
Fixes: b8809e60cdb5 ("dm: exynos: gpio: Convert to driver model")
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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This patch adds support for configuring GPIO pull-up and pull-down
resistors in the BCM283x pinctrl driver. It implements the brcm,pull
device tree property to control pin bias settings.
The implementation follows the hardware-specific pull control
mechanisms:
- BCM2835: two-step GPPUD register sequence
- BCM2711: direct per-pin control registers
This enables device tree configurations to specify pull-up, pull-down,
or no bias for individual GPIO pins.
Tested on Raspberry Pi boards with both BCM2835 and BCM2711 SoCs.
Signed-off-by: Cibil Pankiras <cibil.pankiras@egym.com>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
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"timing" and "timing_res_idx" are unused and not exist in Linux driver,
let's remove them.
Signed-off-by: Zixun LI <admin@hifiphile.com>
Acked-by: Alexander Dahl <ada@thorsis.com>
Reviewed-by: Eugen Hristev <eugen.hristev@linaro.org>
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Setup the pmecc data setup time as 3 clock cycles for 133MHz as
recommended by the datasheet.
Backported from Linux: f55f552a7c7e0a1 ("mtd: rawnand: atmel: set pmecc
data setup time")
Fixes: a490e1b7c017c ("nand: atmel: Add pmecc driver")
Signed-off-by: Zixun LI <admin@hifiphile.com>
Tested-by: Alexander Dahl <ada@thorsis.com>
Reviewed-by: Eugen Hristev <eugen.hristev@linaro.org>
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https://source.denx.de/u-boot/custodians/u-boot-ufs
- Sort again the UFS Kconfig & Makefile
- Use unique name for the rcar-gen5 ufs driver
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https://source.denx.de/u-boot/custodians/u-boot-microblaze
CI: https://source.denx.de/u-boot/custodians/u-boot-microblaze/-/pipelines/28413
AMD/Xilinx/FPGA changes for v2026.01-rc3
- Align brcp1 boot.bin location
- Fix MB-V compilation warning when AXI enet is enabled
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Fix compiler warnings about casting integers to pointers of different
sizes by using uintptr_t as intermediate type. This ensures proper
type conversion across 32-bit and 64-bit architectures.
Signed-off-by: Sai Varun Venkatapuram <saivarun.venkatapuram@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/11b1d9b1a5589d06cff724e807832f366794c075.1762510401.git.michal.simek@amd.com
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We found that some serial console may pull TX line to GROUND during board
boot time. Airoha uses TX line as one of it's BOOT pins. This will lead
to booting in RESERVED boot mode.
It was found that some flashes operates incorrectly in RESERVED mode.
Micron and Skyhigh flashes are definitely affected by the issue,
Winbond flashes are NOT affected.
Details:
--------
DMA reading of odd pages on affected flashes operates incorrectly. Page
reading offset (start of the page) on hardware level is replaced by 0x10.
Thus results in incorrect data reading. Usage of UBI make things even
worse. Any attempt to access UBI leads to ubi damaging. As result OS loading
becomes impossible.
Non-DMA reading is OK.
This patch detects booting in reserved mode, turn off DMA and print big
fat warning.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
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The spinand driver do 3 type of dirmap requests:
* read/write whole flash page without oob
(offs = 0, len = page_size)
* read/write whole flash page including oob
(offs = 0, len = page_size + oob_size)
* read/write oob area only
(offs = page_size, len = oob_size)
The trick is:
* read/write a single "sector"
* set a custom sector size equal to offs + len. It's a bit safer to
round up "sector size" value 64.
* set the transfer length equal to custom sector size
And it works!
Thus we can find all data directly from dirmap request, so flash specific
parameters is not needed anymore. Also
* airoha_snand_nfi_config(),
* airoha_snand_nfi_setup()
functions becomes unnecessary.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
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Set custom sector size equal to flash page size including oob. Thus we
will always read a single sector. The maximum custom sector size is
8187, so all possible flash sector sizes are supported.
This patch is a necessary step to avoid usage of flash specific
parameters.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
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REG_SPI_NFI_SECCUS_SIZE registers
This just reduce the number of modification of REG_SPI_NFI_CNFG and
REG_SPI_NFI_SECCUS_SIZE registers during dirmap operation.
This patch is a necessary step to avoid usage of flash specific
parameters.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
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spi-airoha-snfi uses custom sector size in REG_SPI_NFI_SECCUS_SIZE
register, so setting of page/oob sizes in REG_SPI_NFI_PAGEFMT is not
required.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
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During writing, the entire flash page (including OOB) will be updated
with the values from the temporary buffer, so we need to fill the
untouched areas of the buffer with 0xff value to prevent accidental
data overwriting.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
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Airoha snfi spi controller supports acceleration of DUAL/QUAD
operations, but does not supports DUAL_IO/QUAD_IO operations.
Luckily DUAL/QUAD operations do the same as DUAL_IO/QUAD_IO ones,
so we can issue corresponding DUAL/QUAD operation instead of
DUAL_IO/QUAD_IO one.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
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This driver can accelerate single page operations only, thus
continuous reading mode should not be used.
Continuous reading will use sizes up to the size of one erase block.
This size is much larger than the size of single flash page. Use this
difference to identify continuous reading and return an error.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
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This patch speed up cache reading/writing/updating opearions.
It was tested on en7523/an7581 and some other Airoha chips.
It will speed up
* page reading/writing without oob
* page reading/writing with oob
* oob reading/writing (significant for UBI scanning)
The only know issue appears in a very specific conditions for en7523 family
chips only.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
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Booting without this patch and disabled dirmap support results in
[ 2.980719] spi-nand spi0.0: Micron SPI NAND was found.
[ 2.986040] spi-nand spi0.0: 256 MiB, block size: 128 KiB, page size: 2048, OOB size: 128
[ 2.994709] 2 fixed-partitions partitions found on MTD device spi0.0
[ 3.001075] Creating 2 MTD partitions on "spi0.0":
[ 3.005862] 0x000000000000-0x000000020000 : "bl2"
[ 3.011272] 0x000000020000-0x000010000000 : "ubi"
...
[ 6.195594] ubi0: attaching mtd1
[ 13.338398] ubi0: scanning is finished
[ 13.342188] ubi0 error: ubi_read_volume_table: the layout volume was not found
[ 13.349784] ubi0 error: ubi_attach_mtd_dev: failed to attach mtd1, error -22
[ 13.356897] UBI error: cannot attach mtd1
If dirmap is disabled or not supported in the spi driver, the dirmap requests
will be executed via exec_op() handler. Thus, if the hardware supports
dual/quad spi modes, then corresponding requests will be sent to exec_op()
handler. Current driver does not support such requests, so error is arrised.
As result the flash can't be read/write.
This patch adds support of dual and quad wires spi modes to exec_op() handler.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
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This operation is not needed because airoha_snand_write_data() and
airoha_snand_read_data() will properly handle data transfers above
SPI_MAX_TRANSFER_SIZE.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
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Coverity finds a potential integer overflow in the following code:
ncycles += ((op->data.nbytes * 8) / op->data.buswidth) / (op->data.dtr ? 2 : 1);
A quick analysis shows that the only caller of the suspicious code is the
spinand_select_op_variant() function from the drivers/mtd/nand/spi/core.c
file.
According to the code the value of op->data.nbytes is equal to
nanddev_per_page_oobsize(nand) + nanddev_page_size(nand)
Therefore it's maximum value a bit larger than 4Kb (I never seen flashes
with page size large than 4Kb). So op->data.nbytes always fits within
13 bits. As result an overflow will never happen.
Anyway it's better fix an issue to eliminate the error message.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
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This option is only meaningful within the davinci nand driver, so drop
the statement here (which had no effect).
Signed-off-by: Tom Rini <trini@konsulko.com>
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Add support for FudanMicro FM25S01A SPI NAND.
This driver is ported from linux v6.18 and tested on a MT7981 board.
Link: https://lore.kernel.org/linux-mtd/20250824170013.3328777-1-cnsztl@gmail.com/
Reviewed-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
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The hidden symbol SPL_SYS_NAND_SELF_INIT was not being used correctly
leading to Kconfig dependency issues seen with "make allyesconfig". As
it's a select'd symbol we don't need to have a depends line on it, and
then in turn we need to also update the logic on SYS_NAND_PAGE_SIZE and
SYS_NAND_OOBSIZE.
Signed-off-by: Tom Rini <trini@konsulko.com>
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All these chips are dual and quad capable. They are also DTR capable,
but the core is not yet ready for that.
Performances of all chips are comparable at 30MHz and are as follow:
Eraseblock single read speed: 938kiB/s
Eraseblock dual read speed: 1068kiB/s
Eraseblock quad read speed: 3751kiB/s
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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https://source.denx.de/u-boot/custodians/u-boot-stm
CI: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/28392
dhelectronics:
- Move dh_add_item_number_and_serial_to_env() to common code
- Read values from M24256 write-lockable page on STM32MP13xx DHCOR
- Add MAC address readout from fuses on DH STM32MP1 DHSOM
- Keep the reg11 and reg18 regulators always enabled on STM32MP13xx DHCOR.
- Fix boot for stm32mp15xx-dhsom.
- Fix build of ST DFU virt code on DH STM32MP1 DHSOM
- Introduce DH STM32MP13x target.
STM32MP2:
- Add support for stm32mp257-dk board.
- Fix arm, smc-id value for stm32mp23/25.
- Fix stm32mp235f-dk boot (add syscon compatible, add txbyteclk).
- Add display support:
- Introduce LVDS driver.
- Add LTDC support.
- Add Ethernet support for stm32mp255.
STM32MP13:
- Add ADC support.
- Add power check for stm32mp135f-dk board.
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Initially there was only one DSI bridge with one panel attached to this
device. This explained the call to uclass_first_device_err(UCLASS_PANEL,
...) which worked fine at the time.
Now that multiple bridges and panels, with different technologies, can
be plugged onto the board this way to get the panel device is outdated.
The lookup is done is two steps. First we circle through the
UCLASS_VIDEO_BRIDGE, and once we get one, we search through its
endpoints until we get a UCLASS_PANEL device available.
Acked-by: Yannick Fertre <yannick.fertre@foss.st.com>
Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
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STM32MP2 SoCs feature a new version of the LTDC IP. This new version
features a bus clock, as well as a 150MHz pad frequency. Add its
compatible to the list of device to probe and handle quirks. The new
hardware version features a bus clock.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Acked-by: Yannick Fertre <yannick.fertre@foss.st.com>
Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
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The LVDS Display Interface Transmitter handles the LVDS protocol:
it maps the pixels received from the upstream Pixel-DMA (LTDC)
onto the LVDS PHY.
The LVDS controller driver supports the following high-level features:
• FDP-Link-I and OpenLDI (v0.95) protocols
• Single-Link or Dual-Link operation
• Single-Display or Double-Display (with the same content
duplicated on both)
• Flexible Bit-Mapping, including JEIDA and VESA
• RGB888 or RGB666 output
• Synchronous design, with one input pixel per clock cycle
• No resolution limitation.
Acked-by: Yannick Fertre <yannick.fertre@foss.st.com>
Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
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