summaryrefslogtreecommitdiff
path: root/drivers
AgeCommit message (Collapse)Author
2025-01-27ram: k3-ddrss: Set SDRAM_IDX using device private data, ddr_ram_sizeSanthosh Kumar K
The SDRAM_IDX in DDRSS_V2A_CTL_REG describes the number of address bits minus 16 that are used to determine the mask used to detect memory rollover and prevent aliasing and false coherency issues. Set SDRAM_IDX using the device private data, ddr_ram_size for K3 family of SoCs. Signed-off-by: Santhosh Kumar K <s-k6@ti.com> Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2025-01-27Merge tag 'u-boot-imx-master-20250127' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/24366 - Refactor the imx pinctrl driver. - Enable optional ENETREF clock on i.MX95 - Remove optional from tee-os entry on the i.MX8M u-boot devicetrees.
2025-01-27net: fsl_enetc: Enable optional ENETREF clock on i.MX95Marek Vasut
The ENETCv4 port DT nodes on i.MX95 may contain optional clock phandle to IMX95_CLK_ENETREF "ref" clock. These "ref" clock must be enabled for the ethernet to work. These "ref" clock are enabled after cold boot, but when the system booted Linux and rebooted, those "ref" clock might have been disabled in the process, which would make ethernet inoperable after reboot. Make sure those "ref" clock are always correctly enabled. Signed-off-by: Marek Vasut <marex@denx.de>
2025-01-26Merge a patch series for mx313xx RTC driversTom Rini
This series of patches from Mark Tomlinson fixes two problems with the mx313xx series of RTC devices. Link: https://lore.kernel.org/r/20250120015941.1849667-1-mark.tomlinson@alliedtelesis.co.nz
2025-01-26drivers: rtc: max313xx: Ensure correct date is read after settingMark Tomlinson
When setting the time on the MAX31343, the time is not updated for one second, and reading the time in this interval will give the old time. Wait one second after writing so that the date command will show the correct time when setting the clock. Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz> Cc: Chris Packham <judge.packham@gmail.com> Reviewed-by: Chris Packham <judge.packham@gmail.com>
2025-01-26drivers: rtc: max313xx: Fix setting years 2100-2199Mark Tomlinson
An invalid calculation made setting years 2100-2199 impossible. Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz> Cc: Chris Packham <judge.packham@gmail.com> Reviewed-by: Chris Packham <judge.packham@gmail.com>
2025-01-25pinctrl: imx: Split MMIO accessors into pinctrl-imx-mmio.cMarek Vasut
Split MMIO accessors into pinctrl-imx-mmio.c and build this file only if Kconfig symbol PINCTRL_IMX_MMIO is selected. Select PINCTRL_IMX_MMIO Kconfig symbol for all but pinctrl-imx8.c driver, which does not use the MMIO accessors. This reduces the amount of code compiled on platforms which do not use the code. No functional change. Signed-off-by: Marek Vasut <marex@denx.de>
2025-01-25pinctrl: imx: Fold imx_pinctrl_set_state_scu() from pinctrl-imx8.cMarek Vasut
The only user of the SCU pinctrl code is pinctrl-imx8.c , fold the entire pinctrl-scu.c code into pinctrl-imx8.c and remove the matching Kconfig symbols and Makefile entries. No functional change. Signed-off-by: Marek Vasut <marex@denx.de>
2025-01-25pinctrl: imx: Split imx_pinctrl_set_state_scu() from ↵Marek Vasut
imx_pinctrl_set_state_mmio() Call imx_pinctrl_set_state_common() from imx_pinctrl_scu_conf_pins(), rename imx_pinctrl_scu_conf_pins() to imx_pinctrl_set_state_scu(). Get rid of the unnecessary ifdeffery in pinctrl-imx.h in the process. Remove all SCU support from pinctrl-imx.c imx_pinctrl_set_state_mmio() which makes that function a pure MMIO pinctrl configuration accessor. Update pinctrl-imx8.c to call imx_pinctrl_set_state_scu directly. No functional change. This patch is best viewed with git show -w due to indent change. Signed-off-by: Marek Vasut <marex@denx.de>
2025-01-25pinctrl: imx: Split imx_pinctrl_set_state() into common and mmio partsMarek Vasut
Split imx_pinctrl_set_state() into imx_pinctrl_set_state_common() and imx_pinctrl_set_state_mmio(). The former does the common configuration parsing, the later does call imx_pinctrl_set_state_common() and then does pin configuration using either SCU or MMIO accesses. The SCU part is going to be moved out in follow up patches. This is a preparatory patch for follow up pinctrl drivers which do not use the MMIO accessors, but some other means, like SCU or otherwise. Those will call the common imx_pinctrl_set_state_common() function wrapped into some other imx_pinctrl_set_state_*() function, in a way similar to imx_pinctrl_set_state_mmio() does so for MMIO accesses. Update all imx_pinctrl_set_state_mmio() call sites to call imx_pinctrl_set_state_mmio() instead. No functional change. Signed-off-by: Marek Vasut <marex@denx.de>
2025-01-25pinctrl: imx: Rename imx_pinctrl_remove() to imx_pinctrl_remove_mmio()Marek Vasut
The current implementation of imx_pinctrl_remove() is specific to the MMIO accessor implementation, rename the function to imx_pinctrl_remove_mmio() to make this obvious. No functional change. Signed-off-by: Marek Vasut <marex@denx.de>
2025-01-25pinctrl: imx: Split imx_pinctrl_probe() into common and mmio partsMarek Vasut
Split imx_pinctrl_probe() into imx_pinctrl_probe_common() and imx_pinctrl_probe_mmio(). The former does the common setup, the later does the common setup and MMIO access configuration. The common setup can be used as-is for SCU based systems, update the pinctrl-imx8 to call only the common setup, update all the other pinctrl drivers to call imx_pinctrl_probe_mmio(). No functional change. Signed-off-by: Marek Vasut <marex@denx.de>
2025-01-25pinctrl: imx: Inline struct imx_pinctrl_soc_info access into probeMarek Vasut
The probe function is identical across all the pinctrl drivers. Inline the imx_pinctrl_soc_info access into imx_pinctrl_probe() and drop all the duplicate probe functions. No functional change. Signed-off-by: Marek Vasut <marex@denx.de>
2025-01-25pinctrl: imx: Drop .remove callback for SCU variantMarek Vasut
The return callback for SCU variant of the pinctrl drivers does nothing but returns 0. Remove the return callback from the SCU driver itself, that has the same effect. No functional change. Signed-off-by: Marek Vasut <marex@denx.de>
2025-01-25pinctrl: imx: Rename imx_pinctrl_ops to match driversMarek Vasut
Rename the structure instances to match driver names, so they can be easily looked up e.g. in objdump and readelf outputs. No functional change. Signed-off-by: Marek Vasut <marex@denx.de>
2025-01-25pinctrl: imx: Push imx_pinctrl_ops into drivers and staticizeMarek Vasut
Move imx_pinctrl_ops into drivers and staticize. This is preparatory patch for follow up pinctrl drivers which will not use this variant of imx_pinctrl_ops content. This should not change size, as most of the deployments compiled in one pinctrl driver anyway. No functional change. Signed-off-by: Marek Vasut <marex@denx.de>
2025-01-24treewide: Replace Maximumm with Maximum in Kconfig symbol descriptionMarek Vasut
Replace Maximumm with Maximum in Kconfig symbol description, fix a typo. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Michal Simek <michal.simek@amd.com>
2025-01-23Merge tag 'u-boot-socfpga-next-20250124' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-socfpga 1. Bug fixed for doorbell in secure device manager mailbox driver 2. Enhancement on SoCFPGA dwc_eth_xgmac driver 3. Enhancement on DW MAC driver 4. Improved the error message and status for SoC64 device FPGA configuration driver 5. Updated existing watchdog in system manager to support new SM device
2025-01-24fpga: intel_sdm_mb: add support for query SDM config error and statusBoon Khai Ng
Currently the FPGA reconfig status only return a single error status which make the debugging of FPGA reconfiguration hard. This patch is to expose the error status, major error code and minor error code, for the FPGA reconfig to upper layer app. Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2025-01-24net: dwc_eth_xgmac_socfpga: Add support for distinct mac-mode and phy mode.Boon Khai Ng
This patch adds support for configuring the ethernet MAC mode independently from the PHY mode on our SoC FPGA board. Specifically, this is necessary for a scenario where the ethernet controller MAC is connected to the FPGA HVIO with a different GMII interface, and the FPGA output is routed to the PHY using a RGMII interface. To support this configuration, a mechanism is introduced to handle separate MAC mode settings, ensuring that the MAC controller and PHY can operate correctly with their respective interface modes. If mac-mode is not defined, the MAC mode will default to the PHY mode, ensuring compatibility and proper operation between the MAC and PHY. Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2025-01-24net: dwc_eth_xgmac: Add device name for the error message.Boon Khai Ng
Agilex5 having several ethernet instance, adding the device name at the error message to differentiate between which instance is having issue. Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2025-01-24net: dwc_eth_xgmac_socfpga: Add support for rgmii-id mode.Boon Khai Ng
An issue was identified where selecting the phy-mode as rgmii-id in the device tree source (DTS) would cause the `dwc_eth_xgmac_socfpga` driver to raise an unsupported phy mode error. From the MAC controller's perspective, the rgmii and rgmii-id phy modes are effectively identical. To address this, both modes will now be configured to rgmii in the MAC controller. This change ensures that the rgmii-id phy mode is properly supported without error. Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2025-01-24net: designware: socfpga: Add RGMII-ID supportRufus Segar
This patch adds support for the "rgmii-id", "rgmii-rxid", and "rgmii-txid" modes for the dwmac_socfpga driver. Signed-off-by: Rufus Segar <rhs@riseup.net>
2025-01-23Merge patch series "MediaTek ethernet driver refactor and updates"Tom Rini
Weijie Gao <weijie.gao@mediatek.com> says: This patch series will split the switch initialization code from mtk_eth driver into their own files and then add new SoC and switch support. Link: https://lore.kernel.org/r/cover.1736498083.git.weijie.gao@mediatek.com
2025-01-23Merge patch series "Add bitbang feature for npcm8xx and driver"Tom Rini
Michael Chang <zhang971090220@gmail.com> says: I am resubmitting the patch titled "Add bitbang feature for npcm8xx and driver" for review and inclusion in the upstream project. Driver didn't support bitbang feature. Add bb_miiphy_bus function for driver and open feature for npcm8xx the log is as below: ------------------------------------------------- U-Boot 2024.10-g30b9cdaf2df5-dirty (Jan 09 2025 - 00:57:37 +0000) CPU-0: NPCM845 A1 @ Model: Nuvoton npcm845 Development Board (Device Tree) DRAM: 1 GiB RNG: NPCM RNG module bind OK OTP: NPCM OTP module bind OK AES: NPCM AES module bind OK SHA: NPCM SHA module bind OK I/TC: Reserved shared memory is enabled I/TC: Dynamic shared memory is enabled I/TC: Normal World virtualization support is disabled I/TC: Asynchronous notifications are disabled Core: 649 devices, 28 uclasses, devicetree: separate WDT: Not starting watchdog@901c MMC: sdhci@f0842000: 0 Loading Environment from SPIFlash... SF: Detected w25q512jvq with page size 256 Bytes, erase size 64 KiB, total 64 MiB OK In: serial@0 Out: serial@0 Err: serial@0 Net: eth0: eth@f0802000, eth1: eth@f0804000, eth3: eth@f0808000 Hit any key to stop autoboot: 0 U-Boot> U-Boot> U-Boot>setenv ipaddr 192.168.16.3 U-Boot>ping 192.168.16.12 eth@f0802000 Waiting for PHY auto negotiation to complete ......... TIMEOUT ! Could not initialize PHY eth@f0802000 eth@f0804000 Waiting for PHY auto negotiation to complete ......... TIMEOUT ! Could not initialize PHY eth@f0804000 Speed: 100, full duplex Using eth@f0808000 device host 192.168.16.12 is alive Link: https://lore.kernel.org/r/20250117104540.1580343-1-zhang971090220@gmail.com
2025-01-23net: designware: Add bitbang feature for designware driver.Michael Chang
Add bb_miiphy_bus function for designware bitbang feature. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Signed-off-by: Michael Chang <zhang971090220@gmail.com>
2025-01-23net: mediatek: add support for Airoha AN8855 ethernet switchWeijie Gao
Airoha AN8855 is a 5-port gigabit switch with a 2.5G HSGMII CPU port Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-01-23net: mediatek: add support for MediaTek MT7987 SoCWeijie Gao
This patch adds support for MediaTek MT7987. MT7987 features MediaTek NETSYS v3, similar to MT7988, features three GMACs which support 2.5Gb HSGMII. One 2.5Gb PHY is also embedded an can be connected to a dedicated GMAC. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-01-23net: mediatek: split ethernet switch code from mtk_eth.cWeijie Gao
mtk_eth.c contains not only the ethernet GMAC/DMA driver, but also some ethernet switch initialization code. As we may add more switch support in the future, it's better to move them out of mtk_eth.c to avoid increasing the code complexity. Since not all switches are supported for a particular board, Kconfig options are added to allow user to select which switch should be built into u-boot. If multiple switches are selected, auto-detecting can also be enabled. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-01-23pci: mediatek: add support for multiple ports in mediatek pcie gen3 driverWeijie Gao
One MediaTek PCIe Gen3 controller has only one port, where PCI bus 0 on this port represents the controller itself and bus 1 represents the external PCIe device. If multiple PCIe controllers are probed in U-Boot, U-Boot will use bus numbers greater than 2 as input parameters. Therefore, we should convert the BDF bus number to either 0 or 1 by subtracting the offset by controller->seq_. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-01-23pwm: mediatek: add pwm3 support for mt7981Weijie Gao
This patch adds pwm channel 2 (pwm3) support for mt7981 Signed-off-by: Sam Shih <sam.shih@mediatek.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-01-23spi: mtk_spim: check slave device mode in spi-mem's supports_opWeijie Gao
Call spi_mem_default_supports_op() in supports_op to honor the slave's supported single/dual/quad mode settings. Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-01-23spi: mtk_spim: add support to use DT live treeWeijie Gao
Change devfdt_get_addr_ptr to dev_read_addr_ptr to support DT live tree. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-01-23clk: mediatek: fix uninitialized fields issue in INFRA_MUX structWeijie Gao
This patch adds missing initialization of fields in INFRA_MUX struct which caused uart broken after any other infra mux being enabled by 'clk_prepare_enable' Signed-off-by: Sam Shih <sam.shih@mediatek.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-01-22Merge patch series "upl: Prerequite patches for updated spec"Tom Rini
Simon Glass <sjg@chromium.org> says: The current UPL spec[1] has been tidied up and improved over the last year, since U-Boot's original UPL support was written. This series includes some prerequisite patches needed for the real UPL patches. It is split from [2] [1] https://github.com/UniversalPayload/spec/tree/3f1450d [2] https://patchwork.ozlabs.org/project/uboot/list/?series=438574&state=* Link: https://lore.kernel.org/r/20250111000029.245022-1-sjg@chromium.org
2025-01-22dm: core: Provide ofnode_find_subnode_unit()Simon Glass
The ofnode_find_subnode() function currently processes things two different ways, so the treatment of unit addresses differs depending on whether OF_LIVE is enabled or not. Add a new version which uses the ofnode API and add a test to check that unit addresses can be matched correctly. Leave the old function in place for the !OF_LIVE case, to avoid a code-size increase, e.g. on firefly-rk3288 Signed-off-by: Simon Glass <sjg@chromium.org>
2025-01-22dm: core: Provide ofnode_name_eq_unit() to accept a unit addressSimon Glass
When a unit-address is provided, use it to match against the node name. Since this increases code size, put it into a separate function. Signed-off-by: Simon Glass <sjg@chromium.org>
2025-01-22pci: video: Set up the pixel-format fieldSimon Glass
Add this information to the handoff structure so that it is available to U-Boot proper. Update bochs and the video handoff. Signed-off-by: Simon Glass <sjg@chromium.org>
2025-01-22emulation: Use bloblist to hold tablesSimon Glass
QEMU can have its own internal ACPI and SMBIOS tables. At present U-Boot copies out the SMBIOS tables but points directly to the ACPI ones. The ACPI tables are not aligned on a 4KB boundary, which means that UPL cannot use them directly, since it uses a reserved-memory node for the tables and that it assumed (by EDK2) to be 4KB-aligned. On x86, QEMU provides the tables in a mapped memory region and U-Boot makes use of these directly, thus making it difficult to use any common code. Adjust the logic to fit within the existing table-generation code. Use a bloblist always and ensure that the ACPI tables is placed in an aligned region. Set a size of 8K for QEMU. This does not actually put all the tables in one place, for QEMU, since it currently adds a pointer to the tables in QFW. On ARM, enable bloblist so that SMBIOS tables can be added to the bloblist. Signed-off-by: Simon Glass <sjg@chromium.org>
2025-01-22ofnode: Indicate when out of space in a few placesSimon Glass
Update ofnode_add_subnode() and ofnode_add_prop() to return a suitable error when space is exhausted in the FDT. This makes it easier to see what is going wrong. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2025-01-22ofnode: Use 4K for a default tree-sizeSimon Glass
At some point it would be nice to have the ofnode API automatically expand the tree as required, to accommodate new nodes. For now, expand the default size so that UPL can be supported. Signed-off-by: Simon Glass <sjg@chromium.org>
2025-01-22serial: Support info() method in ns16550 xPL with UPLSimon Glass
UPL needs to pass the serial details onto the next stage, so adjust the condition to support this. Signed-off-by: Simon Glass <sjg@chromium.org>
2025-01-22Merge https://source.denx.de/u-boot/custodians/u-boot-snapdragonTom Rini
The highlights are: * Fixed boot regression due to broken memory parsing * Enable HW RNG and KASLR on all platforms * Add support for Snapdragon X1 Elite hardware (clk/pinctrl) * Add support for QCS9100 ride automotive development platform (clk/ufs) * Add support for PCIe on SM8550, SM8650 and X1E * Implement software debounce for PMIC buttons Additionally, some minor improvements to "ufetch" have been pulled in: * Show CPU architecture (arm/mips/etc) * Make CONFIG_BLK optional * Fix 32-bit support
2025-01-22Merge patch series "spi: Collected fixes"Tom Rini
Alexander Dahl <ada@thorsis.com> says: Hello, two patches for header issues I came across when working on (Q)SPI drivers for atmel boards. Link: https://lore.kernel.org/r/20250115161621.1551826-1-ada@thorsis.com
2025-01-22spi: cadence-quadspi: fix potential malfunction after ~49 days uptimeRonald Wahl
The get_timer function returns an unsigned long which may be calculated from the ARM system counter. This counter is reset only on a cold reset. U-boot divides this counter down to a 1000 Hz counter that will cross the 32bit barrier after a bit more than 49 days. Assigning the value to an unsigned int will truncate it on 64bit systems. Passing this truncated value back to the get_timer function will return a very large value that is certainly larger than the timeout and so will go down the error path and besides stopping U-Boot will lead to messages like "SPI: QSPI is still busy after poll for 5000 ms." Signed-off-by: Ronald Wahl <ronald.wahl@legrand.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-01-22spi: atmel: Really drop atmel_spi.hAlexander Dahl
First try dropping this was with commit 37434db29be4 ("spi: atmel: Drop atmel_spi.h") back in 2018 which was reverted not much later with commit 5270df283676 ("Revert "spi: atmel: Drop atmel_spi.h""). Second try dropping this was in 2020 with commit beeb34ac0cc6 ("spi: atmel: Drop atmel_spi.h"), but that only moved all the definitions into the source file and did not remove the header file. Currently all of the definitions in the header file are (still) contained in the source file, and the header file is include nowhere. Fixes: beeb34ac0cc6 ("spi: atmel: Drop atmel_spi.h") Signed-off-by: Alexander Dahl <ada@thorsis.com>
2025-01-22phy: qcom: add QMP PCIe PHY driverNeil Armstrong
Add support for the PCIe QMP PHY on the SM8550, SM8650 and x1e80100 SoCs. The driver is based on the Linux phy/qualcomm/phy-qcom-qmp-pcie.c driver and adapted to U-Boot. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241125-topic-pcie-phy-v1-1-bf08811d0a07@linaro.org Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2025-01-22pci: Add support for Qualcomm PCIe controllerNeil Armstrong
Add support for the PCIe busses on Qualcomm platforms, by using the pcie_dw_common infrastructure. The driver is based on the Linux driver but only supporting the "1_9_0" and compatible platforms like: - sa8540p - sc7280 - sc8180x - sc8280xp - sdm845 - sdx55 - sm8150 - sm8250 - sm8350 - sm8450 - sm8550 - sm8650 - x1e80100 But it has only been tested on: - sc7280 - sm8550 - sm8650 - x1e80100 It supports setting the IOMMU SID table for supported platforms. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241125-topic-pcie-controller-v1-2-45c20070dd53@linaro.org Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2025-01-22pci: pcie_dw_common: introduce pcie_dw_find_capability()Neil Armstrong
Add PCIe config space capability search function specific for the host controller, which are bridges *to* PCI devices but are not PCI devices themselves. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241125-topic-pcie-controller-v1-1-45c20070dd53@linaro.org Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2025-01-22rng: msm: add support for newer Qualcomm hwrandom IPsNeil Armstrong
On recent Qualcomm SoCs, the hardware random generator is initialized and handled by the firmware because shared between different Execution Environments (EE), thus the initialization step should be skipped. Also support the newer "TRNG" found on SM8550 and newer SoCs that has inbuilt NIST SP800 90B compliant entropic source. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Alexey Minnekhanov <alexeymin@postmarketos.org> Link: https://lore.kernel.org/r/20241125-topic-sm8x50-rng-v1-1-52b72821c3e9@linaro.org Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-06 01:48:13 +0000