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2022-09-15pinctrl: pinctrl_stm32: Populate uc_priv->name[] with pinmux node's namePatrice Chotard
Populate uc_priv->name[] with pinmux node's name in order to indicate the pinmuxing's name in case GPIO is configured in alternate. For example, for STM32 SoC's based platform, "gpio status" command output : before Bank GPIOZ: GPIOZ0: unused : 0 [ ] GPIOZ1: unused : 0 [ ] GPIOZ2: unused : 0 [ ] GPIOZ3: unused : 0 [ ] GPIOZ4: func GPIOZ5: func GPIOZ6: unused : 0 [ ] GPIOZ7: unused : 0 [ ] GPIOZ8: unknown GPIOZ9: unknown GPIOZ10: unknown GPIOZ11: unknown GPIOZ12: unknown GPIOZ13: unknown GPIOZ14: unknown GPIOZ15: unknown After Bank GPIOZ: GPIOZ0: unused : 0 [ ] GPIOZ1: unused : 0 [ ] GPIOZ2: unused : 0 [ ] GPIOZ3: unused : 0 [ ] GPIOZ4: func i2c4-0 GPIOZ5: func i2c4-0 GPIOZ6: unused : 0 [ ] GPIOZ7: unused : 0 [ ] GPIOZ8: unknown GPIOZ9: unknown GPIOZ10: unknown GPIOZ11: unknown GPIOZ12: unknown GPIOZ13: unknown GPIOZ14: unknown GPIOZ15: unknown Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-09-15gpio: Fix pin's status display for pin with GPIOF_UNUSED functionPatrice Chotard
Even pin with GPIOF_UNUSED function can have a label. The criteria to add or not a space character is linked to label not to the used/unused status. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-09-15gpio: Allow to print pin's label even for pin with GPIOF_FUNC functionPatrice Chotard
Currently, if pin's function is GPIOF_FUNC, only "func" if displayed without any other information. It would be interesting, if information is available, to indicate which pinmuxing's name is used. For example, for STM32 SoC's based platform, "gpio status" command output : before Bank GPIOZ: GPIOZ0: unused : 0 [ ] GPIOZ1: unused : 0 [ ] GPIOZ2: unused : 0 [ ] GPIOZ3: unused : 0 [ ] GPIOZ4: func GPIOZ5: func GPIOZ6: unused : 0 [ ] GPIOZ7: unused : 0 [ ] GPIOZ8: unknown GPIOZ9: unknown GPIOZ10: unknown GPIOZ11: unknown GPIOZ12: unknown GPIOZ13: unknown GPIOZ14: unknown GPIOZ15: unknown After Bank GPIOZ: GPIOZ0: unused : 0 [ ] GPIOZ1: unused : 0 [ ] GPIOZ2: unused : 0 [ ] GPIOZ3: unused : 0 [ ] GPIOZ4: func i2c4-0 GPIOZ5: func i2c4-0 GPIOZ6: unused : 0 [ ] GPIOZ7: unused : 0 [ ] GPIOZ8: unknown GPIOZ9: unknown GPIOZ10: unknown GPIOZ11: unknown GPIOZ12: unknown GPIOZ13: unknown GPIOZ14: unknown GPIOZ15: unknown Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-09-15virtio: pci: fix bug of virtio_pci_map_capabilityXiang W
The bar of the structure virtio_pci_cap is the index, and each base address occupies 4 bytes, so it needs to be multiplied by 4. This patch fixes a bug reported by Felix Yan https://lists.denx.de/pipermail/u-boot/2022-August/492779.html Signed-off-by: Xiang W <wxjstz@126.com> Tested-by: Felix Yan <felixonmars@archlinux.org>
2022-09-15nvme: Fix multipage prp-listAlexander Sowarka
The nvme driver falsely assumed that the last entry on a page of the prp-list always points to the next page of the prp-list. This potentially can lead to the illegal creation of pages on the prp-list with only a single entry. This change now ensures that splitting the prp-list into multiple pages, behaves now as required by the NVME-Spec. Related to this, also the size of the memory allocation is adjusted accordingly. Signed-off-by: Alexander Sowarka <alexander.sowarka@aerq.com>
2022-09-14drivers: rng: optee_rng: register to CONFIG_OPTEE_SERVICE_DISCOVERYEtienne Carriere
Changes optee_rng driver to register itself has a OP-TEE service so that a device is bound for the driver when OP-TEE enumerates the PTA RNG service. Cc: Sughosh Ganu <sughosh.ganu@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-09-14drivers: tee: optee: discover OP-TEE servicesEtienne Carriere
This change defines resources for OP-TEE service drivers to register themselves for being bound to when OP-TEE firmware reports the related service is supported. OP-TEE services are discovered during optee driver probe sequence which mandates optee driver is always probe once bound. Discovery of optee services and binding to related U-Boot drivers is embedded upon configuration switch CONFIG_OPTEE_SERVICE_DISCOVERY. Cc: Jens Wiklander <jens.wiklander@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-09-14drivers: tee: optee: remove unused probe local variableEtienne Carriere
Removes local variable child in optee_probe() that is not used. Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-09-14misc: usb251xb: Support 8/16 bit device tree valuesStefan Herbrechtsmeier
The device tree binding [1] specify the vendor-id, product-id, device-id and language-id as 16 bit values and the linux driver reads the boost-up value as 8 bit value. [1] https://www.kernel.org/doc/Documentation/devicetree/bindings/usb/usb251xb.txt Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Reviewed-by: Marek Vasut <marex@denx.de>
2022-09-14dm: core: Add functions to read 8/16-bit integersStefan Herbrechtsmeier
Add functions to read 8/16-bit integers like the existing functions for 32/64-bit to simplify read of 8/16-bit integers from device tree properties. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-09-13mtd: spi-nor-ids: Add Winbond W25Q512JVQ IDChin-Ting Kuo
Add ID for Winbond W25Q512JVQ device which is supported on AST2600 EVB by default. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
2022-09-13spi: aspeed: Clock frequency adjustment supportChin-Ting Kuo
Driver can configure the SPI clock frequnecy to the target value of "spi-max-frequency" property in the device tree. The frequency is divided from HCLK, 200MHz. Usually, the ASPEED SPI clock frequency range is between 12.5MHz and 100MHz. On AST2600, the lowest SPI clock frequency can be about 780kHz. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
2022-09-13spi: aspeed: Support customized decoded address rangesChin-Ting Kuo
If "decoded-ranges" is defined in the device tree, the driver will apply the decoded address ranges from this property to the controller during probe stage. This patch refers to the following OpenBMC u-boot patch. https://patchwork.ozlabs.org/project/openbmc/list/?series=306969 Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
2022-09-13spi: aspeed: Adjust decoded range size supportChin-Ting Kuo
There are some known HW problems about decoded range register configurations on existing AST2500 and AST2600 platforms. Additional callback function, adjust_decoded_sz, is added to solve these problems on each platform. Besides, aspeed_spi_trim_decoded_size function is added to modify overall decoded address size for fitting the maximum AHB decoded size. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
2022-09-13spi: aspeed: SPI dirmap read supportChin-Ting Kuo
From the HW point of view, the performance of command read mode is greater than user mode slightly. Thus, dirmap read framework is introduced to achieve this goal. In dirmap_create, command read mode is configured. Usually, the decoded address area with flash size is assigned to each CS. CPU can thus access the SPI flash as normal memory in dirmap_read function. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
2022-09-13mtd: spi-nor: Use spi-mem dirmap APIChin-Ting Kuo
This adds support for the dirmap API to the spi-nor subsystem, as introduced in Linux commit df5c21002cf4 ("mtd: spi-nor: use spi-mem dirmap API"). This patch is synchronize from the following patch https://patchwork.ozlabs.org/project/uboot/patch/20210205043924.149504-4-seanga2@gmail.com/ The corresponding Linux kernel SHA1 is df5c21002cf4. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Signed-off-by: Sean Anderson <seanga2@gmail.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
2022-09-13spi-mem: Add dirmap API from LinuxChin-Ting Kuo
This adds the dirmap API originally introduced in Linux commit aa167f3fed0c ("spi: spi-mem: Add a new API to support direct mapping"). This also includes several follow-up patches and fixes. Changes from Linux include: * Added Kconfig option * Changed struct device to struct udevice * Changed struct spi_mem to struct spi_slave This patch is obtained from the following patch https://patchwork.ozlabs.org/project/uboot/patch/20210205043924.149504-3-seanga2@gmail.com/ The corresponding Linux kernel SHA1 is aa167f3fed0c. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Signed-off-by: Sean Anderson <seanga2@gmail.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
2022-09-13spi: aspeed: Support AST2400 platformChin-Ting Kuo
Although AST2400 is EOL officially, in order to achieve sustainability and completeness, AST2400 part is added. For AST2400, - Five CSs are supported by FMC controller. - SPI1 controller only supports single CS and there is no address segment address register. The CE control register of SPI1 is located at the offset 0x04 and the 4-byte address mode control bit is bit 13 of this register. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
2022-09-13spi: aspeed: Add ASPEED SPI controller driverChin-Ting Kuo
Add ASPEED BMC FMC/SPI memory controller driver with spi-mem interface for AST2500 and AST2600 platform. There are three SPI memory controllers embedded in an ASPEED SoC. - FMC: Named as Firmware Memory Controller. After AC on, MCU ROM fetches initial device boot image from FMC chip select(CS) 0. - SPI1: Play the role of a SPI Master controller. Or, there is a dedicated path for HOST(X86) to access its BIOS flash mounted under BMC. spi-aspeed-smc.c implements the control sequence when SPI1 is a SPI master. - SPI2: It is a pure SPI flash controller. For most scenarios, flashes mounted under it are for pure storage purpose. ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode. Three types of command mode are supported, normal mode, command read/write mode and user mode. - Normal mode: Default mode. After power on, normal read command 03h or 13h is used to fetch boot image from SPI flash. - AST2500: Only 03h command can be used after power on or reset. - AST2600: If FMC04[6:4] is set, 13h command is used, otherwise, 03h command. The address length is decided by FMC04[2:0]. - Command mode: SPI controller can send command and address automatically when CPU read/write the related remapped or decoded address area. The command used by this mode can be configured by FMC10/14/18[23:16]. Also, the address length is decided by FMC04[2:0]. This mode will be implemented in the following patch series. - User mode: It is a traditional and pure SPI operation, where SPI transmission is controlled by CPU. It is the main mode in this patch. Each SPI controller in ASPEED SoC has its own decoded address mapping. Within each SPI controller decoded address, driver can assign a specific address region for each CS of a SPI controller. The decoded address cannot overlap to each other. With normal mode and command mode, the decoded address accessed by the CPU determines which CS is active. When user mode is adopted, the CS decoded address is a FIFO, CPU can send/receive any SPI transmission by accessing the related decoded address for the target CS. This patch only implements user mode initially. Command read/write mode will be implemented in the following patches. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
2022-09-13pinctrl: aspeed: FWSPICS1 and SPI1CS1 pin supportChin-Ting Kuo
Add FWSPICS1 and SPI1CS1 in AST2500 pinctrl group. On AST2500 EVB, FWSPICS1 can be supported by default. An extra jumper, J45, should be configured before enabling SPI1CS1. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
2022-09-13clk: aspeed: Get HCLK frequency supportChin-Ting Kuo
User can get correct HCLK frequency during driver probe stage by adding the following configuration in the device tree. "clocks = <&scu ASPEED_CLK_AHB>". Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
2022-09-13spi: zynqmp_qspi: Code alignmentAshok Reddy Soma
Few lines are extented to next line though they can fit in 80 character limit, align them to single line. No functional change. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20220825125906.11581-6-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13spi: zynqmp_gqspi: Fix issue of reading more than 32bits lengthAshok Reddy Soma
As the flash sizes are increasing day by day, QSPI can have devices of size > 512MB. In qspi driver we are trying to read all the data at once using DMA. The DMA descriptor destination size is only 29bits long. QSPIDMA_DST_SIZE 0xFF0F0804 BITS: 1:0 Reserved to keep word alignment BITS: 28:2 Number of 4-byte words the DMA will transfer BITS: 31:29 Reserved: Returns 0 when read, writes ignored So we can only transfer data of 0x1FFFFFF0(512MB minus 4bytes) bytes. Anything above will overflow this register and will ignore higher bits above 29 bits. Change the DMA functionality if the requested size is greater than or equal to 512MB to read 256MB chunks. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20220825125906.11581-5-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13spi: zynqmp_gqspi: Add support for IO modeAshok Reddy Soma
Add support for io-mode transfers. This is necessary for UBIFS to work properly with spi-nor devices. The driver will work in IO mode when "has-io-mode" is passed from device tree instead of DMA. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20220825125906.11581-4-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13spi: zynqmp_gqspi: Add tap delays for VersalAshok Reddy Soma
Add tap delays for Versal platform and re-align the tapdelays code. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20220825125906.11581-2-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13spi: cadence-qspi: Use priv instead of plat across the driverAshok Reddy Soma
As per driver model we should enumerate plat structure only in of_to_plat() and should be used only in probe(). Copy required plat structure info into priv structure in probe() and use priv structure across the driver. So replace plat with priv structure across the driver. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220824113847.7482-4-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13spi: cadence_qspi: Call read_setup for STIG_READAshok Reddy Soma
In cadence_spi_read_id we are using STIG mode to read flash id's. Call cadence_qspi_apb_command_read_setup() to setup cmd, addr and data bus width properly before cadence_qspi_apb_command_read(). Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220824113847.7482-3-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13spi: cadence-qspi: Correct flash reset function nameAshok Reddy Soma
In cadence_spi_probe, cadence_qspi_versal_flash_reset() is called to reset the flash device. Looks like there is a mistake in previous series of patches where it is defined as cadence_spi_versal_flash_reset() but called as cadence_qspi_versal_flash_reset. Since there is a weak function defined with the same name this issue was not caught. Fix the issue by renaming cadence_spi_versal_flash_reset as cadence_qspi_versal_flash_reset(). Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220824113847.7482-2-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13cpu: microblaze: add error handling in microblaze_cpu_get_desc()Ovidiu Panait
Check snprintf() return value for errors. Make microblaze_cpu_get_desc() directly return snprintf() error code if ret < 0. Otherwise, if the return value is greater than or equal to size, the resulting string is truncated, so return -ENOSPC. Fixes: 816226d27e ("cpu: add CPU driver for microblaze") Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220829170205.1274484-2-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13net: gem: Check rate before setting it upMichal Simek
On QEMU setting rate for fixed clock is failing. That's why check a rate first if the rate is the same there is no need to ask for the change. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/bc465ffd4904bfd65208b782daa06732b915db54.1661502645.git.michal.simek@amd.com
2022-09-13firmware: zynqmp: Skip loading config object for VersalAshok Reddy Soma
SET_CONFIGURATION is not yet implemented for Versal platforms. Skip loading config object for Versal until support is added. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/eb7ef6c6de36a1f7d056de43042f96fe3639f18e.1659691195.git.michal.simek@amd.com
2022-09-12fpga: zynq: Remove post config info message for SPLStefan Herbrechtsmeier
The drivers informs the user that a post config was not run after FPGA configuration. This message is unnecessary in SPL because the ps7_post_config function is called via spl_board_prepare_for_boot function before jump_to_image_no_args function from board_init_r function. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220808145331.24723-1-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-12zynq: Convert arm twd timer to DM driverStefan Herbrechtsmeier
Move arm twd timer driver from zynq to generic location. DM timer drivers are designed differently to original driver. Timer is counting up and not down. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220805061629.1207-1-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-08-26firmware: ti_sci: Move ACK checking to ti_sci_do_xfer() functionAndrew Davis
We can check if the message was acknowledged in the common ti_sci_do_xfer() which lets us remove it from after each call to this function. This simplifies the code and reduces binary size. Signed-off-by: Andrew Davis <afd@ti.com>
2022-08-26firmware: ti_sci: Remove inline keyword from functionsAndrew Davis
The inline hint is not needed here, the compiler will do the right thing based on if we are compiling for speed or for code size. In this case the inline causes this function to be placed inside each callsite which is not the right thing to do for either speed nor size. There is no performance benefit to this due to the larger function size reducing cache locality, but there is a huge size penalty. Remove inline keyword. Signed-off-by: Andrew Davis <afd@ti.com>
2022-08-26firmware: ti_sci: Factor out message alloc failed messageAndrew Davis
We don't need to print the same message in every location, just print it in the function that fails and remove all the extra message printouts. Signed-off-by: Andrew Davis <afd@ti.com>
2022-08-26firmware: ti_sci: Reduce output on ti_sci_do_xfer errorAndrew Davis
This ti_sci_do_xfer() function already prints out the reason for the failure, and the caller of each of these functions should also notify the user of the failed task. Remove this extra level of error message. Signed-off-by: Andrew Davis <afd@ti.com>
2022-08-26arm: dts: qcom: Sync pinctrl DT nodes with Linux bindingsSumit Garg
Currently for all Qcom SoCs/boards there are separate compatibles for GPIO and pinctrl. But this is inconsistent with official (upstream) Linux bindings which requires only a single compatible "qcom,<SoC name>-pinctrl" and there is no such compatible property as "qcom,tlmm-<SoC name>". So fix this inconsistency for Qcom SoCs in order to comply with upstream DT bindings. This is done via removing compatibles from "msm_gpio" driver and via binding to "msm_gpio" driver from pinctrl driver in case "gpio-controller" property is specified for pinctrl node. Suggested-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2022-08-26gpio: qcom_pmic: Add support for GPIO LV/MV subtypeSumit Garg
GPIO LV (low voltage)/MV (medium voltage) subtypes have different features and register mappings than 4CH/8CH subtypes. Add support for LV and MV subtypes. With GPIO LV/MV subtype available, add "qcom,pms405-gpio" compatible which requires support for GPIO MV subtype. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2022-08-26pmic: Convert pm8916 driver to a generic Qcom PMIC driverSumit Garg
Since both pm8916.c and pm8916_gpio.c are already supporting multiple Qcom SoCs, it makes sense to rename these drivers to pmic_qcom.c and qcom_pmic_gpio.c respectively. Also, these driver can be extended to support additional functionality if required for other Qcom SoCs. Along with this import latest DT binding: qcom,spmi-pmic.txt from Linux kernel and thereby remove pm8916.txt. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2022-08-26reset: qcom: Add support for QCS404 SoC reset tableSumit Garg
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2022-08-26reset: Convert ipq4019 driver to a generic Qcom driverSumit Garg
Since the base functionality remains the same for a reset driver on Qcom SoCs, so leverage that to convert ipq4019 specific reset driver to a generic Qcom reset driver. With that one just need to provide SoC specific reset table. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2022-08-26phy: Add support for drivers to enable USB on QCS404 SoCSumit Garg
QCS404 SoC supports two types of PHY, one supports high speed mode or USB2 PHY and the other supports super speed mode or USB3 PHY. So add corresponding PHY drivers. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2022-08-26phy: Move qcom SoCs specific phy drivers to qcom folderSumit Garg
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2022-08-24Merge commit 'ac30d240dbb520d0980f0687630feb702a14f51a' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-nand-flash into next Re-sync again on some linux part, add some fixes for fsl_elbc from Pali and switch imx8mn bsh to use nand base ident For nand subsystem tested on: - imx8mn Macronix MX30LF4G18AC - P2020 based board Turris 1.1 for fsl_elbc
2022-08-23button: gpio: add DM_GPIO dependencyMichael Walle
The gpio-button driver depends on DM_GPIO, add it to Kconfig to avoid build errors. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Stefan Roese <sr@denx.de>
2022-08-23timer: add orion-timer supportMichael Walle
Add timer support for Kirkwood and MVEBU devices. Cc: Pali Rohár <pali@kernel.org> Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-08-22mtd: rawnand: fsl_elbc: Fix reading address pointer from DTPali Rohár
During compilation gcc throws warning: drivers/mtd/nand/raw/fsl_elbc_nand.c: In function ‘fsl_elbc_nand_probe’: drivers/mtd/nand/raw/fsl_elbc_nand.c:841:31: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] return fsl_elbc_chip_init(0, (void *)dev_read_addr(dev), dev); ^ Fix it by using dev_read_addr_ptr() function which returns pointer instead of dev_read_addr() which returns integer type. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-08-22mtd: rawnand: fsl_elbc: Remove NAND_NO_SUBPAGE_WRITE flagPali Rohár
Subpage write support for freescale eLBC NAND controller driver is implemented in U-Boot and was fixes in the commit d3963721d93f ("nand: Sync with Linux v4.1"). So remove NAND_NO_SUBPAGE_WRITE flag from the fsl_elbc_nand.c driver. This partially revert commit cb04c7723429 ("nand/fsl: add NAND_NO_SUBPAGE_WRITE to eLBC and IFC drivers"), only eLBC driver part. With this change U-Boot with default settings can read from NAND UBIFS image created on Linux with Linux default settings. Prior this change U-Boot was unable to read from NAND UBIFS images created with Linux default settings due to differnet UBI geometry. Linux kernel fsl_elbc_nand.c driver also does not set NAND_NO_SUBPAGE_WRITE flag and has implemented subpage write support. Fixes: cb04c7723429 ("nand/fsl: add NAND_NO_SUBPAGE_WRITE to eLBC and IFC drivers") Fixes: d3963721d93f ("nand: Sync with Linux v4.1") Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Acked-By: Michael Trimarchi<michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-08-22mtd: nand: samsung: Retrieve ECC requirements from extendedMichael Trimarchi
Upstream linux commit 8fc82d456e40a0. On some nand controllers with hw-ecc the controller code wants to know the ecc strength and size and having these as 0, 0 is not accepted. Specifying these in devicetree is possible but undesirable as the nand may be different in different production runs of the same board, so it is better to get this info from the nand id where possible. This commit adds code to read the ecc strength and size from the nand for Samsung extended-id nands. This code is based on the info for the 5th id byte in the datasheets for the following Samsung nands: K9GAG08U0E, K9GAG08U0F, K9GAG08X0D, K9GBG08U0A, K9GBG08U0B. These all use these bits in the exact same way. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-07 06:21:43 +0000