summaryrefslogtreecommitdiff
path: root/drivers
AgeCommit message (Collapse)Author
2021-08-21Fix flash and erase of eMMC Boot2 with FastbootOleh Kravchenko
The current U-Boot version has the next matches for boot partitions: > mmc0boot0 to EMMC_BOOT1 > mmc0boot1 to EMMC_BOOT1 (should be EMMC_BOOT2) This patch fixes a typo for the boot partition number. Signed-off-by: Oleh Kravchenko <oleg@kaa.org.ua> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Sean Anderson <sean.anderson@seco.com>
2021-08-21clk: clk_versaclock: Add support for versaclock driverAdam Ford
The driver is based on the Versaclock driver from the Linux code, but due differences in the clock API between them, some pieces had to be changed. This driver creates a mux, pfd, pll, and a series of fod ouputs. Rate Usecnt Name ------------------------------------------ 25000000 0 `-- x304-clock 25000000 0 `-- clock-controller@6a.mux 25000000 0 |-- clock-controller@6a.pfd 2800000000 0 | `-- clock-controller@6a.pll 33333333 0 | |-- clock-controller@6a.fod0 33333333 0 | | `-- clock-controller@6a.out1 33333333 0 | |-- clock-controller@6a.fod1 33333333 0 | | `-- clock-controller@6a.out2 50000000 0 | |-- clock-controller@6a.fod2 50000000 0 | | `-- clock-controller@6a.out3 125000000 0 | `-- clock-controller@6a.fod3 125000000 0 | `-- clock-controller@6a.out4 25000000 0 `-- clock-controller@6a.out0_sel_i2cb A translation function is added so the references to <&versaclock X> get routed to the corresponding clock-controller@6a.outX. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Sean Anderson <sean.anderson@seco.com>
2021-08-16clk: stm32mp1: add support of BSEC clockPatrick Delaunay
Add the support of the BSEC clock used by the STM32MP misc driver since the commit 622c956cada0 ("stm32mp: bsec: manage clock when present in device tree") even if this clock is not yet defined in kernel device tree stm32mp151.dtsi. This patch avoids issue for basic boot when this secure clock are not provided by secure world with SCMI. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-08-12Merge tag 'u-boot-rockchip-20210812' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-rockchip - Add Rockchip SFC driver support; - DTS sync from kernel; - emmc hs400 support for rk3399; - Fix for spinore bootdevice and MMC boot order;
2021-08-12rockchip: px30: Support configure SFCJon Lin
Make px30 SFC clock configurable Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-08-12mtd: spi-nor-ids: Add XTX XT25F128BChris Morgan
Adds support for XT25F128B used on Odroid Go Advance. Unfortunately this chip uses a continuation code which I cannot seem to parse, so there are possibly going to be collisions with chips that use the same manufacturer/ID. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-08-12spi: rockchip_sfc: add support for Rockchip SFCChris Morgan
This patch adds support for the Rockchip serial flash controller found on the PX30 SoC. It should work for versions 3-5 of the SFC IP, however I am only able to test it on v3. This is adapted from the WIP SPI-MEM driver for the SFC on mainline Linux. Note that the main difference between this and earlier versions of the driver is that this one does not support DMA. In testing the performance difference (performing a dual mode read on a 128Mb chip) is negligible. DMA, if used, must also be disabled in SPL mode when using A-TF anyway. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-08-11Merge https://source.denx.de/u-boot/custodians/u-boot-cfi-flashTom Rini
- Some CFI flash related fixups (Kconfig & header) (Bin) - Enable CFI flash support on the QEMU RISC-V virt machine. (Bin)
2021-08-11mmc: rockchip_sdhci: Add support for RK3568Yifeng Zhao
This patch adds support for the RK3568 platform to this driver. Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-08-11mmc: rockchip_sdhci: add phy and clock config for rk3399Yifeng Zhao
Add clock, phy and other configuration, it is convenient to support new controller. Here a short summary of the changes: - Add mmc_of_parse to parse dts config. - Remove OF_PLATDATA related code. - Reorder header inclusion. - Add phy ops. - add ops set_ios_post to modify the parameters of phy when the clock changes. - Add execute tuning api for hs200 tuning. Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-08-11mtd: kconfig: Fix CFI_FLASH dependencyBin Meng
The DM version CFI flash driver is in driver/mtd/cfi_flash.c, which only gets built when FLASH_CFI_DRIVER is on. If CFI_FLASH is on but FLASH_CFI_DRIVER is not, nothing is enabled at all. Fix this dependency by selecting FLASH_CFI_DRIVER when CFI_FLASH is enabled. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2021-08-11arm: a37xx: pci: Fix handling PIO config error responsesPali Rohár
Returning fabricated CRS value (0xFFFF0001) by PCIe Root Complex to OS is allowed only for 4-byte PCI_VENDOR_ID config read request and only when CRSSVE bit in Root Port PCIe device is enabled. In all other error PCIe Root Complex must return all-ones. So implement this logic in pci-aardvark.c driver properly. aardvark HW does not have Root Port PCIe device and U-Boot does not implement emulation of this device. So expect that CRSSVE bit is set as U-Boot can already handle CRS value for PCI_VENDOR_ID config read request. More callers of pci_bus_read_config() function in U-Boot do not check for return value, but check readback value. Therefore always fill readback value in pcie_advk_read_config() function. On error fill all-ones of correct size as it is required for PCIe Root Complex. And also correctly propagates error from failed config write request to return value of pcie_advk_write_config() function. Most U-Boot callers ignores this return value, but it is a good idea to return correct value from function. These issues about return value of failed config read requests, including special handling of CRS were reported by Lorenzo and Bjorn for Linux kernel driver pci-aardvark together with quotes from PCIe r4.0 spec, see details: https://lore.kernel.org/linux-pci/20210624213345.3617-1-pali@kernel.org/t/#u Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-08-11arm: mvebu: sata_mv failed to identify HDDs during cold startTony Dinh
During cold start, with some HDDs, mv_sata_identify() does not populate the ID words on the 1st ATA ID command. In fact, the first ATA ID command will only power up the drive, and then the ATA ID command processing is lost in the process. Tests with: - Seagate ST9250320AS 250GB HDD and Seagate ST4000DM004-2CV104 4TB HDD. - Zyxel NSA310S (Kirkwood 88F6702), Marvell Dreamplug (Kirkwood 88F6281), Seagate GoFlex Home (Kirkwood 88F6281), Pogoplug V4 (Kirkwood 88F6192). Observation: - The Seagate ST9250320AS 250GB took about 3 seconds to spin up. - The Seagate ST4000DM004-2CV104 4TB took about 8 seconds to spin up. - mv_sata_identify() did not populate the ID words after the call to mv_ata_exec_ata_cmd_nondma(). - Attempt to insert a long delay of 30 seconds, ie. mdelay(30_000), after the call to ata_wait_register() inside mv_ata_exec_ata_cmd_nondma() did not help with the 4TB drive. The ID words were still empty after that 30s delay. Patch Description: - Added a second ATA ID command in mv_sata_identify(), which will be executed if the 1st ATA ID command did not return with valid ID words. - Use the HDD drive capacity in the ID words as a successful indicator of ATA ID command. - In the scenario where a box is rebooted, the 1st ATA ID command is always successful, so there is no extra time wasted. - In the scenario where a box is cold started, the 1st ATA command is the power up command. The 2nd ATA ID command alleviates the uncertainty of how long we have to wait for the ID words to be populated by the SATA controller. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Tony Dinh <mibodhi@gmail.com>
2021-08-09Merge tag 'u-boot-imx-20210809' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20210809 - new SOC: add support for imx8ulp - Toradex fixes for colibri (vf / imx6 / imx7 / imx8x) - convert to DM for mx28evk - Fixes for Gateworks ventana boards CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/8639
2021-08-09ddr: Add DDR driver for iMX8ULPYe Li
Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
2021-08-09imx8ulp: move struct mu_type to common headerPeng Fan
Move struct mu_type to common header to make it reusable by upower and S400 Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09driver: misc: imx8ulp: Add fuse driver for imx8ulpYe Li
This driver uses FSB to read some fuses, but not support program fuse. It only works in SPL (secure mode), u-boot needs traps to ATF to read them. Some fuses can read from S400 API and others are from FSB. Also support program some fuses via S400 API Signed-off-by: Ye Li <ye.li@nxp.com>
2021-08-09arm: imx8ulp: release and configure XRDC at early phaseYe Li
Since S400 will set the memory of SPL image to R/X. We can't write to any data in SPL image. 1. Set the parameters save/restore only for u-boot, not for SPL. to avoid write data. 2. Not use MU DM driver but directly call MU API to send release XRDC to S400 at early phase. 3. Configure the SPL image memory of SRAM2 to writable (R/W/X) Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09drivers: misc: s400_api: Update API for fuse read and writeYe Li
Add API to support fuse read and write Signed-off-by: Ye Li <ye.li@nxp.com>
2021-08-09drivers: misc: imx8ulp: Update S400 API for release RDCYe Li
The RDC API is updated to add a field for XRDC or TRDC Signed-off-by: Ye Li <ye.li@nxp.com>
2021-08-09drivers: misc: imx8ulp: Add S400 API for image authenticationYe Li
Add S400 API for image authentication Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09drivers: misc: s400_api: Update S400_SUCCESS_IND to 0xd6Ye Li
According to latest S400 API doc, the the success indicate value is changed to 0xd6. So update the driver codes. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09drivers: mmc: fsl_esdhc_imx: support i.MX8ULPPeng Fan
i.MX8ULP reuse same SDHC IP as i.MX8M, so follow i.MX8M code logic. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09pinctrl: Add pinctrl driver for imx8ulpYe Li
Add pinctrl driver for i.MX8ULP Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09net: fec_mxc: support i.MX8ULPPeng Fan
Support i.MX8ULP in fec_mxc Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-08-09driver: misc: Add MU and S400 API to communicate with SentinelYe Li
Add MU driver and S400 API. Need enable MISC driver to work Signed-off-by: Ye Li <ye.li@nxp.com>
2021-08-08dm: core: Don't allow uclass use before readySimon Glass
At present it is possible to call uclass_get() before driver model is inited. In fact this happens on x86 boards which use Intel FSPv1, since mrccache_get_region() tries to get the SPI flash device very early during init. This has always been undefined behaviour. Previously it generally worked, i.e. returned an error code without crashing, because gd->uclass_root_s is zeroed and the uclass can be added despite driver model not being ready, due to the way lists are implemented. With the change to use a gd->uclass_root pointer, this no-longer works. For example, it causes a hang on minnowmax. Fix this by adding a check that driver model is ready when uclass_get() is called. This function is called in the process of locating any device, so it is a good place to add the check. This fixes booting on minnowmax. Signed-off-by: Simon Glass <sjg@chromium.org> Fixes: 8a715530bb1 ("dm: core: Allow the uclass list to move")
2021-08-08dm: migrate the dm_warn to use the log macroPatrick Delaunay
Migrate the dm_warn function to log macro with LOGC_DM category and LOGL_WARNING level. This macro allows filtering with log command and allows output on all log backend. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-06Merge tag 'video-2021-08-05' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-video - add display driver for ST-Ericsson MCDE - drop legacy CONFIG_VIDEO dependency for Hitachi tx18d42vm
2021-08-06pci: ppc: Drop ftpci100 driverSimon Glass
This is not used in U-Boot at present. Drop it and related config options. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-06pci: sata_sil: Drop DM_PCI checksSimon Glass
We don't need these checks anymore since when PCI is enabled, driver model is always used. Drop them. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-05pci: Drop DM_PCI check from bios_emulSimon Glass
We don't need these checks anymore since when PCI is enabled, driver model is always used. Drop them. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-05pci: scsi: pci: Drop DM_PCI check from scsiSimon Glass
We don't need this check anymore since when PCI is enabled, driver model is always used. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-05pci: imx: Drop use of DM_PCISimon Glass
Now that DM_PCI is always enabled we don't need to check it. Drop this old code. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-05pci: msc01: Drop use of DM_PCISimon Glass
Now that DM_PCI is always enabled we don't need to check it. Drop this old code. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-05pci: gt64120: Drop use of DM_PCISimon Glass
Now that DM_PCI is always enabled we don't need to check it. Drop this old code. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-05pci: usb: ohci: Test on PCI not DM_PCISimon Glass
Now that DM_PCI is always enabled, check on CONFIG_PCI instead. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Update for non-PCI users of this code, reword] Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-05pci: dm: core: Drop DM_PCI check from devfdt_get_addr_pci()Simon Glass
We don't need this check anymore since when PCI is enabled, driver model is always used. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-05pci: Drop DM_PCI check from pci_commonSimon Glass
We don't need this check anymore since when PCI is enabled, driver model is always used. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-03Merge https://source.denx.de/u-boot/custodians/u-boot-spiTom Rini
- SPI-NOR fix (Big Meng) - XMC XM25QH64C flash (Reto Schneider)
2021-08-03mtd: spi-nor: Mask out fast read if not requested in DTBin Meng
The DT bindings of "jedec,spi-nor" [1] defines "m25p,fast-read" property to indicate that "fast read" opcode can be used to read data from the chip instead of the usual "read" opcode. If this property is not present in DT, mask out fast read in spi_nor_init_params(). This change mirrors the same logic in spi_nor_info_init_params() in drivers/mtd/spi-nor/core.c in the Linux kernel v5.14-rc3. [1] Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml in the kernel tree Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-08-03mtd: spi-nor: Respect flash's hwcaps in spi_nor_adjust_hwcaps()Bin Meng
The smart spi_nor_adjust_hwcaps() does not respect the SPI flash's hwcaps, and only looks to the controller on what can be supported. The flash's hwcaps needs to be AND'ed before checking. Fixes: 71025f013ccb ("mtd: spi-nor-core: Rework hwcaps selection") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-08-03spi: spi-mem-nodm: Fix read data size issueBin Meng
When slave drivers don't set the max_read_size, the spi-mem should directly use data.nbytes and not limit to any size. But current logic will limit to the max_write_size. This commit mirrors the same changes in the dm version done in commit 535b1fdb8e5e ("spi: spi-mem: Fix read data size issue"). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-08-03mtd: spi-nor-ids: Add support for XMC XM25QH64CReto Schneider
This chip has been (briefly) tested on the MediaTek MT7688 based GARDENA smart gateway. Datasheet: http://xmcwh.com/Uploads/2020-12-17/XM25QH64C_Ver1.1.pdf Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-08-02Merge https://source.denx.de/u-boot/custodians/u-boot-x86Tom Rini
- Fixed broken ICH SPI driver in software sequencer mode - Added "m25p,fast-read" to SPI flash node for x86 boards - Drop ROM_NEEDS_BLOBS and BUILD_ROM for x86 ROM builds - Define a default TSC timer frequency for all x86 boards - x86 MTRR MSR programming codes bug fixes - x86 "hob" command bug fixes - Don't program MTRR for DRAM for FSP1 - Move INIT_PHASE_END_FIRMWARE to FSP2 - Use external graphics card by default on Intel Crown Bay - tangier: Fix DMA controller IRQ polarity in CSRT
2021-08-02global: Convert simple_strtoul() with decimal to dectoul()Simon Glass
It is a pain to have to specify the value 10 in each call. Add a new dectoul() function and update the code to use it. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-02global: Convert simple_strtoul() with hex to hextoul()Simon Glass
It is a pain to have to specify the value 16 in each call. Add a new hextoul() function and update the code to use it. Add a proper comment to simple_strtoul() while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-02Merge tag 'efi-2021-10-rc2' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-efi Pull request for efi-2021-10-rc2 Documentation: * handle 'make htmldocs' warnings as errors * add missing board/ti/index.rst Bug fixes: * avoid buffer overrun in TrueType console * lib: disable CONFIG_SPL_HEXDUMP by default
2021-08-02Merge tag 'mmc-2021-7-30' of https://source.denx.de/u-boot/custodians/u-boot-mmcTom Rini
pl180_mmci update and cleanup fix rpmb routing memory alignment
2021-08-02x86: tsc: Rename X86_TSC_TIMER_EARLY_FREQ to X86_TSC_TIMER_FREQBin Meng
Currently there are two places to specify the x86 TSC timer frequency with one in Kconfig used for early timer and the other one in device tree used when the frequency cannot be determined from hardware. This may potentially create an inconsistent config where the 2 values do not match. Let's use the one specified in Kconfig in the device tree as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-06 07:07:48 +0000