summaryrefslogtreecommitdiff
path: root/drivers
AgeCommit message (Collapse)Author
2023-07-14ufs: Use 'TASK_TAG' to construct the ucd_req_ptr->header.dword_0Bhupesh Sharma
Instead of using the hard-coded value of 0x1f, use 'TASK_TAG' macro instead to construct the ucd_req_ptr->header.dword_0 This is in sync with what the Linux UFS driver does, i.e. set the byte0 equal to TASK_TAG (see [1]). Setting it to a fixed value of 0x1f is wrong as we define TASK_TAG as 0 inside u-boot ufs framework. So, instead we should use the macro value directly. [1]. https://github.com/torvalds/linux/blob/master/drivers/ufs/core/ufshcd.c#L2705 Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
2023-07-14drivers: led: bcm6753: do not use null label to find the topPhilippe Reynes
This driver considers that a node with an empty label is the top. But the led class has changed, if a label is not provided for a led, the label is filed with the node name. So we update this driver to use a wrapper to manage the top led node. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2023-07-14net: ti: am65-cpsw-nuss: Use dedicated port mode control registersAndreas Dannenberg
The different CPSW sub-system Ethernet ports have different PHY mode control registers. In order to allow the modes to get configured independently only the register for the port in question must be accessed, otherwise we would just be re-configuring the mode for port 1, while leaving all others at their power-on defaults. Fix this issue by adding a port-number based offset to the mode control base register address based on the fact that the control registers for the different ports are spaced exactly 0x4 bytes apart. Fixes: 9d0dca1199d1 ("net: ethernet: ti: Introduce am654 gigabit eth switch subsystem driver") Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2023-07-14firmware: scmi: return a right errno for SCMI status codeAKASHI Takahiro
scmi_to_linux_errno() is set to return an appropriate errno which corresponds to a given SCMI status code. But the current implementation always returns the same value. Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
2023-07-14clk: scmi: claim the dependency on CONFIG_CLKAKASHI Takahiro
Without CONFIG_CLK, the build fails with the following message: LD u-boot aarch64-none-linux-gnu-ld.bfd: drivers/firmware/scmi/scmi_agent-uclass.o: \ in function `scmi_bind_protocols': .../drivers/firmware/scmi/scmi_agent-uclass.c:79: undefined reference to \ `_u_boot_list_2_driver_2_scmi_clock' Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2023-07-14misc: npcm_host_intf: change initialization sequenceJim Liu
configuration should be done before release host wait Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2023-07-14pinctrl: nuvoton: fix reset reason error for poweronJim Liu
In non tip mode, BMC first power on with PORST+CORST. the gpio status will error. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2023-07-14misc: nuvoton: fix type errorJim Liu
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2023-07-14video: Update stb_truetypeSimon Glass
This was brought in in 2016 and a number of changes have been made since then. There does not seem to be much change in functionality, but it is a good idea to update from time to time. Bring in the latest version: 5736b15 ("re-add perlin noise again") Add a few necessary functions, with dummies in some cases. Update the tests as there are subtle changes in rendering, perhaps not for the better. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-07-14video: Use enum with video_index_to_colour()Simon Glass
Use the provided enum with this function, so it is clearer what should be passed to it. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-07-14console: Allow measuring the bounding box of textSimon Glass
For laying out text accurately it is necessary to know the width and height of the text. Add a measure() method to the console API, so this can be supported. Add an implementation for truetype and a base implementation for the normal console. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-07-14video: Allow temporary colour changesSimon Glass
It is sometimes necessary to highlight some text in a different colour. Add an easy way to do this and then restore the original console colours. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-07-14fdt: Allow more general use of livetreeSimon Glass
At present livetree can only be used for the control FDT. It is useful to be able to use the ofnode API for other FDTs, e.g. those used by the upcoming configuration editor. We already have most of the support present, and tests can be marked with the UT_TESTF_OTHER_FDT flag to use another FDT as a special case. But with this change, the functionality becomes more generally available. Plumb in the require support. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-07-14fdt: Clarify the fdt pre-relocation warningSimon Glass
Reword this so it is easier to understand. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-07-14console: Correct truetype spacing errorSimon Glass
The putc_xy() method is supposed to return the amount of space used. The existing implementation erroneously adds the previous sub-pixel position to the returned value. This spaces out the characters very slightly more than it should. It is seldom noticeable but it does make accurate measurement of the text impossible. Fix this minor but long-standing bug. Fixes: a29b012037c ("video: Add a console driver that uses TrueType fonts") Signed-off-by: Simon Glass <sjg@chromium.org>
2023-07-14video: Provide a way to clear part of the consoleSimon Glass
This is useful when the background colour must be written before text is updated, to avoid strange display artifacts. Add a function for this, using the existing code from the truetype console. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-07-14video: Drop #ifdefs from console_truetypeSimon Glass
Use if() instead to reduce the number of build paths. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-07-14dm: core: Avoid registering an inaccessible treeSimon Glass
At present there are various restrictions on the use of livetree: - It is only available once the tree is unflattened, i.e. after relocation - It is designed to be used with the control FDT - It can (in principle) be used with other FDTs, but only if they are unflattened first; this is not supported Add a few checks to make sure that any tree that is created is actually valid. Otherwise it can be confusing when nodes and properties cannot actually be accessed. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-07-14gpio: Avoid using an invalid ofnodeSimon Glass
Devices do not necessarily have nodes attached to them, since they can be created from platdata. In SPL a devicetree may in fact not exist at all. Check the node before using it. This avoids failure when OF_CHECKS is enabled. Signed-off-by: Simon Glass <sjg@chromium.org> Fixes: 5fc7cf8c8e2 ("gpio: add gpio-hog support") Reviewed-by: Heiko Schocher <hs@denx.de>
2023-07-13Merge https://gitlab.denx.de/u-boot/custodians/u-boot-spiTom Rini
- Add xtxtech spi-nor chip parts (Bruce Suen) - Add bcm63xx-hsspi driver fixes (William Zhang)
2023-07-13Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini
- mvebu: Thecus: Misc enhancement and cleanup (Tony) - mvebu: Add AC5X Allied Telesis x240 board support incl NAND controller enhancements for this SoC (Chris)
2023-07-13Merge tag 'u-boot-imx-20230713' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20230713 ------------------- Merge for 2023.10. CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/16888
2023-07-13clk: imx8mp: Update clocks based on kernel 6.4-RC4Adam Ford
There are some newer clocks added to the kernel recently, so to fix prepare for resycing the device trees, update the clock list. Since there are some minor changes to the USB clocks, update which USB clocks are enabled to match with the upstream kernel as well. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@denx.de> Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice-gw74xx
2023-07-13dm: adc: add iMX93 ADC supportLuca Ellero
This commit adds driver for iMX93 ADC. The driver is implemented using driver model and provides ADC uclass's methods for ADC single channel operations: - adc_start_channel() - adc_channel_data() - adc_stop() ADC features: - channels: 4 - resolution: 12-bit Signed-off-by: Luca Ellero <l.ellero@asem.it> Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
2023-07-13imx: imx8ulp: start the ELE RNG at bootPeng Fan
On the imx8ulp A1 SoC, the ELE RNG needs to be manually started. Signed-off-by: Clement Faure <clement.faure@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: misc: ele_mu: Update ELE MU driverYe Li
Extend the RX timeout value to 10s, because when authentication is failed the ELE needs long time (>2s for 28M image) to return the result. Print rx wait info per 1s. Also correct TX and RX status registers in debug. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: misc: ele_mu: Update MU TR registers countYe Li
According to SRM, the Sentinel MU has 8 TR and 4 RR registers. All of them are used for ELE message. So update TR count to 8 and fix a typo in receive msg Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: ele_api: add DEK Blob generationPeng Fan
- Add crc computation. - Add ele_generate_dek_blob API for encrypted boot support. Signed-off-by: Clement Faure <clement.faure@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: ele_api: support program secure fuse and return lifecyclePeng Fan
Add two ELE API: ele_return_lifecycle_update and ele_write_secure_fuse Add two cmd: ahab_return_lifecycle and ahab_sec_fuse_prog Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: use generic name ele(EdgeLockSecure Enclave)Peng Fan
Per NXP requirement, we rename all the NXP EdgeLock Secure Enclave code including comment, folder and API name to ELE to align. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: scu_api: update to version 1.16 and add more APIsPeng Fan
Upgrade SCFW API to 1.16 Add more APIs: sc_misc_get_button_status sc_pm_reboot sc_seco_v2x_build_info Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: mach: correct SCU API usagePeng Fan
The return value is int type, not sc_err_t(u8), correct the usage. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13mtd: spi-nor: Add support for w25q256jwmVenkatesh Yadav Abbarapu
Add support for Winbond 256M-bit flash w25q256jwm. Performed basic erase/write/readback operations on ZynqMP zc1751+dc1 board. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-07-13spi: npcm_pspi: use ACTIVE_LOW flag for cs gpio and set default max_hzJim Liu
If cs gpio is requested with ACTIVE_HIGH flag, it will be pulled low(i.e. active). This is not what we expected. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-07-13mtd: spi-nor-ids: add xtxtech part#Bruce Suen
add following XTX part numbers to the list: xt25f08: 3V QSPI, 8Mbit xt25f16: 3V QSPI, 16Mbit xt25f32: 3V QSPI, 32Mbit xt25f64: 3V QSPI, 64Mbit xt25f128: 3V QSPI, 128Mbit xt25f256: 3V QSPI, 256Mbit xt25q08: 1.8V QSPI, 8Mbit xt25q16: 1.8V QSPI, 16Mbit xt25q32: 1.8V QSPI, 32Mbit xt25q64: 1.8V QSPI, 64Mbit xt25q128: 1.8V QSPI, 128Mbit xt25q256: 1.8V QSPI, 256Mbit xt25q512: 1.8V QSPI, 512Mbit xt25q01g: 1.8V QSPI, 1Gbit xt25w512: wide voltage, QSPI, 512Mbit xt25w01g: wide voltage, QSPI, 1Gbit remove xt25f128b and add xt25f128,because xt25f128b andxt25f128f share same jdec id,we use xt25f128 instead. Signed-off-by: Bruce Suen <bruce_suen@163.com> [jagan: re-edited the entire patch] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2023-07-13mtd: spi-nor-ids: change full company name of XTXBruce Suen
XTX changed full company name from "XTX Technology (Shenzhen) Limited to "XTX Technology Limited" since 2020,So remove "(Shenzhen)". Signed-off-by: Bruce Suen <bruce_suen@163.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-07-13spi: soft_spi: Support the recommended soft spi propertiesFabio Estevam
According to Documentation/devicetree/bindings/spi/spi-gpio.yaml from Linux, the recommended spio-gpio properties are: sck-gpios, miso-gpios and mosi-gpios. gpio-sck, gpio-mosi and gpio-miso are considered deprecated. Currently, U-Boot only supports the deprecated properties. Allow the soft_spi driver to support both the new and old properties. Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-07-13spi: synquacer: remove SPI_TX_BYTE handlingMasahisa Kojima
Current code expects that SPI_TX_BYTE is single bit mode but it is wrong. It indicates byte program mode, not single bit mode. If SPI_TX_DUAL, SPI_TX_QUAD and SPI_TX_OCTAL bits are not set, the default transfer bus width is single bit. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-07-13spi: bcmbca-hsspi: Add driver for newer HSSPI controllerWilliam Zhang
The newer BCMBCA SoCs such as BCM6756, BCM4912 and BCM6855 include an updated SPI controller that add the capability to allow the driver to control chip select explicitly. Driver can control and keep cs low between the transfers natively. Hence the dummy cs workaround or prepend mode found in the bcm63xx-hsspi driver are no longer needed and this new driver is much cleaner. Port from linux patch: Link: https://lore.kernel.org/r/20230209200246.141520-15-william.zhang@broadcom.com Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-07-13spi: bcm63xx-hsspi: Add prepend mode supportWilliam Zhang
Due to the controller limitation to keep the chip select low during the bus idle time between the transfer, a dummy cs workaround was used when this driver was first upstreamed to the u-boot based on linux kernel driver. It basically picks the dummy cs as !actual_cs so typically dummy cs is 1 when most of the case only cs 0 is used in the board design. Then invert the polarity of both cs and tell the controller to start the transfers using dummy cs. Assuming both cs are active low before the inversion, effectively this keeps dummy cs high and actual cs low during the transfer and workaround the issue. This workaround requires that dummy cs 1 pin to is set to SPI chip selection function in the pinmux when the transfer clock is above 25MHz. The old chips likely have default pinmux set to chip select on the dummy cs pin so it works but this is not case for the new Broadband BCA chips and this workaround stop working. This is specifically an issue to support SPI NAND and SPI NOR flash because these flash devices can typically run at or above 100MHz. This patch utilizes the prepend feature of the controller to combine the multiple transfers in the same message to a single transfer when possible. This way there is no need to keep clock low between transfers and solve the issue without any pinmux requirement. Multiple transfers within a SPI message may be combined into one transfer if the following are all true: * One or more half duplex write transfer in single bit mode * Optional full duplex read/write at the end * No delay and cs_change between transfers Most of the SPI device meets this requirements such as SPI NOR, SPI NAND flash, Broadcom SPI voice card and etc. So this change switches to the prepend mode as the default mode. For any SPI message that does not meet the above requirement, we switch to original dummy cs mode but limit the clock rate to the safe 25MHz. Port from linux patch: Link: https://lore.kernel.org/r/20230209200246.141520-12-william.zhang@broadcom.com Signed-off-by: William Zhang <william.zhang@broadcom.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2023-07-13spi: bcm63xx-hsspi: Add new compatible string supportWilliam Zhang
New compatible string brcm,bcmbca-hsspi-v1.0 is introduced based on dts document brcm,bcm63xx-hsspi.yaml. Add it to the driver to support this new binding. Port from linux patch: Link: https://lore.kernel.org/r/20230207065826.285013-6-william.zhang@broadcom.com Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-07-13spi: bcm63xx-hsspi: Fix multi-bit mode settingWilliam Zhang
Currently the driver always sets the controller to dual data bit mode for both tx and rx data in the profile mode control register even for single data bit transfer. Luckily the opcode is set correctly according to SPI transfer data bit width so it does not actually cause issues. This change fixes the problem by setting tx and rx data bit mode field correctly according to the actual SPI transfer tx and rx data bit width. Fixes: 29cc4368ad4b ("dm: spi: add BCM63xx HSSPI driver") Port from linux patch: Link: https://lore.kernel.org/r/20230209200246.141520-11-william.zhang@broadcom.com Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-07-13spi: bcm63xx-hsspi: Make driver depend on BCMBCA archWilliam Zhang
ARCH_BCMBCA was introduced to cover individual Broadcom broadband SoC for common features and IP blocks. Use this config instead of each chip config as the Kconfig dependency for Broadcom HSSPI driver. Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-07-13spi: pl022: Add chip-select gpio supportLukas Funke
Add support for an optional external chip-select gpio. Signed-off-by: Lukas Funke <lukas.funke@weidmueller.com> Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-07-13spi: pl022: Remove platform data headerStefan Herbrechtsmeier
Remove the platform data header because its content is only used by the driver. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-07-13spi: pl022: Rename flush into pl022_spi_flushStefan Herbrechtsmeier
Rename the flush function into pl022_spi_flush to avoid conflicting types with previous declaration of the function in stdio.h header. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-07-13spi: pl022: Align compatible property with device tree bindingLukas Funke
Align the compatible property with the kernel device tree binding [1] by removing the '-spi' suffix. [1] https://www.kernel.org/doc/Documentation/devicetree/bindings/spi/spi-pl022.yaml Signed-off-by: Lukas Funke <lukas.funke@weidmueller.com> Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-07-13mtd: nand: pxa3xx: Enable devbus/nand arbiter on Armada 8KChris Packham
The CN9130 SoC (an ARMADA 8K type) has both a NAND Flash Controller and a generic local bus controller (Device Bus Controller) that share common pins. With a board design that incorporates both a NAND flash and uses the Device Bus (in our case for an SRAM) accessing the Device Bus device fails unless the NfArbiterEn bit is set. Setting the bit enables arbitration between the Device Bus and the NAND flash. Since there is no obvious downside in enabling this for designs that don't require arbitration, we always enable it. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2023-07-13mtd: nand: pxa3xx: Add support for the Marvell AC5 SoCChris Packham
The NAND flash controller (NFC) on the AC5/AC5X SoC is the same as the NFC used on other Marvell SoCs. It does have the additional restriction of only supporting SDR timing modes up to 3. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2023-07-12riscv: Rename SiFive CLINT to RISC-V ALINTBin Meng
As the RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V ALINT in the source tree to be future-proof. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-06 15:47:18 +0000