summaryrefslogtreecommitdiff
path: root/drivers
AgeCommit message (Collapse)Author
2022-05-24clk: sunxi: add PIO bus gate clocksAndre Przywara
The introduction of the DM pinctrl driver made its probe function enable all clocks enumerated in the DT. This includes the "CLK_BUS_PIO" (and variations) gate clock. Also CLK_PLL_PERIPH0 is used by the R_CCU device. So far we didn't describe those clocks in our clock driver. As we enable them already in the SPL, the devices happen to work, but the clock driver still complains about not finding those clocks: ========= sunxi_set_gate: (CLK#58) unhandled ========= Add the one-liners that are needed to announce the gate bit for those clocks, to silence that message on the console. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org>
2022-05-24clk: sunxi: h6_r: Correct the driver nameSamuel Holland
H6 is from the sun50i family, not sun6i. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-24mmc: sunxi: Remove unnecessary pinmux option dependencySamuel Holland
Now that the pinmux conflict is handled in the board code (by skipping setup for the one conflicting MMC controller), the driver does not need to be entirely disabled based on the UART pinmux. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-23clk: sunxi: implement clock driver for suniv f1c100sGeorge Hilliard
The f1c100s has a clock tree similar to those of other sunxi parts. Add support for it. Signed-off-by: George Hilliard <thirtythreeforty@gmail.com> Signed-off-by: Yifan Gu <me@yifangu.com> Acked-by: Sean Anderson <seanga2@gmail.com> [Andre: add PIO and I2C] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-20Merge https://source.denx.de/u-boot/custodians/u-boot-usbTom Rini
2022-05-20usb: dwc3: Fix non-usb3 configurationsJan Kiszka
Missing nodes may also be signaled via -ENODATA. We need to check for that to prevent failing in non-usb3 setups. Furthermore, dev.phy must be NULL'ed in case usb3-phy was not found. Fixes: 142d50fbce7c ("usb: dwc3: Add support for usb3-phy PHY configuration") Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2022-05-20usb: xhci-dwc3: Support role switch default roleMark Kettenis
When the device tree indicates support for role switching through the "usb-role-switch" property, take the "role-switch-default-mode" property into account when deciding which role to put the controller into. This makes USB devices work on Apple M1 systems where the device tree may include a "dr_mode" property that is set to "otg", but where we need to put the controller into "host" mode to see devices connected to the type-C ports. Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2022-05-19spi: stm32_qspi: Remove SR_BUSY bit check before sending commandPatrice Chotard
Waiting for SR_BUSY bit when receiving a new command is not needed. SR_BUSY bit is already managed in the previous command treatment. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-05-19spi: stm32_qspi: Always check SR_TCF flags in stm32_qspi_wait_cmd()Patrice Chotard
Currently, SR_TCF flag is checked in case there is data, this criteria is not correct. SR_TCF flags is set when programmed number of bytes have been transferred to the memory device ("bytes" comprised command and data send to the SPI device). So even if there is no data, we must check SR_TCF flag. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-05-17pinctrl: probe pinctrl drivers during post-bindRobert Marko
Currently, pinctrl drivers only get probed if pinconf is actually being used, however on SoC-s like Armada 3720 pinctrl driver is a also the GPIO driver. So, if the pinctrl driver doesn't get probed GPIO-s won't get registered and thus they cannot be used. This is a problem on the Methode eDPU as it just uses SB pins as GPIO-s and without them being registered networking won't work as it only has one SFP slot and the TX disable GPIO is on the SB controller. So, probe the pinctrl drivers using DM_FLAG_PROBE_AFTER_BIND like LED uclass does. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-05-17serial: ns16550: Add support for SPL_DEBUG_UART_BASEPali Rohár
Use CONFIG_VAL(DEBUG_UART_BASE) instead of CONFIG_DEBUG_UART_BASE, so proper config value (CONFIG_DEBUG_UART_BASE or CONFIG_SPL_DEBUG_UART_BASE) is used based on building target. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-05-17serial: Add new config option TPL_DEBUG_UART_BASEPali Rohár
TPL_DEBUG_UART_BASE is same as DEBUG_UART_BASE, but applies only for TPL. Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Stefan Roese <sr@denx.de>
2022-05-16serial: Add new config option SPL_DEBUG_UART_BASEPali Rohár
SPL_DEBUG_UART_BASE is same as DEBUG_UART_BASE, but applies only for SPL. In some cases base address of UART is different in SPL and proper U-Boot. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-05-11Convert CONFIG_MTD_CONCAT to KconfigChris Packham
This converts the following to Kconfig: CONFIG_MTD_CONCAT Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefan Roese <sr@denx.de>
2022-05-10Merge tag 'u-boot-stm32-20220510' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-stm Add new STM32 MCU boards and Documentation STM32 programmer improvements video: support several LTDC HW versions and fix data enable polarity board: fix stboard error message, consider USB cable connected when boot device is USB configs: stm32mp1: set console variable for extlinux.conf configs: stm32mp1: add support for baudrate higher than 115200 for ST-Link ARM: stm32mp: Fix Silicon version handling and ft_system_setup() phy: stm32-usbphyc: Add DT phy tuning support arm: dts: stm32mp15: alignment with v5.18 ram: Conditionally enable ASR mach-stm32mp: psci: retain MCUDIVR, PLL3CR, PLL4CR, MSSCKSELR across suspend configs: Use TFTP_TSIZE on DHSOM and STMicroelectronics boards ARM: stm32: Use default CONFIG_TFTP_BLOCKSIZE on DHSOM pinctrl: stm32: rework GPIO holes management
2022-05-10Merge tag 'i2c-2022-07' of https://source.denx.de/u-boot/custodians/u-boot-i2cTom Rini
i2c changes for 2022.07 - i2c: ihs: intel: Fix typo in comments Patch from Michal - misc: atsha204a: Add support for atsha204 chip from Pali
2022-05-10misc: Fix always compiling MISC even for SPL/TPLSean Anderson
We should only build support for misc if the appropriate SPL/TPL symbol is defined. To ease the transition, make SPL/TPL_MISC default to MISC. This is necessary because many drivers don't specify their dependencies properly. These defaults can be removed once all drivers depend on the appropriate config. Fixes: aaba703fd0 ("spl: misc: Allow misc drivers in SPL and TPL") Signed-off-by: Sean Anderson <sean.anderson@seco.com> [trini: Add VPL_MISC symbol, handle like SPL/TPL_MISC] Signed-off-by: Tom Rini <trini@konsulko.com>
2022-05-10clk: stm32mp1: Add missing newlineMarek Vasut
Add missing newline to this debug message, no functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10phy: stm32-usbphyc: stm32-usbphyc: Add DT phy tuning supportPatrice Chotard
Add support of phy-tuning properties for sm32-usbphyc's phy tuning aligned with v5.15 kernel bindings. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-05-10gpio: stm32_gpio: Rework GPIO hole managementPatrice Chotard
On some STM32 SoC's package, GPIO bank may have hole in their GPIO bank Example: If GPIO bank have 16 GPIO pins [0-15]. In particular SoC's package case, some GPIO bank can have less GPIO pins: - [0-10] => 11 pins; - [2-7] => 6 pins. Commit dbf928dd2634 ("gpio: stm32f7: Add gpio bank holes management") proposed a first implementation by not counting GPIO "inside" hole. GPIO are not displaying correctly using gpio or pinmux command when GPIO holes are located at the beginning of GPIO bank. To simplify, consider that all GPIO have 16 GPIO and use the gpio_ranges struct to indicate if a GPIO is mapped or not. GPIO uclass offers several GPIO functions ("input", "output", "unused", "unknown" and "func"), use "unknown" GPIO function to indicate that a GPIO is not mapped. stm32_offset_to_index() is no more needed and removed. This must be reflected using the "gpio" command to indicate to user that a particular GPIO is not mapped (marked as "unknown") as shown below: Example for a 16 pins GPIO bank with the [2-7] mapping (only 6 pins mapped): GPIOI0 : unknown GPIOI1 : unknown GPIOI2 : analog GPIOI3 : analog GPIOI4 : alt function 0 push-pull pull-down GPIOI5 : alt function 0 push-pull pull-down GPIOI6 : alt function 0 push-pull pull-down GPIOI7 : analog GPIOI8 : unknown GPIOI9 : unknown GPIOI10 : unknown GPIOI11 : unknown GPIOI12 : unknown GPIOI13 : unknown GPIOI14 : unknown GPIOI15 : unknown Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-05-10pinctrl: pinctrl_stm32: Use GPIOF_UNKNOWN to indicate not mapped pinsPatrice Chotard
GPIOF_UNKNOWN becomes a valid pin muxing information to indicate that a pin is not mapped. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-05-10pinctrl: pinctrl_stm32: Update pinmux_mode definitionPatrice Chotard
pinmux_mode[] is linked to gpio_function[] defined in gpio-uclass.c So reuse the same gpio_func_t enum value Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-05-10ram: stm32mp1: Conditionally enable ASRMarek Vasut
Enable DRAM ASR, auto self-refresh, conditionally, based on DT PWRCTL register bits. While ASR does save considerable amount of power at runtime automatically, it also causes LTDC underruns on large panels. Let user select whether or not ASR is required or not, generally ASR should be enabled on portable and battery operated devices. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10video: stm32: stm32_ltdc: support several hardware versionsYannick Fertre
Register mapping & pixel formats depend on version of ltdc display controller. Signed-off-by: Yannick Fertre <yannick.fertre@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10video: stm32: stm32_ltdc: fix data enable polarityYannick FERTRE
Wrong DISPLAY_FLAGS used to set the data enable polarity. Signed-off-by: Yannick FERTRE <yannick.fertre@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10misc: atsha204a: Add support for atsha204 chipPali Rohár
atsha204 chip is predecessor of atsha204a chip. Current U-Boot driver atsha204a-i2c.c can use both atsha204 and atsha204a chips because it does not call specific functions to just one of these chips. So just add compatible string for atsha204. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2022-05-10i2c: ihs: intel: Fix typo in comments (actual)Michal Simek
s/actucal/actual/g Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2022-05-09regulator: add driver for the TPS65219 BUCK & LDO regulatorsNeil Armstrong
The TPS65219 I2S PMIC features 3 Buck converters and 4 linear regulators, 2 GPOs, 1 GPIO, and 3 multi-function-pin. This adds the driver for the Buck converters & linear regulators. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2022-05-09power: add driver for the TPS65219 PMICNeil Armstrong
The TPS65219 I2S PMIC features 3 Buck converters and 4 linear regulators, 2 GPOs, 1 GPIO, and 3 multi-function-pin. This adds the PMIC driver, loading the regulator sub-nodes. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2022-05-06Merge https://source.denx.de/u-boot/custodians/u-boot-usbTom Rini
2022-05-06usb: host: ehci-generic: Remove DM_REGULATOR flagPatrice Chotard
Since commit 16cc5ad0b439 ("power: regulator: add dummy helper") regulator dummy helper are always available even if DM_REGULATOR is not set. DM_REGULATOR flag is no more needed to protect no DM core, remove it. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-06usb: host: ehci-generic: Make usage of clock/reset bulk() APIPatrice Chotard
Make usage of clock and reset bulk API in order to simplify the code Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-06watchdog: Add MAX6370 watchdog timer driverPali Rohár
MAX6370 watchdog is available e.g. on Freescale P1/P2 RDB-PC boards. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-05-05misc: fs_loader: Fix compile warnings when CONFIG_CMD_UBIFS is enabledPali Rohár
drivers/misc/fs_loader.c: In function ‘mount_ubifs’: drivers/misc/fs_loader.c:46:12: warning: implicit declaration of function ‘ubi_part’ [-Wimplicit-function-declaration] int ret = ubi_part(mtdpart, NULL); ^~~~~~~~ drivers/misc/fs_loader.c:53:9: warning: implicit declaration of function ‘cmd_ubifs_mount’ [-Wimplicit-function-declaration] return cmd_ubifs_mount(ubivol); ^~~~~~~~~~~~~~~ drivers/misc/fs_loader.c: In function ‘umount_ubifs’: drivers/misc/fs_loader.c:58:9: warning: implicit declaration of function ‘cmd_ubifs_umount’ [-Wimplicit-function-declaration] return cmd_ubifs_umount(); ^~~~~~~~~~~~~~~~ Signed-off-by: Pali Rohár <pali@kernel.org>
2022-05-05reset: Return 0 if ops unimplemented and remove empty functionsMarek Vasut
In case the ops is not implemented, return 0 in the core right away. This is better than having multiple copies of functions which just return 0 in each reset driver. Drop all those empty functions. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
2022-05-05clk: scmi: fix scmi_clk_get_attibute()Heinrich Schuchardt
Local variable out.name lives on the stack and therefore cannot be returned directly. Move the strdup() call into the function. (Coverity 352460) Fixes: 7c33f78983c3 ("clk: scmi: register scmi clocks with CCF") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2022-05-05rtc: rv8803: fix off-by-one in month countingOliver Graute
tm_mon has a range from 0..11, but the RTC expects 1..12. So we adapt the month accordingly. This was determined when comparing the driver with the corresponding linux kernel driver. Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com> Reviewed-by: Michael Walle <michael@walle.cc> Reviewed-by: Heiko Schocher <hs@denx.de>
2022-05-05serial: smh: Check return value of strndupSean Anderson
strndup can fail. Check for it. Fixes: 4855b39be ("serial: smh: Implement puts for DM") Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-05-05gpio: npcm: Add support for Nuvoton NPCM SoCsStanley Chu
Add Nuvoton BMC NPCM7xx/NPCM8xx gpio driver Signed-off-by: Stanley Chu <yschu@nuvoton.com>
2022-05-05pinctrl: mediatek: add support for different types of IO pinsSam Shih
There are many pins in an SoC, and register usage may vary by pins. This patch introduces a concept of "io type" and "io type group" to mediatek pinctrl drivers. This can provide different pinconf handlers implementation (eg: "bias-pull-up/down", "driving" and "input-enable") for IO pins that belong to different types. Signed-off-by: Sam Shih <sam.shih@mediatek.com>
2022-05-05pinctrl: mediatek: introduce multiple memory bases supportSam Shih
Pinctrl design of some mediatek SoC need to access registers that distribute in multiple memory base address. this patch introduce new mechanism in mediatek pinctrl driver to support the chips which have the new design. This patch add a member 'base_calc' in pinctrl private data, and changed original 'base' private data to an array of *iomem. When 'base_calc' attribute is set, it will requests multiplue regs base from the DT, if 'base_calc' attribute is not set, it only use legacy way to request single reg resource from the DT. Signed-off-by: Sam Shih <sam.shih@mediatek.com>
2022-05-05pinctrl: mediatek: rewrite mtk_pinconf_set and related functionsSam Shih
There are many pins in a SoCs, and different pin may belong to different "io_type", For example: some pins of MT7622 belongs to "io_type A", the other belongs to "io_type B", and pinctrl "V0" means handle pinconf via "io_type A" or "io_type B", so SoCs that contain "io_type A" and "io_type B" pins, use "V0" in pinctrl driver. This patch separates the implementation of register operations (e.g: "bias-pull-up/down", "driving" and "input-enable") into different functions, and lets the original V0/V1 ops to call the new functions. Signed-off-by: Sam Shih <sam.shih@mediatek.com>
2022-05-05timer: npcm: Add NPCM timer supportJim Liu
Add Nuvoton BMC NPCM7xx/NPCM8xx timer driver. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Signed-off-by: Stanley Chu <yschu@nuvoton.com>
2022-05-05serial: npcm: Add support for Nuvoton NPCM SoCsJim Liu
Add Nuvoton BMC NPCM7xx/NPCM8xx uart driver Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Signed-off-by: Stanley Chu <yschu@nuvoton.com>
2022-05-05clk: nuvoton: Add support for NPCM750Jim Liu
Add clock controller driver for NPCM750 Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Signed-off-by: Stanley Chu <yschu@nuvoton.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2022-05-04Merge tag 'efi-2022-07-rc2-2' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-efi Pull request for efi-2022-07-rc2-2 * Test Unit test for 'bootmenu' command * UEFI Preparatory patches for implementing a UEFI boot options based menu
2022-05-04Merge https://source.denx.de/u-boot/custodians/u-boot-marvellTom Rini
- mips: octeon: Add ethernet support (Aaron & Stefan) - Misc mvneta changes, cleanups, fixes (Marek)
2022-05-04Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-spiTom Rini
- NPCM7xx FIU SPI driver (Jim Liu) - AT45DB641E dataflash (Luca Ellero)
2022-05-04net: mvneta: Drop unneeded macroMarek Behún
Macro MVNETA_GMAC_FORCE_LINK_UP can be dropped from value assignment in fixed link case, since it's value is written into the register later in the function for link-down-to-link-up case. The value is written as MVNETA_GMAC_FORCE_LINK_DOWN | MVNETA_GMAC_FORCE_LINK_PASS, and so the macro definition can also be dropped. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2022-05-04net: mvneta: Disable fixed PHY code if PHY_FIXED is not compiled inMarek Behún
Guard the code handling the fixed PHY case by CONFIG_IS_ENABLED(PHY_FIXED). Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-06 21:30:06 +0000