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2023-07-27Merge https://source.denx.de/u-boot/custodians/u-boot-usbTom Rini
2023-07-27usb: xhci: Fix double free on failureRichard Habeeb
drivers/core/device.c will call `device_free()` after xhci_register already frees the private device data. This can cause a crash later during the boot process, observed on aarch64 RPi4b as a synchronous exception. All callers of xhci_register use priv_auto, so this won't lead to memory leaks. Signed-off-by: Richard Habeeb <richard.habeeb@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-07-25drivers: watchdog: add mcf watchdog supportAngelo Dureghello
This watchdog driver applies to the following mcf families: - mcf52x2 (5271 5275 5282) - mcf532x (5329 5373) - mcf523x (5235) Cpu's not listed for each family does not have WDT module. Note, after some attempts testing by qemu on 5208 i finally abandoned, watchdog seems not implemented properly. The driver has been tested in a real M5282EVM. Signed-off-by: Angelo Dureghello <angelo@kernel-space.org> --- Changes for v2: - remove unnecessary hardcoded timeouts - remove unnecessary hw_watchdog_xxx stuff - rewrite wdog module reg calculation - using IS_ENABLED() where possible Changes for v3: - remove hardcoded 4s test
2023-07-25drivers: rtc: max313xx: provide read8/write8Chris Packham
In some designs the MAX313xx RTC may need calibration to cope with oscillator inaccuracies. Provide read8/write8 ops so that the registers can be accessed. Because the driver covers a range of MAX313xx variants no attempt is made to ensure the register is valid. Signed-off-by: Chris Packham <judge.packham@gmail.com>
2023-07-25lib: sparse: allocate FASTBOOT_MAX_BLK_WRITE instead of small numberMattijs Korpershoek
Commit 62649165cb02 ("lib: sparse: Make CHUNK_TYPE_RAW buffer aligned") fixed cache alignment for systems with a D-CACHE. However it introduced some performance regressions [1] on system flashing huge images, such as Android. On AM62x SK EVM, we also observe such performance penalty: Sending sparse 'super' 1/2 (768793 KB) OKAY [ 23.954s] Writing 'super' OKAY [ 75.926s] Sending sparse 'super' 2/2 (629819 KB) OKAY [ 19.641s] Writing 'super' OKAY [ 62.849s] Finished. Total time: 182.474s The reason for this is that we use an arbitrary small buffer (info->blksz * 100) for transferring. Fix it by using a bigger buffer (info->blksz * FASTBOOT_MAX_BLK_WRITE) as suggested in the original's patch review [2]. With this patch, performance impact is mitigated: Sending sparse 'super' 1/2 (768793 KB) OKAY [ 23.912s] Writing 'super' OKAY [ 15.780s] Sending sparse 'super' 2/2 (629819 KB) OKAY [ 19.581s] Writing 'super' OKAY [ 17.192s] Finished. Total time: 76.569s [1] https://lore.kernel.org/r/20221118121323.4009193-1-gary.bisson@boundarydevices.com [2] https://lore.kernel.org/r/all/43e4c17c-4483-ec8e-f843-9b4c5569bd18@seco.com/ Fixes: 62649165cb02 ("lib: sparse: Make CHUNK_TYPE_RAW buffer aligned") Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2023-07-25drivers: led: bcm6858: do not use null label to find the topPhilippe Reynes
This driver considers that a node with an empty label is the top. But the led class has changed, if a label is not provided for a led, the label is filed with the node name. So we update this driver to use a wrapper to manage the top led node. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2023-07-25mailbox: k3-sec-proxy: Fill non-message tx data fields with 0x0Nishanth Menon
Sec proxy data buffer is 60 bytes with the last of the registers indicating transmission completion. This however poses a bit of a challenge. The backing memory for sec_proxy is regular memory, and all sec proxy does is to trigger a burst of all 60 bytes of data over to the target thread backing ring accelerator. It doesn't do a memory scrub when it moves data out in the burst. When we transmit multiple messages, remnants of previous message is also transmitted which results in some random data being set in TISCI fields of messages that have been expanded forward. The entire concept of backward compatibility hinges on the fact that the unused message fields remain 0x0 allowing for 0x0 value to be specially considered when backward compatibility of message extension is done. So, instead of just writing the completion register, we continue to fill the message buffer up with 0x0 (note: for partial message involving completion, we already do this). This allows us to scale and introduce ABI changes back also work with other boot stages that may have left data in the internal memory. While at this, drop the unused accessor function. Fixes: f9aa41023bd9 ("mailbox: Introduce K3 Secure Proxy Driver") Signed-off-by: Nishanth Menon <nm@ti.com>
2023-07-24Revert "Merge branch '2023-07-24-introduce-FF-A-suppport'"Tom Rini
This reverts commit d927d1a80843e1c3e2a3f0b8f6150790bef83da1, reversing changes made to c07ad9520c6190070513016fdb495d4703a4a853. These changes do not pass CI currently. Signed-off-by: Tom Rini <trini@konsulko.com>
2023-07-24arm_ffa: introduce sandbox FF-A supportAbdellatif El Khlifi
Emulate Secure World's FF-A ABIs and allow testing U-Boot FF-A support Features of the sandbox FF-A support: - Introduce an FF-A emulator - Introduce an FF-A device driver for FF-A comms with emulated Secure World - Provides test methods allowing to read the status of the inspected ABIs The sandbox FF-A emulator supports only 64-bit direct messaging. Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org> Cc: Jens Wiklander <jens.wiklander@linaro.org> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
2023-07-24arm_ffa: introduce armffa commandAbdellatif El Khlifi
Provide armffa command showcasing the use of the U-Boot FF-A support armffa is a command showcasing how to invoke FF-A operations. This provides a guidance to the client developers on how to call the FF-A bus interfaces. The command also allows to gather secure partitions information and ping these partitions. The command is also helpful in testing the communication with secure partitions. For more details please refer to the command documentation [1]. [1]: doc/usage/cmd/armffa.rst Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org> Cc: Jens Wiklander <jens.wiklander@linaro.org> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
2023-07-24arm_ffa: introduce Arm FF-A supportAbdellatif El Khlifi
Add Arm FF-A support implementing Arm Firmware Framework for Armv8-A v1.0 The Firmware Framework for Arm A-profile processors (FF-A v1.0) [1] describes interfaces (ABIs) that standardize communication between the Secure World and Normal World leveraging TrustZone technology. This driver uses 64-bit registers as per SMCCCv1.2 spec and comes on top of the SMCCC layer. The driver provides the FF-A ABIs needed for querying the FF-A framework from the secure world. The driver uses SMC32 calling convention which means using the first 32-bit data of the Xn registers. All supported ABIs come with their 32-bit version except FFA_RXTX_MAP which has 64-bit version supported. Both 32-bit and 64-bit direct messaging are supported which allows both 32-bit and 64-bit clients to use the FF-A bus. FF-A is a discoverable bus and similar to architecture features. FF-A bus is discovered using ARM_SMCCC_FEATURES mechanism performed by the PSCI driver. Clients are able to probe then use the FF-A bus by calling the DM class searching APIs (e.g: uclass_first_device). The Secure World is considered as one entity to communicate with using the FF-A bus. FF-A communication is handled by one device and one instance (the bus). This FF-A driver takes care of all the interactions between Normal world and Secure World. The driver exports its operations to be used by upper layers. Exported operations: - ffa_partition_info_get - ffa_sync_send_receive - ffa_rxtx_unmap Generic FF-A methods are implemented in the Uclass (arm-ffa-uclass.c). Arm specific methods are implemented in the Arm driver (arm-ffa.c). For more details please refer to the driver documentation [2]. [1]: https://developer.arm.com/documentation/den0077/latest/ [2]: doc/arch/arm64.ffa.rst Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org> Cc: Jens Wiklander <jens.wiklander@linaro.org> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
2023-07-24Merge tag 'u-boot-at91-fixes-2023.10-a' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-at91 First set of u-boot-atmel fixes for the 2023.07 cycle: This small fixes set includes the LTO configs for the boards that had the SPL size up to the limit (sama5d2-based), such that more code can be added. It also includes a fix for mmc non-removable.
2023-07-24atmel_sdhci: Force card-detect if MMC_CAP_NONREMOVABLE.Zixun LI
If the device attached to the MMC bus is not removable, set force card-detect bit to bypass card detection procedure, so card detection pin can be used for other purposes. It's also a workaround for SAMA5D2 who doesn't drive CMD if using GPIO for card detection. Signed-off-by: Zixun LI <zli@ogga.fr> Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-07-24clk: starfive: jh7110: Add of_xlate ops and macros for clock id conversionXingyu Wu
Modify the drivers to add of_xlate ops and transform clock id. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Torsten Duwe <duwe@suse.de> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-07-24clk: starfive: jh7110: Separate the PLL driverXingyu Wu
Drop the PLL part in SYSCRG driver and separate to be a single PLL driver of which the compatible is "starfive,jh7110-pll". Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Torsten Duwe <duwe@suse.de> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-07-21drivers: video: Kconfig: Add config remove videoNikhil M Jain
This is required since user may want to either call the remove method of video driver and reset the display or not call the remove method to continue displaying until next stage. Signed-off-by: Nikhil M Jain <n-jain1@ti.com> Reviewed-by: Devarsh Thakkar <devarsht@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-07-21common: board_f: Pass frame buffer info from SPL to u-bootNikhil M Jain
U-boot proper can use frame buffer address passed from SPL to reserve the memory area used by framebuffer set in SPL so that splash image set in SPL continues to get displayed while u-boot proper is running. Put the framebuffer address and size in a bloblist to make them available at u-boot proper, if in u-boot proper CONFIG_VIDEO is defined. Signed-off-by: Nikhil M Jain <n-jain1@ti.com> Reviewed-by: Devarsh Thakkar <devarsht@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-07-21include: video: Reserve video using blobNikhil M Jain
Add method to reserve video framebuffer information using blob, received from previous stage. Signed-off-by: Nikhil M Jain <n-jain1@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-07-21ram: k3-ddrss: do not touch ctrl regs during trainingBryan Brattlof
During LPDDR initialization we will loop through a series of frequency changes in order to train at the various operating frequencies. During this training, accessing the DRAM_CLASS bitfield could happen during a frequency change and cause the read to hang. Store the DRAM type into the main structure to avoid multiple readings while the independent phy is training. Signed-off-by: Bryan Brattlof <bb@ti.com>
2023-07-21Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini
For once this adds USB support for two SoCs: the H616 and the F1C100s series. The rest is support for LPDDR3 DRAM chips on H616 boards. Gitlab CI passed, and I booted that briefly on an H616 and an F1C200s board. I don't have an H616 board with LPDDR3 DRAM, but reportedly that works for Mikhail, and doesn't regress on my DDR3 boards.
2023-07-21Merge tag 'xilinx-for-v2023.10-rc1-v2' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2023.10-rc1 v2 axi_emac: - Change return value if RX packet is not ready cadence_qspi: - Enable flash reset for Versal NET dt: - Various DT syncups with Linux kernel - SOM - reserved pmufw memory location fpga: - Add load event mtd: - Add missing dependency for FLASH_CFI_MTD spi/nand: - Minor cleanup in Xilinx drivers versal-net: - Prioritize boot device in boot_targets - Wire mini ospi/qspi/emmc configurations watchdog: - Use new versal-wwdt property xilinx: - fix sparse warnings in various places ps7_init* - add missing headers - consolidate code around zynqmp_mmio_read/write - switch to amd.com email zynqmp_clk: - Add handling for gem rx/tsu clocks zynq_gem: - Configure mdio clock at run time zynq: - Enable fdt overlay support zynq_sdhci: - Call dll reset only for ZynqMP SOCs
2023-07-21event: Add fpga load eventChristian Taedcke
This enables implementing custom logic after a bitstream was loaded into the fpga. Signed-off-by: Christian Taedcke <christian.taedcke@weidmueller.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Link: https://lore.kernel.org/r/20230720072724.11516-1-christian.taedcke-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-07-21clk: zynqmp: Add gem rx and tsu clocks to return registerAshok Reddy Soma
Add gem_tsu and gem0_rx till gem3_rx to return proper register from zynqmp_clk_get_register. Otherwise firmware won't be able to set clock for these due to incorrect register address. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230720072859.3724-1-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-07-21clk: zynqmp: Add set_rate support for gem rx and tsu clksAshok Reddy Soma
gem0_rx till gem3_rx and gem_tsu are missing from set rate function. Add them, so that they can be set from pmu firmware via clock framework. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230719084912.30209-1-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-07-21net: axi_emac: Change return value to -EAGAIN if RX is not readyMaksim Kiselev
If there is no incoming package than axiemac_recv will return -1 which in turn leads to printing `eth_rx: recv() returned error -1` error message in eth_rx function. But missing a package is not an fatal error, so return -EAGAIN in that case would be more suitable. Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com> Link: https://lore.kernel.org/r/20230719065337.69280-1-bigunclemax@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-07-21mtd: Add missing MTD dependency for cfi_mtdMichal Simek
cfi_mtd requires add_mtd_device() which is available only when MTD is enabled that's why record this dependency. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/76ae01ce2b2c988758b69e0f0cdcc21bf301c01e.1688472227.git.michal.simek@amd.com
2023-07-21mmc: zynq_sdhci: Dll reset only for ZynqMP platformAshok Reddy Soma
Dll reset is needed only for ZynqMP platforms, add condition in tuning to call arasan_zynqmp_dll_reset() just for ZynqMP platforms. On other platforms like Versal NET, If this condition is not added, we see PLM error messages when dll reset smc is called. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/d673ff3bdc5c236a7f0403c920e719684abd6059.1688991117.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Switch to amd.com emailsMichal Simek
Update my and DPs email address to match current setup. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com
2023-07-21xilinx: Consolidate zynqmp_mmio_read/write in zynqmp_firmware.hMichal Simek
zynqmp_mmio_read/write() are firmware provided hooks that's why use only zynqmp_firmware.h for function declaration. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/e7489556f9e447c737a578c169d7e1e43586a273.1687524706.git.michal.simek@amd.com
2023-07-21cadence_qspi: Enable flash reset for Versal NET platformAshok Reddy Soma
Enable flash reset functionality for Versal NET platform. In cadence_qspi.c there is weak function defined for reset, hence remove the check for config, so that it will work for Versal and Versal NET platforms. Add register defines in Versal NET hardware.h for mini U-Boot flash reset. Add read_delay initialization for Versal NET also. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230614120452.21019-1-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-07-21net: zynq_gem: Don't hardcode the MDC clock divisorVenkatesh Yadav Abbarapu
As per spec MDC must not exceed 2.5MHz, read the pclk clock from the device tree and update the MDC clock divisor. GEM devices support larger clock divisors and have a different range of divisors. Program the MDIO clock divisors based on the clock rate of the pclk clock. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Link: https://lore.kernel.org/r/20230619034922.24019-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-07-21mtd: nand: zynq_nand: Change datatype of status and ecc_status to intAlgapally Santosh Sagar
status and ecc_status are of unsigned type where they are compared for negative value. This is pointed by below sparse warning. Change datatype to int to fix this. warning: comparison of unsigned expression in '< 0' is always false [-Wtype-limits] Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230614090359.10809-5-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-07-21spi: zynq_qspi: Add missing prototype for zynq_qspi_mem_exec_opAlgapally Santosh Sagar
Add missing prototype to fix the sparse warning, warning: no previous prototype for 'zynq_qspi_mem_exec_op' [-Wmissing-prototypes]. Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230614090359.10809-4-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-07-21spi: xilinx_spi: Add missing prototype for xilinx_qspi_mem_exec_opAlgapally Santosh Sagar
Add missing prototype to fix the below sparse warning warning: no previous prototype for 'xilinx_qspi_mem_exec_op' [-Wmissing-prototypes] Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230614090359.10809-2-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-07-21watchdog: versal: Use new compatible xlnx,versal-wwdtMichal Simek
DT binding has been approved that's why use new compatible string. The old one is mark as deprecated and should be removed after some releases. Link: https://lore.kernel.org/r/20230420104231.2243079-3-srinivas.neeli@amd.com/ Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/6e78d0d2e21f2f9e7f8f448bb8e0d27ced4de7d3.1686655339.git.michal.simek@amd.com
2023-07-21usb: cdns3: gadget: Configure speed in udc_startRavi Gunasekaran
When one of the functions does not support super speed, the composite driver forces the gadget to high speed. But the speed is never configured in the cdns3 gadget driver. So configure the speed in cdns3_gadget_udc_start just like in the kernel. Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com> Reviewed-by: Marek Vasut <marex@denx.de>
2023-07-21usb: ehci-mx6: remove unnecessary regulator enable from probeTim Harvey
Remove the regulator_set_enable() call from device probe which resolves a regulator imbalance. This is unnecessary as regulator_set_enable() will be called when ehci_register calls the init_after_reset hook. Suggested-by: Marek Vasut <marex@denx.de> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2023-07-21phy: sun4i: Add H616 USB PHY supportAndre Przywara
Now that the Allwinner USB PHY driver supports the H616 quirk, let's enable support for USB ports on that SoC. We connect the compatible string to a new struct describing the SoCs USB PHY properties, and unblock the PHY driver selection in Kconfig. A later patch will enable USB support in the H616 boards' defconfigs. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-07-21phy: sun4i-usb: Add H616 USB PHY quirk supportAndre Przywara
The H616 USB PHY is some kind of special snowflake: Only port2 works out of the box, but all other ports need some help from this port2 to work correctly: The CLK_BUS_PHY2 and RST_USB_PHY2 clock and reset need to be enabled, and the SIDDQ bit in the PMU PHY control register needs to be cleared. For this register to be accessible, CLK_BUS_ECHI2 needs to be ungated. Don't ask .... Follow the respective Linux patch (b45c6d80325b) and add a quirk bit, triggering the special sequence as outlined above, for PHYs other than PHY2: ungate this one special clock, and clear the SIDDQ bit. We also pick the clock and reset from PHY2 and enable them as well. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-07-21phy: sun4i-usb: Replace types with explicit quirk flagsAndre Przywara
So far we were assigning some crude "type" (SoC name, really) to each Allwinner USB PHY model, then guarding certain quirks based on this. This does not only look weird, but gets more or more cumbersome to maintain. Remove the bogus type names altogether, instead introduce flags for each quirk, and explicitly check for them. This improves readability, and simplifies future extensions. Port of Linux patch 8dd256bae653. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-07-21sunxi: Kconfig: rework PHY_USB_SUN4I selectionAndre Przywara
At the moment we use "select" in each Allwinner SoC's Kconfig section to include the USB PHY driver in the build. This means it cannot be disabled via Kconfig, although USB is not really a strictly required core functionality, and a particular board might not even include USB ports. Rework the Kconfig part by removing the "select" lines for each SoC's section, and instead letting it default to "y" in the PHY driver section itself. We use "depends on !" to exclude the few SoCs we don't support (yet). The Allwinner V3s does not enable USB (PHY) support at the moment, even though it should work: let the PHY default to "n" to keep the current behaviour. Also the MUSB USB driver directly calls some functions from the PHY driver, so let the former depend on the PHY driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Tested-by: Sam Edwards <CFSworks@gmail.com>
2023-07-21phy: sun4i-usb: add Allwinner F1C100s supportAndre Przywara
The Allwinner F1C100s implements a single USB PHY, connected to its MUSB OTG controller. The USB PHY is of the simpler, older type (like the A10), the only real difference is that it's indeed only one PHY. Add a struct describing those F1C100s USB PHY properties, and connect it to the new compatible string. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-07-21phy: sun4i-usb: Fix of_xlate() argument checkAndre Przywara
In its of_xlate() function, the Allwinner USB PHY driver compares the args_count variable against the number of implemented USB PHYs, although this is the *number of arguments* to the DT phandle property. Per the DT binding for this PHY device, this number is always one, so this check will always fail if the particular SoC implements exactly one USB PHY. So far this affected only the V3s (which has USB support disabled), but the F1C100s also sports one PHY only. Fix that check to compare args_count against exactly 1, and the args[0] content (requested PHY number) against the number of implemented PHYs. This fixes USB operation on the Allwinner V3s and allows to enable USB on the Allwinner F1C100s SoC. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-07-20core: read: fix dev_read_addr_size()John Keeping
The behaviour of dev_read_addr_size() is surprising as it does not handle #address-cells and #size-cells but instead hardcodes the values based on sizeof(fdt_addr_t). This is different from dev_read_addr_size_index() and dev_read_addr_size_name() both of which do read the cell sizes from the device tree. Since dev_read_addr_size() is only used by a single driver and this driver is broken when CONFIG_FDT_64BIT does not match the address size in the device tree, fix the function to behave like all of the other similarly named functions. Drop the property name argument as the only caller passes "reg" and this is the expected property name matching the other similarly named functions. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # chromebook_jerry Tested-by: Simon Glass <sjg@chromium.org> # chromebook_bob
2023-07-20dm: core: of_access: fix return value in of_property_match_stringEugen Hristev
of_property_match_string calls of_find_property to search for the string property. If the device node does not exist, of_find_property returns NULL, and of_property_match_string returns -EINVAL, which is correct. However, if the device node exists, but the property is not found, of_find_property still returns NULL, but it will place -FDT_ERR_NOTFOUND in the *lenp variable. of_property_match_string does not use the lenp parameter, thus this error case is being lost, and treated as if the node is NULL, and returns -EINVAL, which is incorrect. The callers of of_property_match_string treat the error differently if the return value is -EINVAL or -ENOENT, e.g. in dwc3 driver: ret = generic_phy_get_by_name(dev, "usb3-phy", &phy); if (!ret) { ret = generic_phy_init(&phy); if (ret) return ret; } else if (ret != -ENOENT && ret != -ENODATA) { debug("could not get phy (err %d)\n", ret); return ret; } else { phy.dev = NULL; } So the caller drivers will just consider the property missing if -ENOENT is returned, versus the case of -EINVAL, which means something else. To fix this situation, changed the code to call the of_find_property with the right third argument to catch this error code and treat it accordingly. Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-07-18Merge https://source.denx.de/u-boot/custodians/u-boot-mmcTom Rini
2023-07-18mmc: Set clock when reverting to safe bus modeValentine Barshak
Set MMC clock when reverting to safe bus mode and speed in case current MMC mode fails. Otherwise, trying out the other modes may fail as well. Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> [hp: fallback to legacy_speed] Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-07-18mmc: renesas-sdhi: Send stop when MMC tuning command failsHai Pham
When tuning command (CMD21) fails with command error, call mmc_send_stop_transmission() to send stop command (CMD12). Reviewed-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> [Marek: Add dev_dbg() message in case tuning abort fails Move tuning opcode check from mmc_abort_tuning()] Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-07-18mmc: Introduce mmc_send_stop_transmission()Hai Pham
If a tuning command times out, the card could still be processing it, which will cause problems for recovery. The eMMC specification section 6.6 Data transfer mode (cont’d) claims that CMD12 can be used to stop CMD21: " The relationship between the various data transfer modes is summarized (see Figure 27): - All data read commands can be aborted any time by the stop command (CMD12). The data transfer will terminate and the Device will return to the Transfer State. The read commands are: ... send tuning block (CMD21) .... " Add a function that does that. Based on Linux commit [1] and [2]. [1] e711f0309109 ("mmc: mmc: Introduce mmc_abort_tuning()") [2] 21adc2e45f4e ("mmc: Improve function name when aborting a tuning cmd") Reviewed-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> [Marek: Update commit message, quote relevant part of the specification. Rename to mmc_send_stop_transmission(). Remove tuning opcode check, this is controller driver specific. Deduplicate part of mmc_read_blocks() using this function.] Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-07-18mmc: Fix MMC_CMD_STOP_TRANSMISSION response type and add commentMarek Vasut
For MMC/eMMC, the MMC_CMD_STOP_TRANSMISSION response is R1 for read transfers and R1b for write transfers per JEDEC Standard No. 84-B51 Page 126 . The response is R1b unconditionally per Physical Layer Simplified Specification Version 9.00. Correct the response type and add a comment about it. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Peng Fan <peng.fan@nxp.com>
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-07 11:50:19 +0000