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2021-10-23mtd: spi-nor-core: Check return value of write_enable() in spi_nor_erase()Marek Behún
The spi_nor_erase() function does not check return value of the write_enable() call. Fix this. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Tested-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-10-23mtd: spi-nor-core: Try cleaning up in case writing BAR failedMarek Behún
Use the cleanup codepath of spi_nor_erase() also in the event of failure of writing the BAR register. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Tested-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-10-23mtd: spi-nor: Add support for Spansion S25FL256LTakahiro Kuwano
The S25FL256L is a part of the S25FL-L family and has the same feature set as S25FL128L except the density. The datasheet can be found in the following link. https://www.cypress.com/file/316171/download The S25FL256L is 32MB NOR Flash that does not support Bank Address Register. This fixup is activated if CONFIG_SPI_FLASH_BAR is enabled and returns ENOTSUPP in setup() hook to avoid further ops. Tested on Xilinx Zynq-7000 FPGA board. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
2021-10-23mtd: spi-nor-ids: Add GD25LQ256D ChipYanhong Wang
Add Gigadevice GD25LQ256D SPI NOR chip. https://www.gigadevice.com/datasheet/gd25lq256d/ Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [jagan: updated commit message] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-10-08mtd: spi-nor-ids: Reinstate Micron MT25QL02GMarek Vasut
This ID disappeared in 5b66fdb29dc ("mtd: spi: Remove unused files"), add the ID back, since the chip is used on devices supported by U-Boot. Fixes: 5b66fdb29dc ("mtd: spi: Remove unused files") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Horatiu Vultur <horatiu.vultur@microchip.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Stefan Roese <sr@denx.de> Cc: Vignesh R <vigneshr@ti.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-10-08mtd: spinand: macronix: Fix ECC Status ReadHaolin Li
According to datasheet, the upper four bits are reserved or used for reflecting the ECC status of the accumulated pages. The error bits number for the worst segment of the current page is encoded on lower four bits. Fix it by masking the upper bits. This same issue has been already fixed in the linux kernel by: "mtd: spinand: macronix: Fix ECC Status Read" (sha1: f4cb4d7b46f6409382fd981eec9556e1f3c1dc5d) Apply the same fix in the U-Boot driver. Signed-off-by: Haolin Li <li.haolin@qq.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-10-07Merge tag 'u-boot-amlogic-20211007' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-amlogic - Add new SoC ID for S905Y2 found in Radxa Zero - pcie_dw_meson: fix usb fail when pci link fails to go up - Sync Amlogic DT from Linux 5.14 - dwc3-meson-gxl: add AXG compatible - dts: keep back HW order for MMC devices since change in Upstream Linux - Cleanup local AXG DT USB nodes now everything is upstream - distro_bootcmd: run pci enum for scsi_boot just like it is done for nvme_boot - New Boards: - Odroid-HC4: a variant of Odroid-C4 with 2 SATA ports (via PCIe-SATA bridge) - Beelink GS-King X: A variant of the other Beelink board with 2 SATA ports (via USB3-SATA bridge) - Banana Pi M5: another credit card SBC - JetHub D1/H1: home automation controllers - Radxa Zero: another RPi Zero sized SBC
2021-10-07usb: dwc3: meson-gxl: add AXG compatibleNeil Armstrong
Upstream Linux uses the "amlogic,meson-axg-usb-ctrl" for AXG SoCs. This adds it to the compatible list for this driver. Reported-by: Vyacheslav Bocharov <adeep@lexina.in> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Vyacheslav Bocharov <adeep@lexina.in>
2021-10-07pci: pcie_dw_meson: fix usb fail when pci link fails to go upNeil Armstrong
On Amlogic A311D, when the PCIe link fails disabling the related clocks makes USB fail. For an unknown reason, this doesn happen on the S905D3 SoC. Mimic the Linux behavior by not considering a link failure a probe failure, and continue even if the PCIe link is down. Reported-by: Art Nikpal <email2tema@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-10-07sysreset: provide SBI based sysreset driverHeinrich Schuchardt
Provide sysreset driver using the SBI system reset extension. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Samuel Holland <samuel@sholland.org>
2021-10-07serial: Add a debug console using the RISC-V SBI interfaceSamuel Holland
The RISC-V SBI interface v0.1 provides a function for printing a character to the console. Even though SBI v0.1 functions are deprecated, the SBI console is quite useful for early debugging, because it works without any dcache, memory, or MMIO access in S mode. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-10-07clk: k210: Try harder to get the best configSean Anderson
In some cases, the best config cannot be used because the VCO would be out-of-spec. In these cases, we may need to try a worse combination of r/od in order to find the best representable config. This also adds a few test cases to catch this and other (possible) unlikely errors. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-07k210: clk: Refactor out_of_spec testsSean Anderson
Everything here sits in a while (true) loop. However, this introduces a couple of layers of indentation. We can simplify the code by introducing a single goto instead of using continue/break. This will also make adding loops in the next patch easier. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-10-07clk: k210: Fix checking if ulongs are less than 0Sean Anderson
The PLL functions take ulong arguments for rate, but still check if that rate is negative (which is never true). The correct way to handle this is to use IS_ERR_VALUE (like is already done in k210_clk_set_rate). While we're at it, we can move the error checking up into the caller of the pll set/get rate functions. This also protects our other calculations from using bogus values for rate. Fixes: 609bd60b94 ("clk: k210: Rewrite to remove CCF") Reported-by: Coverity Scan <scan-admin@coverity.com> Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-10-06Convert CONFIG_NAND_OMAP_ECCSCHEME to KconfigTom Rini
The values of CONFIG_NAND_OMAP_ECCSCHEME map to the enum in include/linux/mtd/omap_gpmc.h for valid ECC schemes. Make which one we will use be a choice statement, enumerating the ones which we have implemented. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06Convert CONFIG_NAND_FSL_ELBC et al to KconfigTom Rini
This converts the following to Kconfig: CONFIG_NAND_FSL_ELBC CONFIG_NAND_FSL_IFC Note that a number of PowerPC platforms had previously enabled CONFIG_NAND_FSL_ELBC without CONFIG_MTD_RAW_NAND, and now they no longer enable the option, reducing the size of a few functions. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06Convert CONFIG_SYS_NAND_MAX_CHIPS to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SYS_NAND_MAX_CHIPS Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06nand.h: Cleanup linux/mtd/rawnand.h usageTom Rini
We only include <linux/mtd/rawnand.h> in <nand.h> for the forward declaration of struct nand_chip, so do that directly. Then, include <linux/mtd/rawnand.h> where required directly. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06Convert CONFIG_SYS_NAND_ONFI_DETECTION to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SYS_NAND_ONFI_DETECTION Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06Convert CONFIG_SYS_NAND_5_ADDR_CYCLE to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SYS_NAND_5_ADDR_CYCLE Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06Convert CONFIG_SYS_NAND_BAD_BLOCK_POS to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SYS_NAND_BAD_BLOCK_POS In order to do this, introduce a choice for HAS_LARGE/SMALL_BADBLOCK_POS as those are the only valid values. Use LARGE as the default as no in-tree boards use SMALL, but it is possible. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06nand_spl_simple: Drop CONFIG_SYS_NAND_4_ADDR_CYCLE supportTom Rini
This code is unused, drop it. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06Convert CONFIG_SYS_NAND_PAGE_COUNT to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SYS_NAND_PAGE_COUNT Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06Convert CONFIG_SPL_NAND_LOAD et al to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SPL_NAND_LOAD CONFIG_SYS_NAND_BLOCK_SIZE CONFIG_SYS_NAND_PAGE_SIZE CONFIG_SYS_NAND_OOBSIZE Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06Convert CONFIG_NAND_LPC32XX_MLC to KconfigTom Rini
This converts the following to Kconfig: CONFIG_NAND_LPC32XX_MLC Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-05reboot-mode: migrate uclass to livetreePatrick Delaunay
Use dev_ function to support a live tree. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-05demo: migrate uclass to livetreePatrick Delaunay
Use dev_ function to read the sides and colour to support a live tree. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-05remoteproc: migrate uclass to livetreePatrick Delaunay
Use dev_ function to read the name and boolean to support a live tree. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-05gpio: Factor out DT flag translationSamuel Holland
The generic GPIO flags binding is shared across many drivers, some of which need their own xlate function. Factor out the flag translation code from gpio_xlate_offs_flags so it does not need to be duplicated. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-05gpio: Verify validity of pin offsets from device treesSamuel Holland
Translation of an OF GPIO specifier should fail if the pin offset is larger than the number of pins in the GPIO bank. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-05gpio: Verify validity of pin offsets when looking up namesSamuel Holland
Translation of a pin name to a device+offset should fail if the offset is larger than the number of pins in the GPIO bank. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-05pinctrl: single: Add request() apiBharat Gooty
Add pinctrl_ops->request api to configure pctrl pad register in gpio mode. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com> Acked-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-05pinctrl: single: Parse gpio details from dtBharat Gooty
Parse different gpio properties from dt as part of probe function. This detail is required to enable pinctrl pad later when gpio lines are requested. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com> Acked-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
2021-10-04Merge branch 'next'Tom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-04mtd: cqspi: Fix division by zeroMarek Vasut
Both dummy.nbytes and dummy.buswidth may be zero. By not checking the later, it is possible to trigger division by zero and a crash. This does happen with tiny SPI NOR framework in SPL. Fix this by adding the check and returning zero dummy bytes in such a case. Fixes: 38b0852b0ea ("spi: cadence-qspi: Add support for octal DTR flashes") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Pratyush Yadav <p.yadav@ti.com> [trini: Drop Pratyush's RB as his requested changes weren't made as Marek disagreed]
2021-10-03watchdog: rti_wdt: Add support for loading firmwareJan Kiszka
To avoid the need of extra boot scripting on AM65x for loading a watchdog firmware, add the required rproc init and loading logic for the first R5F core to the watchdog start handler. In case the R5F cluster is in lock-step mode, also initialize the second core. The firmware itself is embedded into U-Boot binary to ease access to it and ensure it is properly hashed in case of secure boot. One possible firmware source is https://github.com/siemens/k3-rti-wdt. The board is responsible for providing the firmware as additional loadable via the U-Boot fit image. The driver will pick up its location from /fit-images/k3-rti-wdt-firmware then. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2021-10-03pci: pcie_layerscape_fixup_common: lx2_board_fix_fdt can be staticVladimir Oltean
To avoid W=1 build warnings, declare this function as static, since it is not used outside of this translation module. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-10-03pci: pcie_layerscape_fixup_common: include fdt_support.h for ft_pci_setupVladimir Oltean
The function prototype for ft_pci_setup is inside fdt_support.h, we need to include that header. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-10-03pci: layerscape: ls_pcie_conf_address can be staticVladimir Oltean
To avoid W=1 build warnings, declare this function as static, since it is not used outside of this translation module. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-10-03pci: _dm_pci_phys_to_bus can be staticVladimir Oltean
To avoid W=1 build warnings, declare this function as static, since it is not used outside of this translation module. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-10-03pci: pci_read_config can be staticVladimir Oltean
To avoid W=1 build warnings, declare this function as static, since it is not used outside of this translation module. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-10-03pci: pci_write_config can be staticVladimir Oltean
To avoid W=1 build warnings, declare this function as static, since it is not used outside of this translation module. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-10-03pci: include pci_internal.h inside pci_auto.cVladimir Oltean
To avoid a build warning with W=1, provide a function prototype for dm_pciauto_prescan_setup_bridge, which is a non-static function whose definition is inside pci_auto.c. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-10-03rtc: rx8025: revise single register write to use offsetMathew McBride
Writing of individual registers was not functioning correctly as a 0 'offset' byte under DM-managed I2C was being appended in front of register we wanted to access. Signed-off-by: Mathew McBride <matt@traverse.com.au>
2021-10-03rtc: rx8025: set date in a single i2c transactionMathew McBride
The RX8025/RX8035 does not like having it's time registers set byte-by-byte in separate I2C transactions. From the note at the top of the file, it appears target-dependent workarounds have been used in the past for this. Resolve this by setting the time registers in a single I2C transaction. As part of this, also ensure the '24/12' flag in the RTC is reset before writing the date (instead of after), otherwise the RX8035 will clear the seconds and minutes registers. Tested on Traverse Ten64 (NXP LS1088A) with RX8035. Signed-off-by: Mathew McBride <matt@traverse.com.au>
2021-10-03rtc: rx8025: add support for EPSON RX8035.Mathew McBride
The RX8035 is a newer model from EPSON which is very similar in operation to the RX8025. The changes mirror similar ones that will be in Linux 5.15: https://lore.kernel.org/all/20210709044518.28769-2-matt@traverse.com.au/ The UBOOT_DRIVER ID has also been corrected, previously it declared itself as rx8010sj_rtc which is a different driver. Signed-off-by: Mathew McBride <matt@traverse.com.au>
2021-10-03rtc: rx8025: drop non-DM supportMathew McBride
A search of the tree showed there is only one user of this driver (soon to be two) - board/socrates The second user will be the Traverse Ten64 board. Both these boards have DM_RTC. Signed-off-by: Mathew McBride <matt@traverse.com.au>
2021-10-01serial: Remove extraneous SYS_MALLOC_F checkTom Rini
We enforce that DM_SERIAL will have SYS_MALLOC_F enabled and so SYS_MALLOC_F_LEN will have a value. Remove the build-time check. Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-01arm: Remove zmx25 board and ARCH_MX25Tom Rini
This board has not been converted to CONFIG_DM by the deadline. Remove it. As this is the last ARCH_MX25 platform, remove those references as well. Cc: Matthias Weisser <weisserm@arcor.de> Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-01arm: Remove aspenite boardTom Rini
This board has not been converted to CONFIG_DM by the deadline. Remove it. As this is the last armada100 platform, remove that support as well. Cc: Prafulla Wadaskar <prafulla@marvell.com> Signed-off-by: Tom Rini <trini@konsulko.com>
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