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In both include/fsl_qe.h and then also remove common.h from the files
which had included fsl_qe.h
Signed-off-by: Tom Rini <trini@konsulko.com>
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There are no platforms which enable this feature, so remove it.
Signed-off-by: Tom Rini <trini@konsulko.com>
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Now that sandbox has <asm/barrier.h> and defines nop() there we should
include that in our driver for clarity and then remove our local nop()
from <k210/pll.h>.
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
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This option is necessary to compile any way.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
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Much of the functionality of fastboot relies on being able to run
commands as defined in the environment. This means it does depend on
CMDLINE being enabled.
Signed-off-by: Tom Rini <trini@konsulko.com>
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While it is nice to have the font command, using 'select' makes it
impossible to build the console code without it. Stop using 'select' and
make it default if CONSOLE_TRUETYPE is enabled when asking the command.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
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In order to do a DFU update over TFTP we need to have some network
device available, so make this depend on NETDEVICES
Signed-off-by: Tom Rini <trini@konsulko.com>
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As VIRTIO_NET is the symbol for enabling network devices, make this
depend on NETDEVICES
Signed-off-by: Tom Rini <trini@konsulko.com>
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https://source.denx.de/u-boot/custodians/u-boot-amlogic
- fixup to also enabled DFU RAM boot for libretech-ac
- sm fix to bind child sm devices in the device tree
- add missing A1 clocks for USB stack
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One well-known sm child device that provides secure power control is the
Secure Power Controller. This device utilizes SMC calls to communicate
with power domains on the secure monitor side.
Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com>
Signed-off-by: Alexey Romanov <avromanov@salutedevices.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231101140500.9025-3-avromanov@salutedevices.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
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Since we sync device tree with Linux, we have to add this
clock definition for USB stack.
Signed-off-by: Alexey Romanov <avromanov@salutedevices.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231101140500.9025-2-avromanov@salutedevices.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
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Older DesignWare Ethernet MAC versions that this driver supports can
only work with 32-bit DMA source/destination addresses. Some platforms
have no physical RAM at the lowest 4GB address space. For these
platforms the driver must translate DMA addresses to/from physical
memory addresses.
Call translation routines so that properly configured platforms can use
the DesignWare Ethernet MAC. For platforms using device-tree this
usually means adding dma-ranges property to the bus the device node is
in.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
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e1000_eth_ids holds compatible strings for e1000 devices, but it
is meaningless as e1000 is a PCI device and there is no such
compatible string assigned to e1000 by the DT bindings community.
Drop it.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Setting the clock delay from the device tree settings
rx-internal-delay-ps and tx-internal-delay-ps was broken:
- The expected value in the device tree is suppose to be a
delay in picoseconds, but the driver only allowed an array index.
- Driver converted this array index to the actual delay in
picoseconds and tried to apply this in the device register. This
however is not a valid register value. The actual logic here was
reversed, it converted an register representation of the delay to
the device tree delay in picoseconds.
Only when the internal delays were NOT configured in the device tree
and they default value of 7 (=2000ps) was used, a valid value was
loaded in the register.
Signed-off-by: Frank de Brabander <debrabander@gmail.com>
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It adds the driver for the internal MDIO bus of HIFEMAC Ethernet
controller. It's based on the mainstream linux driver.
Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
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It adds the driver for HIFEMAC Ethernet controller found on HiSilicon
SoCs like Hi3798MV200. It's based on the mainstream linux driver, but
quite a lot of code gets rewritten and cleaned up to adopt u-boot driver
model.
Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
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Marvell LinkStreet switches support Clause 45 MDIO on the internal bus.
C45 read or writes require the register address to be written first to
the SMI PHY Data register, and then a special C45 Write Address Register
OP is used on the SMI PHY Register before making a C45 Read Data Register
OP and being able to actually read the register.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
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Driver is currently defining the mask and bit shifting itself,
there is no need for that as U-Boot has generic bitfield macros that help
us achieve the same result but in a cleaner way.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
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Add optional reset control, especially for the Aspeed SOC. For the
hardware without a reset line, the reset assertion/deassertion will be
skipped.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
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Set upper 32bit address for DMA descriptors and buffer address to support
64-bit addressing.
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
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PALMAS PMIC family has embedded poweroff function used by some
device to initiane device power off. Implement it as sysreset
driver.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
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TPS65910/TPS65911 PMICs have embedded power control functions
used by some device to initiane device power off. Implement it as
sysreset driver.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
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TPS80031/TPS80032 PMICs have embedded power control functions
used by some device to initiane device power off. Implement it as
sysreset driver.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
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MAX77663 PMIC has embedded poweroff function used by some
device to initiane device power off. Implement it as sysreset
driver.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
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Tegra uses built in Power Management Controller (PMC) to perform
CPU reset. Code to perform this was located in mach-tegra, so lest
create DM driver to handle this.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
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The driver provides regulator set/get voltage enable/disable
functions for TI TPS5911 PMIC.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Add support to bind the regulators/child nodes with the pmic.
Also adds the pmic i2c based read/write functions to access pmic
registers.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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The driver provides regulator set/get voltage enable/disable
functions for TI TPS80031/TPS80032 PMICs.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Add support to bind the regulators/child nodes with the pmic.
Also adds the pmic i2c based read/write functions to access pmic
registers.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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The driver provides regulator set/get voltage
enable/disable functions for MAXIM MAX77663 PMICs.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
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Add support to bind the regulators/child nodes with the pmic.
Also adds the pmic i2c based read/write functions to access pmic
registers.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
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dev->driver_data will carry the tail of ldo if there is a number and
if there is no number it will be an error code, anyway it will not be
zero. This results in a wrong ldo regulator detection.
To avoid this check for non-numerical ldo first and then manipulate
dev->driver_data.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
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Existing PALMAS PMIC driver is fully compatible with TI TPS65913
PMIC found in many Tegra 4 devices, like Tegra Note 7 and ASUS
TF701T. TPS65913 shares same structure of regulators like TPS659038
so data can be reused.
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # NVIDIA Tegratab
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
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Default-tap and default-trim values are used for eMMC setup
mostly on T114+ devices. As for now, those values are hardcoded
for T210 and ignored for all other Tegra generations. Fix this
by passing tap and trim values from dts.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
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https://source.denx.de/u-boot/custodians/u-boot-dfu
u-boot-dfu-20231103
- Fix CRC chunk size in fastboot
- Make size optional for dfu on mmc
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Just various bugfixes, apart from the TI one
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on Peach-pi console every key press is echoed with message
'cros_ec_command: Returned status 1'
this is not proper fix, just hack to disable this message
Signed-off-by: Milan P. Stanić <mps@arvanta.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
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https://source.denx.de/u-boot/custodians/u-boot-sh
- Remove common.h usage
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https://source.denx.de/u-boot/custodians/u-boot-i2c
i2c updates for v2024.01-rc2
- nuvoton: support standard/fast/fast plus mode
- bootcount: remove legacy i2c driver and implement
DM based version
Bugfixes:
- designware_i2c: adjust timing calculation
SPL probing failed on the StarFive VisionFive 2 board
Heinrich fixed this, by syncing timing calculation with
linux implementation.
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+ CI: Use OpenSBI 1.3.1 release for testing
+ riscv: Support resume after exception
+ rng: Support RNG provided by RISC-V Zkr ISA extension
+ board: starfive VF2: Support jtag
+ board: starfive VF2: Support TRNG driver
+ board: sifive unmatched: Move kernel load address
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In line with changes elsewhere, drop inclusion of the common header.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
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In line with changes elsewhere, drop inclusion of the common header.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
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In line with changes elsewhere, drop inclusion of the common header.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
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In line with changes elsewhere, drop inclusion of the common header.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
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In line with changes elsewhere, drop inclusion of the common header.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
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Adds to support JH7110 TRNG driver which is based on linux kernel's
jh7110-trng.c. This can support to generate 256-bit random numbers and
128-bit but this makes 256-bit default for convenience.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
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Add STGCLK_SEC_HCLK and STGCLK_SEC_MISCAHB clocks for JH7110 TRNG
device.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
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The Zkr ISA extension (ratified Nov 2021) introduced the seed CSR. It
provides an interface to a physical entropy source.
A RNG driver based on the seed CSR is provided. It depends on
mseccfg.sseed being set in the SBI firmware.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
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https://source.denx.de/u-boot/custodians/u-boot-clk
Clock changes for 2024.01-rc2
This contains several fixes for the clock core.
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In clk_enable()/clk_disable() functions, when CCF is activated,
we must pass a private clk struct to enable()/disable() ops functions.
Otherwise, the use of a container_of() construction within these ops
should be banned. Because passing a non-private clk struct to
container_of() results in an out of range error.
At the moment, clk-mux, clk-fixed-factor, clk-gate and possibly other
clocks use container_of() in their enable()/disable() functions.
Therefore, for these functions to work correclty, private clk struct
must be passed.
Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20230905221649.3577929-1-bigunclemax@gmail.com
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