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2024-04-21Merge tag 'video-20240421' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-video CI: https://source.denx.de/u-boot/custodians/u-boot-video/-/pipelines/20466 - simple_panel: support timing parsing from EDID - dw_hdmi: fix gcc-14 compiler warnings - dw_hdmi: support vendor PHY for HDMI - rockchip: add Rockchip INNO HDMI PHY driver - rockchip: RK3328 HDMI and VOP support - evb-rk3328: enable vidconsole support - Tegra DC and DSI improvements and Tegra 114 support - add LG LG070WX3 MIPI DSI panel driver - add Samsung LTL106HL02 MIPI DSI panel driver - add Toshiba TC358768 RGB to DSI bridge support - add basic support for the Parade DP501 transmitter - Tegra 3 panel and bridge driver improvements - simplefb: modernise DT parsing - fdt_simplefb: Enumerate framebuffer info from video handoff - preserve framebuffer if SPL is passing video hand-off - fdt_support: allow reserving FB region without simplefb
2024-04-21video: Assume video to be active if SPL is passing video hand-offDevarsh Thakkar
If SPL is passing video handoff structure to U-boot then it is safe to assume that SPL has already enabled video and that's why it is passing video handoff structure to U-boot so that U-boot can preserve the framebuffer. Signed-off-by: Devarsh Thakkar <devarsht@ti.com> Reviewed-by: Nikhil M Jain <n-jain1@ti.com>
2024-04-21video: simplefb: modernise DT parsingCaleb Connolly
simplefb was using old style FDT parsing which doesn't behave well in combination with livetree. Update it to use ofnode instead and add a missing null check for the "format" property. Standardise the error logging while we're here. Fixes: 971d7e64245d ("video: simplefb") Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-21video: renesas: shift the init sequence by one step earlierSvyatoslav Ryhel
Shift all setup stages one step earlier to better fit the existing uclass. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2024-04-21video: bridge: ssd2825: shift the init sequence by one step earlierSvyatoslav Ryhel
Shift all setup stages one step earlier to better fit the existing uclass. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2024-04-21video: endeavoru-panel: shift the init sequence by one step earlierSvyatoslav Ryhel
Shift all setup stages one step earlier to better fit the existing uclass. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2024-04-21video: bridge: add basic support for the Parade DP501 transmitterJonas Schwöbel
The Parade DP501 is a DP & DVI/HDMI dual-mode transmitter. It enables an RGB/Parallel SOC output to be converted, packed and serialized into either DP or TMDS output device. Only DisplayPort functionality of this transmitter has been implemented and tested. Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2024-04-21video: bridge: add Toshiba TC358768 RGB to DSI bridge supportSvyatoslav Ryhel
Add initial support for the Toshiba TC358768 RGB to DSI bridge. The driver is based on the mainline Linux Toshiba TC358768 bridge driver and implements the same set of features. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF700T Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2024-04-21video: panel: add Samsung LTL106HL02 MIPI DSI panel driverAnton Bambura
LTL106HL02 is a color active matrix TFT (Thin Film Transistor) liquid crystal display (LCD) that uses amorphous silicon TFT as switching devices. This model is composed of a TFT LCD panel, a driver circuit and a backlight unit. The resolution of a 10.6" contains 1920 x 1080 pixels and can display up to 16,8M color with wide viewing angle. Co-developed-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Co-developed-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Anton Bambura <jenneron@protonmail.com>
2024-04-21video: panel: add LG LG070WX3 MIPI DSI panel driverSvyatoslav Ryhel
The LD070WX3 is a Color Active Matrix Liquid Crystal Display with an integral Light Emitting Diode (LED) backlight system. The matrix employs a-Si Thin Film Transistor as the active element. It is a transmissive type display operating in the normally Black mode. This TFT-LCD has 7.0 inches diagonally measured active display area with WXGA resolution (800 by 1280 pixel array). Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2024-04-21video: tegra20: dsi: use set_backlight for backlight onlyJonas Schwöbel
Shift the backlight set further to prevent visual glitches on panel init. Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2024-04-21video: tegra20: dsi: set correct fifo depthJonas Schwöbel
According to Thierry Reding's commit in the linux kernel 976cebc35bed0456a42bf96073a26f251d23b264 "drm/tegra: dsi: Make FIFO depths host parameters" correct depth of the video FIFO is 1920 *words* no *bytes* Tested-by: Ion Agorria <ion@agorria.com> # HTC One X Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Nvidia Tegratab T114 Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2024-04-21video: tegra20: dsi: remove pre-configurationJonas Schwöbel
Configuration for DC driver command mode is not required for every panel. Removed. Tested-by: Ion Agorria <ion@agorria.com> # HTC One X Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Nvidia Tegratab T114 Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2024-04-21video: tegra20: dsi: add reset supportSvyatoslav Ryhel
Implement reset use to discard any changes which could have been applied to DSI before and can interfere with current configuration. Tested-by: Ion Agorria <ion@agorria.com> # HTC One X Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Nvidia Tegratab T114 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2024-04-21video: tegra20: dsi: add T114 supportSvyatoslav Ryhel
Existing Tegra DSI driver mostly fits T114 apart MIPI calibration which on T114 has dedicated driver. To resolve this MIPI calibration logic was split for pre-T114 and T114+ devices. Tested-by: Ion Agorria <ion@agorria.com> # HTC One X Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Nvidia Tegratab T114 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2024-04-21video: tegra20: add MIPI calibration driverSvyatoslav Ryhel
Dedicated MIPI calibration driver is used on T114 and newer. Before T114 MIPI calibration registers were part of VI and CSI. Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Nvidia Tegratab T114 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2024-04-21video: tegra20: dc: parameterize V- and H-sync polaritiesSvyatoslav Ryhel
Based on Thierry Reding's Linux commit: 'commit 1716b1891e1de05e2c20ccafa9f58550f3539717 ("drm/tegra: rgb: Parameterize V- and H-sync polarities")' Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2024-04-21video: tegra20: dc: clean framebuffer memory blockJonas Schwöbel
Fill the framebuffer memory with zeros to avoid visual glitches. Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2024-04-21video: tegra20: dc: enable backlight after DC is configuredJonas Schwöbel
The goal of panel_set_backlight() is to enable backlight. Hence, it should be called at the probe end. Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2024-04-21video: tegra20: dc: fix printing of framebuffer addressJonas Schwöbel
Framebuffer address should not be a pointer. Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2024-04-21video: tegra20: dc: configure behavior if PLLD/D2 is usedSvyatoslav Ryhel
If DISP1 is a PLLD/D2 child, it cannot go over 370MHz. The cause of this is not quite clear. This can be overcomed by further halving the PLLD/D2 if the target parent rate is over 800MHz. This way DISP1 and DSI clocks will have the same frequency. The shift divider in this case has to be calculated from the original PLLD/D2 frequency and is passed from the DSI driver. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS Grouper E1565 Tested-by: Ion Agorria <ion@agorria.com> # HTC One X Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Nvidia Tegratab T114 Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Microsoft Surface 2 Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com>
2024-04-21video: tegra20: dc: add powergateSvyatoslav Ryhel
Add powergate use on T114 to complete resetting of DC. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2024-04-21video: tegra20: dc: add PLLD2 parent supportSvyatoslav Ryhel
T30+ SOC have second PLLD - PLLD2 which can be actively used by DC and act as main DISP1/2 clock parent. Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS Grouper E1565 Tested-by: Ion Agorria <ion@agorria.com> # HTC One X Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Nvidia Tegratab T114 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2024-04-21video: tegra20: dc: pass DC id to internal devicesSvyatoslav Ryhel
Tegra SoC has 2 independent display controllers called DC_A and DC_B, they are handled differently by internal video devices like DSI and HDMI controllers so it is important for last to know which display controller is used to properly set up registers. To achieve this, a pipe field was added to pdata to pass display controller id to internal Tegra SoC devices. Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS Grouper E1565 Tested-by: Ion Agorria <ion@agorria.com> # HTC One X Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Nvidia Tegratab T114 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2024-04-21video: tegra20: consolidate DC headerSvyatoslav Ryhel
Consolidate HD headers and place the result into video/tegra20 since it is used only by devices from this directory. Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS Grouper E1565 Tested-by: Ion Agorria <ion@agorria.com> # HTC One X Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Nvidia Tegratab T114 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2024-04-21video: tegra20: dc: fix image shift on rotated panelsSvyatoslav Ryhel
Subtracting 1 from x and y fixes image shifting on rotated panels. Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS Grouper E1565 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2024-04-21video: tegra20: dc: diverge DC per-SOCSvyatoslav Ryhel
Diverge DC driver setup to better fit each of supported generations of Tegra SOC. Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS Grouper E1565 Tested-by: Ion Agorria <ion@agorria.com> # HTC One X Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Nvidia Tegratab T114 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2024-04-21video: dw_hdmi: Fix compiler warnings with gcc-14Khem Raj
GCC-14 find more warnings like "make pointer from integer without a cast" fix them by adding a type cast. Signed-off-by: Khem Raj <raj.khem@gmail.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Tom Rini <trini@konsulko.com>
2024-04-21video: rockchip: Add rk3328 vop supportJagan Teki
Add support for Rockchip RK3328 VOP. Require VOP cleanup before handoff to Linux by writing reset values to WIN registers. Without this Linux VOP trigger page fault as below [ 0.752016] Loading compiled-in X.509 certificates [ 0.787796] inno_hdmi_phy_rk3328_clk_recalc_rate: parent 24000000 [ 0.788391] inno-hdmi-phy ff430000.phy: inno_hdmi_phy_rk3328_clk_recalc_rate rate 148500000 vco 148500000 [ 0.798353] rockchip-drm display-subsystem: bound ff370000.vop (ops vop_component_ops) [ 0.799403] dwhdmi-rockchip ff3c0000.hdmi: supply avdd-0v9 not found, using dummy regulator [ 0.800288] rk_iommu ff373f00.iommu: Enable stall request timed out, status: 0x00004b [ 0.801131] dwhdmi-rockchip ff3c0000.hdmi: supply avdd-1v8 not found, using dummy regulator [ 0.802056] rk_iommu ff373f00.iommu: Disable paging request timed out, status: 0x00004b [ 0.803233] dwhdmi-rockchip ff3c0000.hdmi: Detected HDMI TX controller v2.11a with HDCP (inno_dw_hdmi_phy2) [ 0.805355] dwhdmi-rockchip ff3c0000.hdmi: registered DesignWare HDMI I2C bus driver [ 0.808769] rockchip-drm display-subsystem: bound ff3c0000.hdmi (ops dw_hdmi_rockchip_ops) [ 0.810869] [drm] Initialized rockchip 1.0.0 20140818 for display-subsystem on minor 0 Signed-off-by: Jagan Teki <jagan@edgeble.ai>
2024-04-21video: rockchip: Add rk3328 hdmi supportJagan Teki
Add Rockchip RK3328 HDMI Out driver. Signed-off-by: Jagan Teki <jagan@edgeble.ai>
2024-04-21phy: rockchip: Add Rockchip INNO HDMI PHY driverJagan Teki
Add Rockchip INNO HDMI PHY driver for RK3328. Reference from linux-next phy-rockchip-inno-hdmi driver. Signed-off-by: Jagan Teki <jagan@edgeble.ai>
2024-04-21clk: rk3328: Add get hdmiphy clockJagan Teki
Add support to get the hdmiphy clock for RK3328 PCLK_HDMIPHY. Signed-off-by: Jagan Teki <jagan@edgeble.ai>
2024-04-21clk: rockchip: rk3328: Add VOP clk supportJagan Teki
VOP get and set clock would needed for VOP drivers. Add support for it. Signed-off-by: Jagan Teki <jagan@edgeble.ai>
2024-04-21video: rockchip: vop: Add dsp offset supportJagan Teki
Unlike RK3399, RK3288 the Newer Rockchip SoC's like RK3328 have different offsets for dsp registers. Group the dsp register set via dsp_regs pointers so that dsp_offset would point the dsp_regs to access for any changes in the offset value. Signed-off-by: Jagan Teki <jagan@edgeble.ai>
2024-04-21video: rockchip: vop: Add win offset supportJagan Teki
Unlike RK3399, RK3288 the Newer Rockchip SoC's like RK3328 have different offsets for win registers. Group the win register set via win_regs pointers so that win_offset would point the win_regs to access for any changes in the offset value. Signed-off-by: Jagan Teki <jagan@edgeble.ai>
2024-04-21video: rockchip: vop: Simplify rkvop_enableJagan Teki
Get the regs from priv pointer instead of passing it an argument. This would simplify the code and better readability. Signed-off-by: Jagan Teki <jagan@edgeble.ai>
2024-04-21video: dw_hdmi: Add setup_hpd hookJagan Teki
Add support for DW HDMI Setup HPD status. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
2024-04-21video: dw_hdmi: Add read_hpd hookJagan Teki
Add support for DW HDMI Read HPD status. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
2024-04-21video: dw_hdmi: Extend the HPD detectionJagan Teki
HPD detection on some DW HDMI designed SoC's would need to read and setup the HPD status explicitly. So, extend the HPD detection code by adding the dw_hdmi_detect_hpd function and move the default detection code caller there. The new read and setup hdp will integrate the same function in later patches. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
2024-04-21video: dw_hdmi: Add Vendor PHY handlingJagan Teki
DW HDMI support Vendor PHY like Rockchip RK3328 Inno HDMI PHY. Extend the vendor phy handling by adding platform phy hooks. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
2024-04-21video: rockchip: hdmi: Detect hpd after controller initJagan Teki
HDP is a hardware connector event, so detect the same once the controller and attached PHY initialization are done. Signed-off-by: Jagan Teki <jagan@edgeble.ai>
2024-04-21video: simple_panel: add EDID supportSvyatoslav Ryhel
Support timing parsing from EDID if panel device tree node provides DDC i2c bus instead of timings node. Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF201 Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> [agust: reworked to fix dm_i2c_* build errors and to big img size] Signed-off-by: Anatolij Gustschin <agust@denx.de>
2024-04-20video: simple_panel: simplify platform data passSvyatoslav Ryhel
Pass MIPI DSI platform data to simple DSI panel directly from driver data on panel probe. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2024-04-20pci: dw_imx: add support for IMX8MMTim Harvey
Add support for the IMX8MM SoC by adding driver data with the compatible string of the GPR controller. Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2024-04-20clk: imx8mm: Add support for PCIe clocksTim Harvey
Add support for PCIe clocks required to enable PCIe support on iMX8MM SoC. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Marek Vasut <marex@denx.de>
2024-04-19Merge tag 'u-boot-stm32-20240419' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-stm MP1: _ Add OHCI HCD support for STM32MP15xx DHSOM _ Report OTP-CLOSED instead of rev.? on closed STM32MP15xx _ Initialize TAMP_SMCR BKP..PROT fields on STM32MP15xx _ Jump to ep on successful resume in PSCI suspend code _ Add FASTBOOT support for STM32MP13 _ Fix/Rework key and leds management for STM32MP13/15 _ net: dwc_eth_qos: Clean up STM32 glue code and add STM32MP13xx support MP2: _ Add stm32-fmc-ebi support _ Add: sdmmc2 support and fix AARCH64 compilation
2024-04-19Merge tag 'u-boot-dfu-20240419' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-dfu u-boot-dfu-20240419 - new "fastboot oem board" command
2024-04-19mmc: stm32_sdmmc2: Fix AARCH64 compilation warningsPatrice Chotard
When building with AARCH64 defconfig, we got warnings, fix them. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2024-04-19mmc: stm32_sdmmc2: Add "st,stm32mp25-sdmmc2" compatiblePatrick Delaunay
Add compatible used for STM32MP25 family. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2024-04-19net: dwc_eth_qos: Add support for st, ext-phyclk propertyMarek Vasut
The "st,ext-phyclk" property is a unification of "st,eth-clk-sel" and "st,eth-ref-clk-sel" properties. All three properties define ETH CK clock direction, however: - "st,eth-clk-sel" selects clock direction for GMII/RGMII mode - "st,eth-ref-clk-sel" selects clock direction for RMII mode - "st,ext-phyclk" selects clock direction for all RMII/GMII/RGMII modes The "st,ext-phyclk" is the preferrable property to use. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Christophe ROULLIER <christophe.roullier@foss.st.com>
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-05 19:42:42 +0000