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Rename rmobile_is_gen3_mmc0() to rcar_is_gen3_mmc0() because
this particular function is specific to Renesas R-Car Gen3.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
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Rename ARCH_RMOBILE to ARCH_RENESAS because all the chips are made
by Renesas, while only a subset of them is from the R-Mobile
line.
Use the following command to perform the rename:
"
$ git grep -l 'ARCH_RMOBILE' | xargs -I {} sed -i 's@ARCH_RMOBILE@ARCH_RENESAS@g' {}
"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
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Rename rmobile.h to renesas.h because all the chips are made
by Renesas, while only a subset of them is from the R-Mobile
line.
Use the following command to perform the rename:
"
$ git grep -l 'include.*rmobile.h' | \
xargs -I {} sed -i '/include.*rmobile.h/ s@rmobile.h@renesas.h@g' {}
"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
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Rename RMOBILE_CPU_TYPE_* to RENESAS_CPU_TYPE_* because all
the chips are made by Renesas, while only a subset of them is
from the R-Mobile line.
Use the following command to perform the rename:
"
$ git grep -l '\<RMOBILE_CPU_TYPE_[A-Z0-9]\+\>' | \
xargs -I {} sed -i 's@\<RMOBILE\(_CPU_TYPE_[A-Z0-9]\+\)\>@RENESAS\1@g' {}
"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
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Rename rmobile_get_cpu_rev_*() to renesas_get_cpu_rev_*() because
all the chips are made by Renesas, while only a subset of them is
from the R-Mobile line.
Use the following command to perform the rename:
"
$ git grep -l '\<rmobile_get_cpu_rev_\(integer\|fraction\)\>' | \
xargs -I {} sed -i 's@\<rmobile_get_cpu_rev_\(integer\|fraction\)\>@renesas_get_cpu_rev_\1@g' {}
"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
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Rename rmobile_get_cpu_type() to renesas_get_cpu_type() because
all the chips are made by Renesas, while only a subset of them
is from the R-Mobile line.
Use the following command to perform the rename:
"
$ git grep -l '\<rmobile_get_cpu_type\>' | \
xargs -I {} sed -i 's@\<rmobile_get_cpu_type\>@renesas_get_cpu_type@g' {}
"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
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https://gitlab.denx.de/u-boot/custodians/u-boot-snapdragon
- Two fixes for the qcom-pmic button driver
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i.MX93 uses the same USB IP as i.MX8MM. It can then reuse the ehci-mx6
driver.
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Mathieu Othacehe <othacehe@gnu.org>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
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The datasheet can be found here:
https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/EN25Q80B_Ver.E.pdf
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
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To prepare support for multiple register layouts pointers to register
tables where added to struct cpg_mssr_info. These pointers are suppose
to be filled in at probe time and no intended change in behavior was
intended.
However the new pointers where only filled in by some paths of the
driver implemented in clk-rcar-gen3.c. The path implemented in
clk-rcar-gen2.c was not updated leaving the pointers uninitialized
leading to a crash when trying to probe the clocks.
Fix this by filling in the pointers in the Gen2 code path with the
values used before they where moved to struct cpg_mssr_info.
Fixes: d413214fb748 ("clk: renesas: Add register pointers into struct cpg_mssr_info")
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Acked-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Tested-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # R8A7791 Porter
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
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https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2024.04-rc3
zynqmp:
- Cover missing _SE chip variants to fix fpga programming
versal:
- Enable LTO for mini configurations
versal-net:
- Enable LTO for mini configurations
- Fix GIC address to aligned with real silicon
xilinx:
- DTs cleanup and fixups
- Enable HTTP boot
- Add missing spl header to zynqmp.c
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This message isn't an error (there can be a watchdog subnode for example)
but it shouldn't be printed unless this driver is being debugged. Demote
it to a debug print.
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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The pmic_reg_read() function can return errors. Add a check for that.
Fixes: 4e8aa0065d4b ("button: qcom-pmic: introduce Qualcomm PMIC button driver")
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
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AM64 ES2.0 bootrom seems to enable WAIT0EDGEDETECTION interrupt.
This causes a lockup at A53 SPL when accessing NAND controller
or ELM registers.
A good option would be to softrest GPMC block at probe
but this cannot be done for AM64 as SOFTRESET bit is marked
as reserved in SYSCONFIG register.
Fix the issue by disabling all IRQs at probe.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
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Some platforms (such as the Lichee Pi 4A) have their dwmac device
addressable only in high memory space. Storing the node's base address
on 32 bits is not possible in such case.
Use platform's physical address type to store the base address.
Signed-off-by: Nils Le Roux <gilbsgilbert@gmail.com>
Cc: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI:
https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/19583
- Fix the i.MX8MP SPI compatible string.
- Let the SPL clock code do the configuration on Data Modul i.MX8M Plus
eDM SBC.
- Enable secure boot on the imx93_var_som board.
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ID code is added for zu67dr_SE, zu11eg_SE, zu19eg_SE and zu47dr_SE
variants. SE is the select edition of restricted devices with the
capabilities.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20240123045715.893652-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
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Recent i.MX8MP DTs use new fsl,imx6ul-ecspi compatible string instead
of the fsl,imx51-ecspi compatible string. Add the new compatible string
to fix ECSPI operation on i.MX8MP.
For details, see Linux:
48d74376fb68 ("arm64: dts: imx8mp: update ecspi compatible and clk")
8eb1252bbedf ("spi: imx: remove ERR009165 workaround on i.mx6ul")
Fixes: 451799a6ceac ("arm: dts: imx8mp: Sync the DT with kernel 6.4-rc4")
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
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Support RPC SPI on R8A779H0 V4M SoC.
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
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Add pinctrl tables for R8A779H0 V4M SoC.
The current version of these PFC tables is imported and squashed from:
https://lore.kernel.org/linux-renesas-soc/cover.1706264667.git.geert+renesas@glider.be/
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
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Add PLL7 support to Gen3/Gen4 common clock driver. Add initial PLL7
multiplier and divider values into table in R8A779H0 V4M clock driver.
The PLL7 is new PLL added in R8A779H0 V4M SoC. Only integer multiplication
mode is supported by PLL7. The PLL reference clock are either 16.66 MHz or
20 MHz on R8A779H0 V4M SoC, and the output frequency must be 2000 MHz. The
multiplier values fitting this requirement are calculated to 120 or 100.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
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Add clock tables for R8A779H0 V4M SoC.
The current version is imported from:
https://lore.kernel.org/linux-renesas-soc/c678ef7164e3777fa91572f72e47ef385cea64b8.1706194617.git.geert+renesas@glider.be/
The current version still contains PLL7 extras from the
previous version to provide ethernet support in U-Boot.
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
- Add USB support for phycore-imx8mp
- Fix environment corruption, reset on mx6sabresd
- Print reset cause on imx8
- Extend mkimage to support generating an image for i.MXRT FlexSPI
- Add new apalis and colibri variants
- Add support for phyBOARD-Segin-i.MX93 support
- Fix when FEC is primarily used instead of EQOS on i.MX93.
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Add implementation of sc_pm_reset_reason() call for obtaining
reset reason.
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
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Add TJA1120 driver structure and report 1G speed.
Signed-off-by: "Radu Pirea (NXP OSS)" <radu-nicolae.pirea@oss.nxp.com>
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Rename nxp_c45_tja11xx structure to nxp_c45_tja1103. The driver will
support more PHYs and nxp_c45_tja11xx is too generic.
Signed-off-by: "Radu Pirea (NXP OSS)" <radu-nicolae.pirea@oss.nxp.com>
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Read PHY speed from hardware instead of assuming 100Mbps by default.
The TJA1103 works only at 100Mbps, but the driver will support more PHYs.
Signed-off-by: "Radu Pirea (NXP OSS)" <radu-nicolae.pirea@oss.nxp.com>
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Use a local definition for the PHY features. PHY_100BT1_FEATURES are
not defined using the 100BaseT1 bit, so keep this workaround in the driver.
Signed-off-by: "Radu Pirea (NXP OSS)" <radu-nicolae.pirea@oss.nxp.com>
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A number of assorted fixes
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https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Add board: rv1126 Sonoff iHost board
- rv1126 ddr4 support;
- Enable BOOTSTD_FULL for RK3399 and RK3588;
- rk3036 spl stack addr fix;
- dts sync from linux v6.8-rc1 for rk356x, rk3588, rv1126;
- Enable eMMC HS200 mode by default for rk3568 and rk3588;
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This error path should return -EINVAL instead of success.
Fixes: e261fbf34785 ("blk: host_dev: Sanity check on the size of host backing file")
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
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Add a comment to explain the code under is_secure condition of
ti_sci_do_xfer. This will help avoid confusion amongst people who may in
future touch upon this code.
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
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The ti_sci driver in U-Boot has support for secure_msg as part of it's
do_xfer function. This let's U-boot send secure messages during boot up.
The protocol to send such secure messages is described as part of the
struct ti_sci_secure_msg_hdr. As part of this, there are 2 fields for
checksum and reserved that occupy the first 4 bytes of any secure
message. This is called as the secure_hdr.
As of now, the secure_hdr needs to be 0 init-ed before sending secure
messages. However the existing code was never putting the zero-inited vars
into the secure_buf, leading to possibility of the first 4 bytes of
secure_buf being possibly garbage.
Fix this by initialising the secure_hdr itself to the secure_buf
location, thus when we make secure_hdr members 0, it automatically ensures
the first 4 bytes of secure_buf are 0.
Fixes: 32cd25128bd849 ("firmware: Add basic support for TI System Control Interface (TI SCI)")
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
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Use ring_idx to pair rings. ring_idx will be same as tx flow_id for all
non-negative flow_ids. For negative flow_ids, ring_idx will be tchan->id
added with bchan_cnt.
Link: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/dma/ti/k3-udma.c?h=v6.8-rc2#n1686
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
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https://source.denx.de/u-boot/custodians/u-boot-raspberrypi
Add RaspberryPi5 basic support.
Acked-by: Peter Robinson <pbrobinson@gmail.com>
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Testing has shown that writing to eMMC using HS400 modes on RK3568
result in an ERROR.
Change the tap number for transmit clock to fix this.
Also stop DLL when config_dll() is called to disable DLL.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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Add support for ddr4 on rv1126. Timing detection files are imported
from downstream Rockchip BSP u-boot. Allow selecting ddr4 ram with
define CONFIG_RAM_ROCKCHIP_DDR4.
Signed-off-by: Tim Lunn <tim@feathertop.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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Some ethernet PHY require being reset before a phy-id can be read back
on the MDIO bus. This can result in the following message being show
on e.g. a Radxa ROCK Pi E v1.21 with a RTL8211F ethernet PHY.
Could not get PHY for ethernet@ff540000: addr -1
Add support to designware ethernet driver to reset eth phy by calling
the eth phy uclass function eth_phy_set_mdio_bus(). The call use NULL
as bus parameter to not set a shared mdio bus reference that would be
freed when probe fails. Also add a eth_phy_get_addr() call to try and
get the phy addr from DT when DM_MDIO is disabled.
This help fix ethernet on Radxa ROCK Pi E v1.21:
=> mdio list
ethernet@ff540000:
1 - RealTek RTL8211F <--> ethernet@ff540000
Reported-by: Trevor Woerner <twoerner@gmail.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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In the SMBIOS 3 entry point the Structure Table Maximum Size field was
incorrectly named max_struct_size. A Maximum Structure Size field only
exists in the SMBIOS 2.1 entry point and has a different meaning.
Call the Structure Table Length field table_maximum_size.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
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For RISC-V CPUs the SMBIOS Processor ID field contains
the Machine Vendor ID from CSR mvendorid.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
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This patch adds an implementation of the Andes watchdog ATCWDT200 driver.
Signed-off-by: CL Wang <cl634@andestech.com>
Signed-off-by: Randolph <randolph@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
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https://source.denx.de/u-boot/custodians/u-boot-at91
First set of u-boot-at91 features for the 2024.04 cycle:
This set includes some DT alignments and solves a compile issue for
custom nand defconfigs.
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This ports the pad drive strength register configuration which can be
already found in the Linux driver for this PHY.
Signed-off-by: Lukasz Tekieli <tekieli.lukasz@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
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Make sure that core SDHCI accessors are used and add
device specific card detection initialization, which
is borrowed from vendor Linux driver code.
Tested-by: Jens Maus <mail@jens-maus.de>
Tested-by: Darko Alavanja <darko.alavanja@konsulko.com>
Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
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brcm,bcm2708-fb device provided by firmware on RPi5 uses
16 bits per pixel, so lets calculate framebuffer bytes
per pixel dynamically based on queried information.
Tested to work for RPi2b v1.2, RPi3b v1.3, RPi4b v1.1,
RPi2 Zero W, RPi5b v1.0.
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Tested-by: Jens Maus <mail@jens-maus.de>
Tested-by: Darko Alavanja <darko.alavanja@konsulko.com>
Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
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Existing gpio-gate-clock driver acts like a simple GPIO switch without any
effect on gated clock. Add actual clock actions into enable/disable ops and
implement get_rate op by passing gated clock if it is enabled.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20240110160956.4476-2-clamor95@gmail.com
[ sorted includes ]
Signed-off-by: Sean Anderson <seanga2@gmail.com>
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This function is a no-op. Remove it.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20231216193843.2463779-3-seanga2@gmail.com
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Nothing uses this function. Remove it. Since clk_free no longer does
anything, just stub it out.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20231216193843.2463779-2-seanga2@gmail.com
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