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2021-09-22phy: sun50i-usb3: Add a driver for the H6 USB3 PHYSamuel Holland
This driver is needed for XHCI to work on the Allwinner H6 SoC. The driver is copied from Linux v5.10. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-09-20wdt: dw: Fix passing NULL pointer to reset functionsSean Anderson
reset_*_bulk expects a real pointer. Fixes: 4f7abafe1c ("driver: watchdog: reset watchdog in designware_wdt_stop() function") Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2021-09-17clk: ti: k3: Update driver to account for divider flagsSuman Anna
The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-09-17clk: ti: k3-pll: Change DIV_CTRL programming to read-modify-writeDave Gerlach
There are three different divider values in the DIV_CTRL register controlled by the k3-pll driver. Currently the ti_pll_clk_set_rate function writes the entire register when programming plld, even though plld only resides in the lower 6 bits. Change the plld programming to read-modify-write to only affect the relevant bits for plld and to preserve the other two divider values present in the upper 16 bits, otherwise they will always get set to zero when programming plld. Fixes: 0aa2930ca192 ("clk: add support for TI K3 SoC PLL") Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-09-14pinctrl: fix typoYuan Fang
fix typo in pinctrl Kconfig file to avoid git commit failure on some commit hooks check. Signed-off-by: Yuan Fang <fangyuanseu@gmail.com>
2021-09-13Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini
- a fix for U-Boot 2021.10 to bring back MMC boot on older boards.
2021-09-14sunxi: mmc: A20: Fix MMC optimisationAndre Przywara
Some SoCs (as seen on A20) seem to misreport the MMC FIFO level if the FIFO is completely full: the level size reads as zero, but the FIFO_FULL bit is set. We won't do a single iteration of the read loop in this case, so will be stuck forever. Check for this situation and use a safe minimal FIFO size instead when we hit this case. This fixes MMC boot on A20 devices after the MMC FIFO optimisation (9faae5457f52). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-09-13pci: Drop DM_PCISimon Glass
This option has not effect now. Drop it, using PCI instead where needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-13pci: Drop PCI_INDIRECT_BRIDGESimon Glass
This does not work with driver model so can be removed. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-13net: Drop DM_PCI check from designware driverSimon Glass
We don't need this check anymore since when PCI is enabled, driver model is always used. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-13pci: acpi: Drop DM_PCI check from ahciSimon Glass
We don't need these checks anymore since when PCI is enabled, driver model is always used. Drop them. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-13Merge tag 'mmc-2021-9-13' of https://source.denx.de/u-boot/custodians/u-boot-mmcTom Rini
Support using mmc command for enumerating mmc card in a given mode Fix device_remove in mmc Fix switch issue with send_status disabled Drop 1ms delay in fsl_esdhc command sending Revert "mmc: sdhci: set to INT_DATA_END when there are data"
2021-09-13mmc: fsl_esdhc: remove 1ms sleep in esdhc_send_cmd_common()Michael Walle
Since the beginning of this driver which was initially for the MPC8379 and MPC8536 SoCs, there is this spurious 1ms delay. According to the comment it should actually be only 8 clock cycles. Esp. during EFI block transfers, this 1ms add up to a significant delay and slows down EFI boot. I couldn't find any mention in the MPC8536 that there should be a delay of 8 clock cycles between commands. The SD card specification mentions that the clock has to be left enabled for 8 cycles after a command or response. But I don't see how this delay will help with this. Go ahead and just remove it. If there will ever be any regression we can introduce a compile time flag, but for now I'd like to keep it simple. In the split off imx driver this delay was also removed in commit 9098682200e6 ("mmc: fsl_esdhc_imx: remove the 1ms delay before sending command"). Signed-off-by: Michael Walle <michael@walle.cc>
2021-09-10mmc: fix device_remove when HS400_ES is enabledYe Li
HS400_ES is missed when down grade to HS mode during device_remove the mmc device Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-09-10mmc: fix switch issue with send_status disabledYe Li
When send_status is false or wait_dat0 is not supported, the switch function should not send CMD13 but directly return. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-09-10mmc: Add support for enumerating MMC card in a given mode using mmc commandAswath Govindraju
Add support for enumerating MMC card in a given mode using mmc rescan and mmc dev commands. The speed mode is provided as the last argument in these commands and is indicated using the index from enum bus_mode in include/mmc.h. A speed mode can be set only if it has already been enabled in the device tree. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-09-10Revert "mmc: sdhci: set to INT_DATA_END when there are data"Yuezhang.Mo@sony.com
This reverts commit 17ea3c862865c0d704646f67dbf8412f9ff54f59. In eMMC specification, for the response-with-busy(R1b, R5b) command, the DAT0 will driven to LOW as BUSY status, and in sdhci specification, the transfer complete bit should be wait for BUSY status de-assert. All response-with-busy commands don't contain data, the data judgement is no need. Signed-off-by: Yuezhang.Mo <Yuezhang.Mo@sony.com> Reviewed-by: Andy Wu <Andy.Wu@sony.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-09-10arm: a37xx: pci: Don't spam about PIO Response StatusMarek Behún
Use dev_dbg() instead of dev_err() in pcie_advk_check_pio_status(). For example CRS is not an error status, it just says that the request should be retried. Without this, U-Boot spams the terminal with pcie_advk pcie@d0070000: Non-posted PIO Response Status: UR, 0xc80 @ 0x100000 pcie_advk pcie@d0070000: Non-posted PIO Response Status: UR, 0xc80 @ 0x108000 pcie_advk pcie@d0070000: Non-posted PIO Response Status: UR, 0xc80 @ 0x110000 pcie_advk pcie@d0070000: Non-posted PIO Response Status: UR, 0xc80 @ 0x120000 pcie_advk pcie@d0070000: Non-posted PIO Response Status: UR, 0xc80 @ 0x128000 pcie_advk pcie@d0070000: Non-posted PIO Response Status: UR, 0xc80 @ 0x130000 ... when a device is not connected to a PCIe switch (Unsupported Request from the switch). Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-09-10arm: mvebu : sata_mv should probe all portsTony Dinh
While a board could have multiple SATA ports, some of the ports might not have a disk attached to them. So while probing for disks, sata_mv_probe() should continue probing all ports, and skip one with no disk attached. Tests with: - Seagate Goflex Net (Marvell Kirkwood 88F6281) out-of-tree u-boot. - Zyxel NSA325 (Marvell Kirkwood 88F6282 out-of-tree u-boot. Observation: If a board has 2 or more SATA ports, and there is only one disk attached to one of the ports, sata_mv_probe() does not return a successful probe status. And if only one disk is attached to the 2nd port (i.e. port 1), it is not probed at all. Patch Description: Let sata_mv_probe() continues probing all ports, even if there is error in probing a given port, and then return a successful status if there is at least one port was probed successfully. Signed-off-by: Tony Dinh <mibodhi@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2021-09-10arm: a37xx: pci: Implement re-issuing config requests on CRS responsePali Rohár
According to PCIe base specification, if CRS Software Visibility is not enabled, the Root Complex must re-issue the Configuration Request as a new Request. Normally this part of Root Complex is implemented in hardware but aardvark is somehow special and does not implement it in hardware and expect that handling of config requests are fully implemented in software. This re-issuing functionality is required also because U-Boot does not support CRS Software Visibility feature and therefore expects that Root Complex re-issues requests as is specified in PCIe base specification. Retry / re-issue config request up to the PIO_MAX_RETRIES, to prevent infinite loop. After retry count exceed PIO_MAX_RETRIES, returns failure. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-09-10arm: a37xx: pci: Disable returning CRS responsePali Rohár
There was mistake in commit 4cd61c43fd51 ("arm: a37xx: pci: Fix handling PIO config error responses"). U-Boot does not support handling of CRS return value for PCI_VENDOR_ID config read request and also does not set CRSSVE bit. Therefore disable returning CRS response for now. Signed-off-by: Pali Rohár <pali@kernel.org> Fixes: 4cd61c43fd51 ("arm: a37xx: pci: Fix handling PIO config error responses") Reviewed-by: Stefan Roese <sr@denx.de>
2021-09-08image: Drop if/elseif hash selection in calculate_hash()Alexandru Gagniuc
calculate_hash() would try to select the appropriate hashing function by a if/elseif contruct. But that is exactly why hash_lookup_algo() exists, so use it instead. This does mean that we now have to 'select HASH' to make sure we get the hash_lookup_algo() symbol. However, the change makes sense because even basic FITs will have to deal with "hash" nodes. My only concern is that the 'select SPL_HASH' might cause some platform to grow above its SPL size allowance Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> [trini: Make FSL_CAAM be implied only on ARM && SPL] Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-07cache: add sifive composable cache driverZong Li
This driver is currently responsible for enabling all ccache ways. Composable cache could be configure as RAM or cache, we will use it as RAM at the beginning to put the u-boot SPL there. In u-boot proper phrase, we will use the composable cache as cache, and try to enable the cache ways. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-09-07riscv: Add missing sentinel in ocores_i2c.cThomas Skibo
The ocores_i2c.c driver is missing a sentinel at the end of the compatible strings list. This causes the "dm compat" command to spew garbage. Signed-off-by: Thomas Skibo <thomas-git@skibo.net> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-09-03spi: zynqmp_gqspi: Fix dma alignment issueAshok Reddy Soma
DMA is aligned to ARCH_DMA_MINALIGN(64 bytes), but as per spec, alignment required is 4bytes only. Change DMA alignment from ARCH_DMA_MINALIGN to GQSPI_DMA_ALIGN. Remove alignment of data length in non-exponential case. Some minor improvements in the initialization to initialize gen_fifo threshold and disable qspi controller while setting config register. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-09-03spi: zynqmp_gqspi: Switch genfifo start to manual modeAshok Reddy Soma
Current implementation uses auto mode for starting generic FIFO. The recommendation from IP designers is to use manual mode, hence change to manual start mode. In fill genfifo first write to genfio and then trigger manual start. Also enable and check for genfifo empty interrupt status in place of genfifo not full interrupt. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-27Merge tag 'xilinx-for-v2021.10-rc3' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2021.10-rc3 xilinx: - Disable CONFIG_ARCH_FIXUP_FDT_MEMORY - Print information about cpu via soc drivers and enable DISPLAY_CPUINFO - Wire infrastructure for DTB_RESELECT and MULTI_DTB_FIT zynq: - Wire single QSPI - Use power-source instead of io-standard properties - Enable nor on zc770-xm012 zynqmp: - Change handling around multi_boot() - Setup offset for u-boot.itb in spi - Generate run time dfu_alt_info for capsule update - Use explicit values for enums (zynqmp_firmware.h) - Enable RTC/SHA1/BUTTON/BUTTON_GPIO command - Disable WDT driver by default - Bind usb/scsi via preboot because of EFI - DT updates/fixes - Add soc driver - Fix SPL SPI boot mode versal: - Add soc driver sdhci: - Update tap delay programming for zynq_sdhci driver cmd: - Fix RTC uclass handling in date command - Update pwm help message - Update reset help message watchdog: - Fix wwdt compilation rtc: - Deal with seq alias in rtc uclass - Add zynqmp RTC driver fdt: - Add kernel-doc for fdt_fixup_memory_banks()
2021-08-26watchdog: versal: Include header file needed for dev_ functionsAshok Reddy Soma
dev_dbg, dev_err and dev_warn seems to be moved to different header file. Include dm/device_compat.h file to compile properly. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26soc: xilinx: versal: Add soc_xilinx_versal driverT Karthik Reddy
soc_xilinx_versal driver allows identification of family & revision of versal SoC. This driver is selected by CONFIG_SOC_XILINX_VERSAL. Probe this driver using platdata U_BOOT_DEVICE structure which is defined at mach-versal/cpu.c. Add this config to xilinx_versal_virt_defconfig & xilinx_versal_mini_ospi_defconfig file to select this driver. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26soc: xilinx: zynqmp: Add soc_xilinx_zynqmp driverT Karthik Reddy
soc_xilinx_zynqmp driver allows identification of family & revision of zynqmp SoC. This driver is selected by CONFIG_SOC_XILINX_ZYNQMP. Add this config to xilinx_zynqmp_virt_defconfig file. Probe this driver using platdata U_BOOT_DEVICE structure which is specified in mach-zynqmp/cpu.c. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26mmc: zynq_sdhci: Use set_control_reg from sdhci.cAshok Reddy Soma
Since set_control_reg is available in sdhci.c, use it and remove arasan_sdhci_set_control_reg(). Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26mmc: zynq_sdhci: Wait till sd card detect state is stableT Karthik Reddy
As per SD spec when SD host controller is reset, it takes 1000msec to detect the card state. In case, if we enable the sd bus voltage & card detect state is not stable, then host controller will disable the sd bus voltage. In case of warm/subsystem reboot, due to unstable card detect state host controller is disabling the sd bus voltage to sd card causing sd card timeout error. So we wait for a maximum of 1000msec to get the card detect state stable before we enable the sd bus voltage. This current fix is workaround for now, this needs to be analysed further. Zynqmp platform should behave the same as Versal, but we did not encounter this issue as of now. So we are fixing it for Versal only. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26mmc: zynq_sdhci: Move setting tapdelay code to driverAshok Reddy Soma
Move tapdelay function calls to zynq_sdhci.c and make them static inline. zynqmp_tap_delay.h has function prototypes for the functions defined in tap_delays.c, which will not be needed anymore. Remove tap_delays.c and zynqmp_tap_delay.h files. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-08-26mmc: zynq_sdhci: Add xilinx_pm_request() method to set tapdelaysAshok Reddy Soma
Currently xilinx sdhci driver is using zynqmp_mmio_write() to set tapdelay values and DLL resets. Continue to use this for SPL and mini U-Boot where U-Boot will be executed at EL3 level. Use firmware call xilinx_pm_request() using appropriate arguments to set input/output tapdelays and also for DLL resets in regular flow(EL2). Host driver should explicitly request DLL reset before ITAP (assert DLL) and after OTAP (release DLL) to avoid issues in some cases. Also handle error return where possible. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-08-25ddr: altera: Add SDRAM driver for Intel N5X deviceTien Fong Chee
The DDR subsystem in Diamond Mesa is consisted of controller, PHY, memory reset manager and memory clock manager. Configuration settings of controller, PHY and memory reset manager is come from DDR handoff data in bitstream, which contain the register base addresses and user settings from tool. Configuration settings of memory clock manager is come from the HPS handoff data in bitstream, however the register base address is defined in device tree. The calibration is fully done in HPS, which requires IMEM and DMEM binaries loading to PHY SRAM for running this calibration, both IMEM and DMEM binaries are also part of bitstream, this bitstream would be loaded to OCRAM by SDM, and configured by DDR driver. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-08-25ddr: socfpga: Enable memory test on memory size less than 1GBTien Fong Chee
Minimum 1GB memory size is required in current memory test, so this patch improves the memory test for processing memory size less than 1GB, and the size in power of two. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-08-25drivers: clk: Add memory clock driver for Intel N5X deviceSiew Chin Lim
Add memory clock manager driver for N5X. Provides memory clock initialization and enable functions. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-25drivers: clk: Add clock driver for Intel N5X deviceSiew Chin Lim
Add clock manager driver for N5X. Provides clock initialization and get_rate functions. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-23Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini
fsl-qoriq: Fixes related to env, spi, usb, crypto, configs, distro-boot for Layerscape Boards like lx2, sl28, ls2088ardb. powerpc: Fixes for t208xrdb revd board and cortina related configs update for T208xRDB, T4240RDB.
2021-08-23Merge tag 'for-v2021.10-rc3' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-i2c i2c changes for for-v2021.10-rc3 new driver: - Introduce mcp230xx support from Sebastian Reichel new feature: - i2c-gpio: add support for "sda-gpios" + "scl-gpios" i2c-gpio bindings. from Samuel Holland - bootcount: add a new driver with syscon as backend from Nandor Han
2021-08-22bootcount: add a new driver with syscon as backendNandor Han
The driver will use a syscon regmap as backend and supports both 16 and 32 size value. The value will be stored in the CPU's endianness. Signed-off-by: Nandor Han <nandor.han@vaisala.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-22i2c: i2c-gpio: Support the named GPIO bindingSamuel Holland
To avoid confusion about the order of the GPIOs, the i2c-gpio binding was updated to use a separate property for each GPIO instead of an array. However, the driver only supports the old binding. Add support for the new binding as well, so the driver continues to work as device trees are updated. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2021-08-22gpio: mcp230xx: Introduce new driverSebastian Reichel
Introduce driver for I2C based MCP230xx GPIO chips, which are quite common and already well supported by the Linux kernel. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-22i2c: add dm_i2c_reg_clrsetSebastian Reichel
Add function to apply a bitmask to an i2c register, so that specific bits can be cleared and/or set. Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-21Fix flashing of eMMC user area with FastbootOleh Kravchenko
'gpt' and 'mmc0' fastboot partitions have been treated as the same device, but it is wrong. Fill disk_partition structure with eMMC user partition info to properly flash data. Signed-off-by: Oleh Kravchenko <oleg@kaa.org.ua> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Marek Vasut <marex@denx.de> Cc: Sean Anderson <sean.anderson@seco.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Sean Anderson <sean.anderson@seco.com>
2021-08-21Fix flash and erase of eMMC Boot2 with FastbootOleh Kravchenko
The current U-Boot version has the next matches for boot partitions: > mmc0boot0 to EMMC_BOOT1 > mmc0boot1 to EMMC_BOOT1 (should be EMMC_BOOT2) This patch fixes a typo for the boot partition number. Signed-off-by: Oleh Kravchenko <oleg@kaa.org.ua> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Sean Anderson <sean.anderson@seco.com>
2021-08-21clk: clk_versaclock: Add support for versaclock driverAdam Ford
The driver is based on the Versaclock driver from the Linux code, but due differences in the clock API between them, some pieces had to be changed. This driver creates a mux, pfd, pll, and a series of fod ouputs. Rate Usecnt Name ------------------------------------------ 25000000 0 `-- x304-clock 25000000 0 `-- clock-controller@6a.mux 25000000 0 |-- clock-controller@6a.pfd 2800000000 0 | `-- clock-controller@6a.pll 33333333 0 | |-- clock-controller@6a.fod0 33333333 0 | | `-- clock-controller@6a.out1 33333333 0 | |-- clock-controller@6a.fod1 33333333 0 | | `-- clock-controller@6a.out2 50000000 0 | |-- clock-controller@6a.fod2 50000000 0 | | `-- clock-controller@6a.out3 125000000 0 | `-- clock-controller@6a.fod3 125000000 0 | `-- clock-controller@6a.out4 25000000 0 `-- clock-controller@6a.out0_sel_i2cb A translation function is added so the references to <&versaclock X> get routed to the corresponding clock-controller@6a.outX. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Sean Anderson <sean.anderson@seco.com>
2021-08-18crypto/fsl: fix missed dma_addr_t -> caam_dma_addr_t conversionHoria Geantă
One of the "dma_addr_t" instances was left out when converting to "caam_dma_addr_t". Fixes: 2ff17d2f74c5 ("crypto: fsl: refactor for 32 bit version CAAM support on ARM64") Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-08-18net: cortina: Add support for tfa boot in cortina firmwareKuldeep Singh
Add support for boards supporting TFA boot separately in cortina firmware. Please note, a weak function is defined to retrieve firmware address values as CONFIG_CORTINA_FW_ADDR is now defined in defconfig and can only have one possible value defined. This weak function will help in overwrting the values to get proper addresses as per boot source. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-08-18configs: Migrate CORTINA_FW_ADDR and CORTINA_FW_LENGTH to KconfigKuldeep Singh
Use moveconfig.py script to convert below defines to Kconfig and move these entries to defconfigs. CONFIG_CORTINA_FW_ADDR CONFIG_CORTINA_FW_LENGTH Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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