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2021-11-17phy: cadence: phy-cadence-torrent: Change the name of subnode searchedAswath Govindraju
Search for "phy" in the subnode names, to syncup with kernel. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2021-11-17nvme: Fix error in nvme_setup_prpsJon Lin
Consulting to "NVM Express® Base Specification, revision 2.0". If more PRP List pages are required, then the last entry of the PRP List contains the Page Base Address of the next PRP List page. The next PRP List page shall be memory page aligned. Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
2021-11-17nvme: Enable FUAJon Lin
Most NVME devcies maintain data in internal cache for an uncertain times, and u-boot has no method to force NVME to flush cache. So this patch adds FUA to avoid data loss caused by power off after data programming. Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Reviewed-by: Stefan Agner <stefan@agner.ch>
2021-11-17RFC: arm: pci: Add PCI cam support to PCI-E ecam driverAlistair Delva
When booting U-Boot in crosvm, the virtual machine emulates a PCI cam device, not the PCI-E 'ecam' device normally seen on e.g. QEMU. This PCI device can be supported with only trivial changes to the ecam driver. Instead of adding a completely new driver which is identical besides the initialization step, add support for the PCI version to the existing driver. Signed-off-by: Alistair Delva <adelva@google.com> Cc: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Cc: Ram Muthiah <rammuthiah@google.com>
2021-11-17crypto: aspeed: Add AST2600 ACRY supportChia-Wei Wang
ACRY is designed to accelerate ECC/RSA digital signature generation and verification. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2021-11-17clk: ast2600: Add RSACLK control for ACRYChia-Wei Wang
Add RSACLK enable for ACRY, the HW RSA/ECC crypto engine of ASPEED AST2600 SoCs. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2021-11-17crypto: aspeed: Add AST2600 HACE supportJohnny Huang
Hash and Crypto Engine (HACE) is designed to accelerate the throughput of hash data digest, and symmetric-key encryption. Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-11-17clk: ast2600: Add YCLK control for HACEJoel Stanley
Add YCLK enable for HACE, the HW hash engine of ASPEED AST2600 SoCs. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2021-11-17mmc: mtk-sd: implement waiting for DAT0 line stateJulien Masson
With the recent changes on mmc driver, we saw that the boot is ~5 secs longer compared to v2021.07 on mediatek platforms. This regression is seen during mmc_init and caused by the following patch [1]. Indeed since we did not support poll dat0, we fulfilled the condition of [1] and a delay of 500 ms was added for every __mmc_switch call. By adding the support of wait_dat0(), we now don't need to mdelay during mmc_init anymore. [1]: https://patchwork.ozlabs.org/project/uboot/patch/1629192034-64056-1-git-send-email-ye.li@nxp.com/ Signed-off-by: Julien Masson <jmasson@baylibre.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-11-17pci: Add standard PCIe ECAM macrosPali Rohár
Lot of PCIe controllers are using ECAM addressing. So add common ECAM macros into U-Boot's pci.h header file which can be suitable for most PCI controller drivers. Replace custom ECAM address macros in every PCI controller driver by new ECAM macros from U-Boot's pci.h header file. Similar macros are defined also in Linux kernel. There is a small difference between Linux and these new U-Boot macros. U-Boot's PCIE_ECAM_OFFSET() takes device and function numbers in separate arguments. Linux's PCIE_ECAM_OFFSET() takes device and function numbers encoded in one argument. The reason is that U-Boot's PCI_DEVFN() macro is different than Linux's PCI_SLOT() macro. So having device and function numbers in separate arguments makes code more straightforward. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-17pinctrl: Add Apple pinctrl driverMark Kettenis
This driver supports both pin muxing and GPIO support for the pin control logic found on Apple SoCs. Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2021-11-17aspeed: AST2600 Pinctrl DriverRyan Chen
This driver uses Pinctrl framework and is compatible with the Linux driver for AST2600. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
2021-11-15usb: Make USB_MUSB_PIO_ONLY selected by USB_MUSB_SUNXISamuel Dionne-Riel
This ensures the USB_MUSB_PIO_ONLY config is set to an apppropriate value from the changes enabling USB_MUSB_GADGET does. Namely, USB_MUSB_PIO_ONLY default to =y on USB_MUSB_SUNXI being y. Signed-off-by: Samuel Dionne-Riel <samuel@dionne-riel.com>
2021-11-13Merge tag 'dm-pull-13nov21' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-dm env tidy-ups test fixes binman fixes and ELF enhancements
2021-11-13Merge tag 'efi-2022-01-rc2-2' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-efi Pull request for efi-2022-01-rc2-2 UEFI: * fix measurement of BootOrder variable for TCG2 protocol TPM: * TIS mmio driver. This driver supports QEMU's emulated TPM.
2021-11-13sandbox: fix sandbox_wdt_expire_now()Heinrich Schuchardt
With CONFIG_SYSRESET_WATCHDOG=y the sandbox can use a watchdog based system reset. To make this work calling sandbox_wdt_expire_now() must lead to a reset. With this change we can test the development suggested in [PATCH 0/4] Improved sysreset/watchdog uclass integration https://lists.denx.de/pipermail/u-boot/2021-August/458656.html Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-11-12Convert CONFIG_MACB to KconfigTom Rini
This converts the following to Kconfig: CONFIG_MACB Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-11rtc: ds1337: fix compatible string typoClemens Gruber
The driver supports the ds1339 as well, which was probably intended by the author but prevented by a typo. Fix the typo. Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
2021-11-11Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini
- device-tree sync-up with Linux for ls1028a - fixes/update in fsl-ddr driver, fsl-validate, lx2162a, fsl-mc, spintable code, configs, qspi node, pci - enable EFI_SET_TIME support in sl28 - powerpc: Drop -mstring
2021-11-10tpm: Use the new API on tpm2 spi driverIlias Apalodimas
Convert our SPI TPM driver and use the newly added API Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2021-11-10tpm2: Add a TPMv2 MMIO TIS driverIlias Apalodimas
Add support for devices that expose a TPMv2 though MMIO. Apart from those devices, we can use the driver in our QEMU setups and test TPM related code which is difficult to achieve using the sandbox driver (e.g test the EFI TCG2 protocol). It's worth noting that a previous patch added TPMv2 TIS core functions, which the current driver is consuming. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2021-11-10tpm2: Introduce TIS tpm coreIlias Apalodimas
There's a lot of code duplication in U-Boot right now. All the TPM TIS compatible drivers we have at the moment have their own copy of a TIS implementation. So let's create a common layer which implements the core TIS functions. Any driver added from now own, which is compatible with the TIS spec, will only have to provide the underlying bus communication mechanisms. Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2021-11-10tpm: refactor function names for LPC based TPMsIlias Apalodimas
With the upcoming TPM2 API, some of the functions name are part of the new header file. So switch conflicting internal function names and defines. Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canaonical.com> Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2021-11-10tpm: refactor function names and macros for infineon v1.2 TPMIlias Apalodimas
With the upcoming TPM2 API, some of the functions name are part of the new header file. So switch conflicting internal function names and defines. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2021-11-10Merge tag 'u-boot-stm32-20211110' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-stm - DHSOM update: - Remove nWP GPIO hog - Increase SF bus frequency to 50Mhz and enable SFDP - Disable video output for DHSOM - Disable EFI - Enable DFU_MTD support - Create include file for STM32 gpio driver private data - Split board and SOC STM32MP15 configuration - Device tree alignement with v5.15-rc6 for STM32MP15 - Add binman support for STM32MP15x - Normalise newlines for stm32prog - Update OTP shadow registers in SPL
2021-11-10stm32mp15: replace CONFIG_TFABOOT when it is possiblePatrick Delaunay
In some part of STM32MP15 support the CONFIG_TFABOOT can be replaced by other config: CONFIG_ARMV7_PSCI and CONFIG_ARM_SMCCC. This patch also simplifies the code in cpu.c, stm32mp1_ram.c and clk_stml32mp1.c as execution of U-Boot in sysram (boot without SPL and without TFA) is not supported: the associated initialization code is present only in SPL. This cleanup patch is a preliminary step to support SPL load of OP-TEE in secure world, with SPL in secure world and U-Boot in no-secure world. Reported-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-10gpio: stm32: create include file for driver private dataPatrick Delaunay
The stm32 gpio driver private data are not needed in arch include files, they are not used by code except for stm32 gpio and pincontrol drivers, using the same IP; the defines for this IP is moved in a new file "stm32_gpio_priv.h" in driver/gpio. This patch avoids to have duplicated file gpio.h for each SOC in MPU directory mach-stm32mp and in each MCU directory arch-stm32* and allows to remove CONFIG_GPIO_EXTRA_HEADER for all STM32. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-11-10Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-marvellTom Rini
- Minor kwboot improvements (Pali) - Misc kwbimage improvements (Pali) - pci_mvebu: Use global MBUS_PCI_MEM_SIZE macro (Pali)
2021-11-10pci: pci_mvebu: Use global MBUS_PCI_MEM_SIZE macroPali Rohár
Header file mach/cpu.h already defines MBUS_PCI_MEM_SIZE macro which defines size of MBUS_PCI_MEM_BASE window. So use global MBUS_PCI_MEM_SIZE macro instead of locally defined PCIE_MEM_SIZE macro. Both macros have same definition. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-10watchdog: don't autostart watchdog on Sunxi boardsHeinrich Schuchardt
The Sunxi boards only support a 16 second watchdog timeout. This is too short to boot Linux. The UEFI specification requires 300 seconds as default timeout. Change the default for CONFIG_WATCHDOG_AUTOSTART for ARCH_SUNXI. Fixes: b147bd3607f8 ("sunxi: Enable watchdog timer support by default") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Tested-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-11-09pci: layerscape: Fix the LUT and msi-map mismatch issueHou Zhiqiang
In the current code, it doesn't reset the cursors of LUT entry and StreamID at the beginning of the fixup, so it can result in LUT entry setup and msi-map mismatch and LUT entries and StreamID leaking when reload and fixup the DTB. This patch move the initialization of LUT entry and StreamID cursors to the beginning of the fixup to resolve the issues. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09configs: fsl: migrate FMAN/QE specific defines to KconfigRajesh Bhagat
Use moveconfig.py script to convert CONFIG_SYS_FMAN_FW_ADDR, CONFIG_SYS_QE_FW_ADDR and CONFIG_SYS_QE_FMAN_FW_LENGTH to Kconfig and move these entries to defconfigs. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09usb: dwc3: add layerscape supportMichael Walle
Add support for the proper dwc3 device tree binding support as specified in the offical device tree spec. Initially, add support for the LS1028A support. Other SoCs should be easy to add by just adding the corresponding compatible string. Unfortunately, the device trees of all other layerscape SoCs are not converted and uses a wrong compatible string only known in u-boot. To maintain backwards compatibility with current u-boot device trees, add the generic "fsl,layerscape-dwc3" compatible string. OTG mode is not supported yet. The dr_mode in the devicetree will either have to be set to peripheral or host. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09usb: dwc3: Enable undefined length INCR burst typeMichael Walle
[backport from linux commit d9612c2f0449e24983a8b689603210486a930c90] Enable the undefined length INCR burst type and set INCRx. Different platform may has the different burst size type. In order to get best performance, we need to tune the burst size to one special value, instead of the default value. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09usb: dwc3: Add frame length adjustment quirkMichael Walle
[backport from linux commit db2be4e9e30c6e43e48c5749d3fc74cee0a6bbb3] Add adjust_frame_length_quirk for writing to fladj register which adjusts (micro)frame length to value provided by "snps,quirk-frame-length-adjustment" property thus avoiding USB 2.0 devices to time-out over a longer run Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09usb: common: silence dubious errorsMichael Walle
Both dr_mode and maximum-speed properties are usually optional. Drivers will still try to fetch the properties nonetheless, which leads to error messages, although they are no errors. Change pr_err() to pr_debug(). Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09pci: layerscape: add official ls1028a binding supportMichael Walle
The official bindind of the PCIe controller of the ls1028a has the following compatible string: compatible = "fsl,ls1028a-pcie"; Additionally, the resource names and count are different. Update the driver to support this binding and change the entry in the ls1028a device tree. Cc: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09usb: xhci: fsl: add new compatible fsl,ls1028a-dwc3Michael Walle
The official ls1028a binding of the driver uses the following as compatibles: compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; Change the ls1028a device tree and add this new compatible to the fsl specific xhci driver, otherwise the generic dwc3 driver will be used with the compatibles above. Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Marek Vasut <marex@denx.de> Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09scsi: ceva: rename the resource name to match the linux kernel oneMichael Walle
The driver will look for a named resource "ecc-addr", but this isn't the official binding. In fact, the official device tree binding documentation doesn't mention any resource names at all. But it is safe to assume that it's the linux ones we have to use if we want to be compatible with the linux device tree. Thus rename "ecc-addr" to "sata-ecc" and convert all the users in u-boot. While at it, also rename "sata-base" to "ahci" although its not used at all. This change doesn't affect the SATA controller on the ZynqMP. Cc: Michal Simek <monstr@monstr.eu> Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09serial: lpuart: add new compatible fsl, ls1028a-lpuartMichael Walle
The official ls1028a binding of the driver uses the following as compatibles: compatible = "fsl,ls1028a-lpuart"; Add the missing compatible to the driver and update the device tree. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09spi: fsl_dspi: rename num-cs to spi-num-chipselectsMichael Walle
The official devicetree bindings specifies spi-num-chipselects as the name. Use it. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09spi: fsl_dspi: add new compatible fsl, ls1021a-v1.0-dspiMichael Walle
The official ls1028a binding of the driver uses the following as compatibles: compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; Add the missing compatible to the driver and update the device tree. We can use the fallback "fsl,ls1021a-v1.0-dspi", because the endianness is determined by the little-endian property and not by the compatible string itself. Further, we won't need and specific details on the DMA configuration (which is different on the LS1021A). If it's ever needed, we can later add the more specific "fsl,ls1028a-dspi" compatible to the driver. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09watchdog: sp805_wdt: use correct compatible stringMichael Walle
According to the linux device tree specification the compatible string is: compatible = "arm,sp805", "arm,primecell"; Fix all users in u-boot. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09drivers: ddr: lc_common_dimm_params.c : Fix Divison by zero issueManinder Singh
Adds check for memory clock variable before calculating caslat_actual. Set mclk_ps to slowest DIMM supported if mclk_ps is found zero. Signed-off-by: Maninder Singh <maninder.singh_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09drivers: net: fsl-mc: add a command which dumps the MC logCosmin-Florin Aluchenesei
Extended fsl_mc command adding an extra option dump_log Signed-off-by: Cosmin-Florin Aluchenesei <aluchenesei.cosmin-florin@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09board: fsl_validate: Fix Double free IssueKshitiz Varshney
Remove Double free issue from calc_img_key_hash() and calc_esbchdr_esbc_hash() function. Verified the secure boot changes using lx2162aqds board. Signed-off-by: Kshitiz Varshney <kshitiz.varshney@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09drivers: ddr: main.c: Fix Bad Shift operator issuePriyanka Singh
Fix Bad Shift operator issue in step_to_string function by adding an if check Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09drivers: ddr: fsl_ddr_gen4.c: Fix divide by zero issuePriyanka Singh
Fix possible divide by zero issue in fsl_ddr_set_memctl_regs by adding an if check Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09drivers: ddr: util.c: Fix divide by zero issuePriyanka Singh
Fix possible divide by zero issue in get_memory_clk_period_ps by adding a check Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09exynos78x0: pinctrl: set const to structsMinkyu Kang
to fix following checkpatch warings. WARNING: struct should normally be const Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Cc: Dzmitry Sankouski <dsankouski@gmail.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
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