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2023-10-07net: dwc_eth_qos: Add glue driver for GMAC on Rockchip RK3568Jonas Karlman
Add a new glue driver for Rockchip SoCs, i.e RK3568, with a GMAC based on Synopsys DWC Ethernet QoS IP. rk_gmac_ops was ported from linux commit: 3bb3d6b1c195 ("net: stmmac: Add RK3566/RK3568 SoC support") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-10-07net: dwc_eth_qos: Stop spam of RX packet not available messageJonas Karlman
Remove spam of RX packet not available debug messages when waiting to receive a packet. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-10-07net: dwc_eth_qos: Return error code when start failsJonas Karlman
Return error code when phy_connect fails or no link can be established. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-10-07net: dwc_eth_qos: Drop unused rx_pkt from eqos_privJonas Karlman
rx_pkt is allocated and not used for anything, remove it. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-10-07rockchip: Port IO-domain driver for RK3568 from linuxJonas Karlman
Port the Rockchip IO-domain driver for RK3568 from linux. The driver auto probe after bind to configure IO-domain based on the regulator voltage. Compared to the linux driver this driver is not notified about regulator voltage changes and only configure IO-domain based on the initial voltage autoset by the regulator. It is not recommended to enable MMC_IO_VOLTAGE or the mmc signal voltage and IO-domain may end up out of sync. Based on the linux commit 28b05a64e47c ("soc: rockchip: io-domain: add rk3568 support"). Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-07regulator: rk8xx: Return correct voltage for switchout convertersshengfei Xu
The voltage value for switchout converters is always reported as 0 uV. When the switch is enabled, it's voltage is same as input supply. Fix this by implementing get_value for switchout converters. Fixes: ee30068fa574 ("power: pmic: rk809: support rk809 pmic") Signed-off-by: shengfei Xu <xsf@rock-chips.com> [jonas@kwiboo.se: fix checkpatch error, update commit message] Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-07regulator: rk8xx: Return correct voltage for buck convertersJoseph Chen
Information from the first range group is always used to calculate the voltage returned for buck converters. This may result in wrong voltage reported back to the regulator_get_value caller. Traverse all the possible BUCK ranges to fix this issue. Fixes: addd062beacc ("power: pmic: rk816: support rk816 pmic") Fixes: b62280745e55 ("power: pmic: rk805: support rk805 pmic") Fixes: b4a35574b38d ("power: pmic: rk817: support rk817 pmic") Fixes: ee30068fa574 ("power: pmic: rk809: support rk809 pmic") Signed-off-by: Joseph Chen <chenjh@rock-chips.com> [jonas@kwiboo.se: fix checkpatch error, simplify buck get_value, update commit message] Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-07power: regulator: Only run autoset once for each regulatorJonas Karlman
With the commit 4fcba5d556b4 ("regulator: implement basic reference counter"), keeping regulator enablement in balance become more important. Calling regulator_autoset multiple times on a fixed regulator increase the enable count for each call, resulting in an unbalanced enable count. Introduce a AUTOSET_DONE flag and use it to mark that autoset has run for the regulator. Return -EALREADY on any subsequent call to autoset. This fixes so that the enable count is only ever increased by one per regulator for autoset. Fixes: 4fcba5d556b4 ("regulator: implement basic reference counter") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-07phy: rockchip: naneng-combphy: Use signal from comb PHY on RK3588Jonas Karlman
Route signal from comb PHY instead of PCIe3 PHY to PCIe1l0 and PCIe1l1. Fixes use of pcie2x1l0 on ROCK 5B. Code imported from mainline linux driver. Fixes: c5b4a012bca8 ("phy: rockchip: naneng-combphy: Support rk3588") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-07phy: rockchip: snps-pcie3: Add support for RK3588Jonas Karlman
Add support for the RK3588 variant to the driver. Code imported almost 1:1 from mainline linux driver. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-07phy: rockchip: snps-pcie3: Add bifurcation support for RK3568Jonas Karlman
Configure aggregation or bifurcation mode on RK3568 based on the value of data-lanes property. Code imported almost 1:1 from mainline linux driver. Fixes: 6ec62b6ca698 ("phy: rockchip: Add Rockchip Synopsys PCIe 3.0 PHY") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-07phy: rockchip: snps-pcie3: Refactor to use a phy_init opsJonas Karlman
Add a phy_init ops in preparation for upcoming support of a RK3588 variant in the driver. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-07phy: rockchip: snps-pcie3: Refactor to use clk_bulk APIJonas Karlman
Change to use clk_bulk API and syscon_regmap_lookup_by_phandle to simplify in preparation for upcoming support of a RK3588 variant. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-07pci: pcie_dw_rockchip: Configure number of lanes and link width speedJonas Karlman
Set number of lanes and link width speed control register based on the num-lanes property. Code imported almost 1:1 from dw_pcie_setup in mainline linux. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-05Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini
+ ae350: modify memory layout and target name + ae350: use generic RISC-V timer driver in S-mode + Support bootstage report for RISC-V + Support C extension exception command for RISC-V + Add Starfive timer support
2023-10-05Merge branch '2023-10-04-TI-dts-updates'Tom Rini
- Resync some TI K3 DTS files, to fix booting on them.
2023-10-04Merge tag 'dm-pull-4oct23' of https://source.denx.de/u-boot/custodians/u-boot-dmTom Rini
moveconfig: enhance output; rename to qconfig
2023-10-04drivers: firmware: ti_sci: Get SCI revision only if TIFS/SYSFW is upNeha Malcom Francis
When setting up boot media to load the TIFS binary in legacy boot flow (followed by J721E), get_timer() is called which calls dm_timer_init() which then gets the tick-timer: mcu_timer0. mcu_timer0 uses k3_clks (clock controller) and k3_pds (power controller) from the dmsc node that forces probe of the ti_sci driver of TIFS that hasn't been loaded yet! Running ti_sci_cmd_get_revision from the probe leads to panic since no TIFS and board config binaries have been loaded yet. Resolve this by moving ti_sci_cmd_get_revision to ti_sci_get_handle_from_sysfw as a common point of invocation for both legacy and combined boot flows. Before doing this, it is important to go through whether any sync points exist where revision is needed before ti_sci_get_handle_from_sysfw is invoked. Going through the code along with boot tests on both flows ensures that there are none. Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2023-10-04dm: core: Adjust dump-sorting to get stats only when neededSimon Glass
If we are not sorting the tree we don't need to get the stats. Adjust the code to avoid the wasted time. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-10-04Merge tag 'u-boot-stm32-20231004' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-stm STM32 MCU: _ alignment with kernel DT v6.5 for stm32f429 and stm32f746 _ rework way of displaying ST logo for stm32f746-disco and stm32f769-disco STM32 MPU: _ alignment with kernel DT v6.6-rc1 _ add RNG support for stm32mp13 _ add USB, USB boot and stm32prog command support for stm32mp13 _ add support of USART1 clock for stm32mp1 _ only print RAM and board code with SPL_DISPLAY_PRINT flag for stm32mp1 _ rename update_sf to dh_update_sd_to_sf and add dh_update_sd_to_emmc for stm32mp15xx DHCOR [ Fix merge conflict at board/st/common/stm32mp_dfu.c ] Signed-off-by: Tom Rini <trini@konsulko.com>
2023-10-04clk: stm32mp1: Add support for USART1 clockAnatolij Gustschin
Add USART1 clock parents and mux configuration. This allows support for configuring the USART1 as the serial console in SPL and U-Boot via device tree. Without this patch the SPL with usart1 serial console enabled crashes because it can not find the clock specified in the device tree for usart1. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-10-04ram: stm32mp1: Only print RAM config with CONFIG_SPL_DISPLAY_PRINTHarald Seiler
Ensure that the RAM configuration line is only printed when CONFIG_SPL_DISPLAY_PRINT is set. Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-10-04rng: stm32: Implement custom RNG configuration supportGatien Chevallier
STM32 RNG configuration should best fit the requirements of the platform. Therefore, put a platform-specific RNG configuration field in the platform data. Default RNG configuration for STM32MP13 is the NIST certified configuration [1]. While there, fix and the RNG init sequence to support all RNG versions. [1] https://csrc.nist.gov/projects/cryptographic-module-validation-program/entropy-validations/certificate/53 Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-10-04rng: stm32: add error concealment sequenceGatien Chevallier
Seed errors can occur when using the hardware RNG. Implement the sequences to handle them. This avoids irrecoverable RNG state. Try to conceal seed errors when possible. If, despite the error concealing tries, a seed error is still present, then return an error. A clock error does not compromise the hardware block and data can still be read from RNG_DR. Just warn that the RNG clock is too slow and clear RNG_SR. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-10-04rng: stm32: add RNG clock frequency restraintGatien Chevallier
In order to ensure a good RNG quality and compatibility with certified RNG configuration, add RNG clock frequency restraint. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-10-04rng: stm32: Implement configurable RNG clock error detectionGatien Chevallier
RNG clock error detection is now enabled if the "clock-error-detect" property is set in the device tree. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-10-04rng: stm32: rename STM32 RNG driverGatien Chevallier
Rename the RNG driver as it is usable by other STM32 platforms than the STM32MP1x ones. Rename CONFIG_RNG_STM32MP1 to CONFIG_RNG_STM32 Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Grzegorz Szymaszek <gszymaszek@short.pl> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-10-04riscv: andesv5: Prefer using the generic RISC-V timer driver in S-modeYu Chien Peter Lin
The Andes PLMT driver directly accesses the mtime MMIO region, indicating its intended use in the M-mode boot stage. However, since U-Boot proper (S-mode) also uses the PLMT driver, we need to specifically mark the region as readable through PMPCFGx (or S/U-mode read-only shared data region for Smepmp) in OpenSBI. Granting permission for this case doesn't make sense. Instead, we should use the generic RISC-V timer driver to read the mtime through the TIME CSR. Therefore, we add the SPL_ANDES_PLMT_TIMER config, which ensures that the PLMT driver is linked exclusively against M-mode U-Boot or U-Boot SPL binaries. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Samuel Holland <samuel@sholland.org>
2023-10-04timer: starfive: Add Starfive timer supportKuan Lim Lee
Add timer driver in Starfive SoC. It is an timer that outside of CPU core and inside Starfive SoC. Signed-off-by: Kuan Lim Lee <kuanlim.lee@starfivetech.com> Reviewed-by: Wei Liang Lim <weiliang.lim@starfivetech.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-04timer: riscv_aclint_timer: add timer_get_boot_us for BOOTSTAGEChanho Park
timer_get_boot_us function is required to record the boot stages as us-based timestamp. To get a micro-second time from a timer tick, this converts the formula like below to avoid zero result of (tick / rate) part. From: time(us) = (tick / rate) * 1000000 To : time(us) = (tick * 1000) / (rate / 1000) Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-10-04riscv: timer: add timer_get_boot_us for BOOTSTAGEChanho Park
timer_get_boot_us function is required to record the boot stages as us-based timestamp. To get a micro-second time from a timer tick, this converts the formula like below to avoid zero result of (tick / rate) part. From: time(us) = (tick / rate) * 1000000 To : time(us) = (tick * 1000) / (rate / 1000) Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-10-02Merge branch 'next_pinctrl_sync' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-sh - pinctrl re-sync for Renesas chips
2023-10-02Merge branch 'next'Tom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-10-01clk: renesas: Synchronize R8A774E1 RZ/G2H clock tables with Linux 6.5.3Marek Vasut
Synchronize R8A774E1 RZ/G2H clock tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-01clk: renesas: Synchronize R8A774C0 RZ/G2E clock tables with Linux 6.5.3Marek Vasut
Synchronize R8A774C0 RZ/G2E clock tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-01clk: renesas: Synchronize R8A774B1 RZ/G2N clock tables with Linux 6.5.3Marek Vasut
Synchronize R8A774B1 RZ/G2N clock tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-01clk: renesas: Synchronize R8A774A1 RZ/G2M clock tables with Linux 6.5.3Marek Vasut
Synchronize R8A774A1 RZ/G2M clock tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-01clk: renesas: Synchronize R8A779G0 V4H clock tables with Linux 6.5.3Marek Vasut
Synchronize R-Car R8A779G0 V4H clock tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . The PLL2_VAR is not implemented yet and PLL2 is still configured as regular PLL2 only. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-01clk: renesas: Synchronize R8A779F0 S4 clock tables with Linux 6.5.3Marek Vasut
Synchronize R-Car R8A779F0 S4 clock tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-01clk: renesas: Synchronize R8A779A0 V3U clock tables with Linux 6.5.3Marek Vasut
Synchronize R-Car R8A779A0 V3U clock tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-01clk: renesas: Synchronize R8A77995 D3 clock tables with Linux 6.5.3Marek Vasut
Synchronize R-Car R8A77995 D3 clock tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-01clk: renesas: Synchronize R8A77990 E3 clock tables with Linux 6.5.3Marek Vasut
Synchronize R-Car R8A77990 E3 clock tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-01clk: renesas: Synchronize R8A77980 V3H clock tables with Linux 6.5.3Marek Vasut
Synchronize R-Car R8A77980 V3H clock tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-01clk: renesas: Synchronize R8A77970 V3M clock tables with Linux 6.5.3Marek Vasut
Synchronize R-Car R8A77970 V3M clock tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-01clk: renesas: Synchronize R8A77965 M3-N clock tables with Linux 6.5.3Marek Vasut
Synchronize R-Car R8A77965 M3-N clock tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-01clk: renesas: Synchronize R8A77960 M3-W and R8A77961 M3-W+ clock tables with ↵Marek Vasut
Linux 6.5.3 Synchronize R-Car R8A77960 M3-W and R8A77961 M3-W+ clock tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-01clk: renesas: Synchronize R8A77951 H3 clock tables with Linux 6.5.3Marek Vasut
Synchronize R-Car R8A77951 H3 clock tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-01clk: renesas: Synchronize R8A7794 E2 clock tables with Linux 6.5.3Marek Vasut
Synchronize R-Car R8A7794 E2 clock tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-01clk: renesas: Synchronize R8A7792 V2H clock tables with Linux 6.5.3Marek Vasut
Synchronize R-Car R8A7792 V2H clock tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-01clk: renesas: Synchronize R8A7791 M2-W and R8A7793 M2-N clock tables with ↵Marek Vasut
Linux 6.5.3 Synchronize R-Car R8A7791 M2-W and R8A7793 M2-N clock tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-01 18:15:58 +0000