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2022-09-29dm: core: Drop the const from ofnodeSimon Glass
Now that we support writing to ofnodes, the const is not accurate. Drop it to avoid undesirable casting. Also drop the ofnode_to_npw() which is now the same as ofnode_to_np(). Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29dm: core: Support writing a property to an empty nodeSimon Glass
At present this does not work with livetree. Fix it and add a test. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29dm: core: Allow adding ofnode subnodesSimon Glass
Add this feature to the ofnode interface, supporting both livetree and flattree. If the node exists it is returned, along with a -EEXIST error. Update the functions it calls to handle this too. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29dm: core: Pass a root node to of_find_node_by_phandle()Simon Glass
This function currently assumes that the control FDT is used. Update it to allow a root node to be passed, so it can work with any tree. Also add a comment to ofnode_get_by_phandle() so that its purpose is clear. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29sandbox: power: Update PMIC driver to use logSimon Glass
Use the log functions instead of pr_...() so we can avoid using __func__. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-09-29treewide: Drop image_header_t typedefSimon Glass
This is not needed and we should avoid typedefs. Use the struct instead and rename it to indicate that it really is a legacy struct. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-26Merge tag 'xilinx-for-v2023.01-rc1-v2' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2023.01-rc1 (round 2) xilinx: - Add support for new Versal NET SOC zynqmp: - Use mdio bus for ethernet phy description - Wire ethernet phy reset via i2c-gpio versal: - Config cleanup
2022-09-26Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv ↵Tom Rini
into next
2022-09-26reset: zynqmp: Enable reset driver for Versal NETJay Buddhabhatti
Enable zynqmp reset driver for Versal NET. Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/c8c26618f87d8451c6ffa9487809a24718bff6a7.1663589964.git.michal.simek@amd.com
2022-09-26mailbox: zynqmp: Enable ipi mailbox driver for Versal NETJay Buddhabhatti
Enable mailbox configs for Versal NET. Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/b3a9a6a58b74d17e2ec5f60617fa42062fbab951.1663589964.git.michal.simek@amd.com
2022-09-26firmware: zynqmp: Add Versal NET compatible stringJay Buddhabhatti
Add compatible string for Versal NET. Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/ec73f786e1c89094752ff3693f6f0fb4536c85c5.1663589964.git.michal.simek@amd.com
2022-09-26clk: versal: Enable clock driver for Versal NETJay Buddhabhatti
Add support for Versal NET compatible string in clock driver. Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20a35d0c1ffcc222fbe93dd406cdd0aff92f5223.1663589964.git.michal.simek@amd.com
2022-09-26spi: zynqmp_gqspi: Add support for Versal NETMichal Simek
Add support for Versal NET platform. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/f374e9a81f2d85de1240029f3ba5f6423cfa0680.1663589964.git.michal.simek@amd.com
2022-09-26spi: cadence_qspi: Add support for Versal NET platformMichal Simek
Trivial changes to support cadence ospi driver for Versal NET platform. Also avoid ospi flash reset for now. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/0789141f432189aab69bc496fe33e0218d1d7510.1663589964.git.michal.simek@amd.com
2022-09-25sandbox: Convert to use driver model for SCSISimon Glass
At present sandbox is producing a warning about SCSI migration. Drop the legacy code and replace it with a new implementation. Also drop the SATA command, which does not work with driver model. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25sandbox: scsi: Move request-handling code to scsi_emulSimon Glass
Move this code into the emulator file so it can be used by multiple drivers. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25sandbox: scsi: Move structs to header fileSimon Glass
Move these to the SCSI header file so we can access them from multiple emulators. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25sandbox: scsi: Remove setup calls from handle_read()Simon Glass
Move the device-specific code out into the top-level function. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25sandbox: scsi: Move reply setup out of helperSimon Glass
Move this code out of the helper function so we can (later) add it as part of the shared emulation code. Set a default value of 0 for buff_used since that is what we use when there is an error. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25sandbox: scsi: Move file size into shared structSimon Glass
Move this information into struct scsi_emul_info so we can use it in common code. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25sandbox: scsi: Move block size into shared structSimon Glass
Move this information into struct scsi_emul_info so we can use it in common code. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25scsi: Move vendor/product info into the shared structSimon Glass
Move this information into struct scsi_emul_info so we can use it in common code. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25sandbox: Move buffer to scsi_emul_infoSimon Glass
Move the buffer into this struct so it can be shared between different implementations. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25scsi: Move core emulation state into a new structSimon Glass
In preparation for sharing the emulation code between two drivers, move some of the fields into a new struct. Use a separate header file so it can be used by various drivers. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25scsi: Move cmd_phase enum to the headerSimon Glass
This can be used by common files, so move it to the SCSI header and rename it. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25sandbox: usb: Rename transfer_len in protocol structSimon Glass
This has the same name as a field in our local private struct, which is confusing. Change the name to xfer_len instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25blk: Rename if_type to uclass_idSimon Glass
Use the word 'uclass' instead of 'if_type' to complete the conversion. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-24serial: Call flush() before changing baudratePali Rohár
Changing baudrate is a sensitive operation. To ensure that U-Boot messages printed before changing baudrate are not lost, call new U-Boot console flush() function. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-09-24serial: Implement serial_flush() function for console flush() fallbackPali Rohár
Like in all other console functions, implement also serial_flush() function as a fallback int console flush() function. Flush support is available only when config option CONSOLE_FLUSH_SUPPORT is enabled. So when it is disabled then provides just empty static inline function serial_flush(). Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-09-24serial: Implement flush callbackPali Rohár
UART drivers have putc/puts functions which just put characters into HW transmit queue and do not wait until all data are transmitted. Implement flush callback via serial driver's pending(false) callback which waits until HW transmit all characters from the queue. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-09-23ddr: fsl: Fix re-align of verbose DRAM information for non-SPL buildsPali Rohár
During init_dram() is called also compute_lowest_common_dimm_parameters() function which prints multi-line detailed output. So print also re-aligning filler after "Detected ?DIMM" line to have "DRAM: " output aligned. Signed-off-by: Pali Rohár <pali@kernel.org>
2022-09-23ddr: fsl: Allow to detect 4 GB DDR modules in 32-bit modePali Rohár
U-Boot core code already handles the case when RAM size is bigger than CONFIG_MAX_MEM_MAPPED. So there is no need to do duplicate check in fsl ddr driver for CONFIG_MAX_MEM_MAPPED. Instead simplify code to just check if RAM size can be representable in phys_size_t type. And avoid printing warning if phys_size_t is just 1 byte smaller than RAM size, which is the typical situation with 4 GB DDR module. Signed-off-by: Pali Rohár <pali@kernel.org>
2022-09-23ddr: fsl: Fix fsl_ddr_sdram_size() for 4GB modules with 32-bit phys_size_tPali Rohár
Function fsl_ddr_compute() always return size in unsigned long long type, but function fsl_ddr_sdram_size() returns size in phys_size_t type. When 36-bit addressing mode is not enabled then phys_size_t type is only 32-bit and thus it cannot store value 4GB (0x100000000). Function fsl_ddr_sdram_size() in this case returns truncated value 0x0. Fix this issue by returning the highest representable value, which is 0xffffffff (4GB - 1 byte). This change fixes crashing of proper U-Boot because it detected 4 GB module as RAM with zero size. Signed-off-by: Pali Rohár <pali@kernel.org>
2022-09-23ddr: fsl: Fix checking for maximal mappable memoryPali Rohár
Check needs to be done against CONFIG_MAX_MEM_MAPPED macro and not fixed size 4GB (as CONFIG_MAX_MEM_MAPPED can be lower and for example for e500 cores it is just 2GB). Also fix printf re-align, which should be applied only for non-SPL builds, during init_dram() call. Signed-off-by: Pali Rohár <pali@kernel.org>
2022-09-23cpu: add basic cpu driver for MediaTek ARM chipsWeijie Gao
Add basic CPU driver used to retrieve CPU model information. Tested-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-09-23clk: mediatek: add clock driver support for MediaTek MT7981 SoCWeijie Gao
This patch adds clock driver support for MediaTek MT7981 SoC Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23clk: mediatek: add clock driver support for MediaTek MT7986 SoCWeijie Gao
This patch adds clock driver support for MediaTek MT7986 SoC Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23clk: mediatek: add CLK_XTAL support for clock driverWeijie Gao
This adds the CLK_XTAL macro/flag to allow modeling clocks which are directly connected to the xtal clock. Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23clk: mediatek: add infrasys clock mux supportWeijie Gao
This patch adds infrasys clock mux support for mediatek clock drivers. Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23clk: mediatek: add support to configure clock driver parentWeijie Gao
This patch adds support for a clock node to configure its parent clock where possible. Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23clk: mediatek: add CLK_BYPASS_XTAL flag to allow bypassing searching clock ↵Weijie Gao
parent of xtal clock The mtk clock framework in u-boot uses array index for searching clock parent (kernel uses strings for search), so we need to specify a special clock with ID=0 for CLK_XTAL in u-boot. In the mt7622/mt7629 clock tree, the clocks with ID=0 never call mtk_topckgen_get_mux_rate, adn return xtal clock directly. This what we expected. However for newer chips, they may have some clocks with ID=0 not representing the xtal clock and still needs mtk_topckgen_get_mux_rate be called. Current logic will make entire clock driver not working. This patch adds a flag to indicate that whether a clock driver needs clocks with ID=0 to call mtk_topckgen_get_mux_rate. Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23pinctrl: mediatek: add pinctrl driver for MT7986 SoCWeijie Gao
This patch adds pinctrl and gpio support for MT7986 SoC Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23pinctrl: mediatek: add pinctrl driver for MT7981 SoCWeijie Gao
This patch adds pinctrl and gpio support for MT7981 SoC Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23i2c: add support for MediaTek I2C interfaceWeijie Gao
This patch adds support for MediaTek I2C interface Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23spi: add support for MediaTek spi-mem controllerWeijie Gao
This patch adds support for spi-mem controller found on newer MediaTek SoCs This controller supports Single/Dual/Quad SPI mode. Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
2022-09-23watchdog: mediatek: add support for MediaTek MT7986 SoCWeijie Gao
Add watchdog support for MediaTek MT7986 SoC Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23timer: mtk: add support for MediaTek MT7981/MT7986 SoCsWeijie Gao
This patch add general-purpose timer support for MediaTek MT7981/MT7986. These two SoCs uses a newer version of timer with its register definition slightly changed. Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23pwm: mtk: add support for MediaTek MT7981 SoCWeijie Gao
This patch adds PWM support for MediaTek MT7981 SoC. MT7981 uses a different register offset so we have to add a version field to indicate the IP core version. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23pwm: mtk: add support for MediaTek MT7986 SoCWeijie Gao
This patch adds PWM support for MediaTek MT7986 SoC. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23serial: mtk: add support for using dynamic baud clock souceWeijie Gao
The baud clock on some platform may change due to assigned-clock-parent set in DT. In current flow the baud clock is only retrieved during probe stage. If the parent of the source clock changes after probe stage, the setbrg will set wrong baudrate. To get the right clock rate, this patch records the baud clk struct to the driver's priv, and changes the driver's flow to get the clock rate before calling _mtk_serial_setbrg(). Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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