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2025-07-18input: Tighten dependency requirements for TEGRA_KEYBOARDTom Rini
This driver requires headers which only exist on Tegra. Express that requirement in Kconfig as well. Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-18misc: Tighten requirements on IHS_FPGA driverTom Rini
This driver requires that the gdsys legacy driver option also be enabled in order to build. Express that requirement in Kconfig as well. Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-17Merge tag 'u-boot-imx-master-20250717' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27088 - Add support for the i.MX95 B0 version. - Enable standard boot for phycore-imx8mp. - Kconfig fixes for i.MX MMC and FSL_SEC_MON. - Support 4Gb single die variant of the i.MX8MM Venice board.
2025-07-17Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini
CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/27087 - Board: mpfs_icicle: Fix board_fit_config_name_match and disable DEBUG_UART - Board: Add SD card support to the Beagle-V-Fire - Board: Add support for TH1520-integrated GMACs
2025-07-17mmc: Remove unused kona_sdhci driverTom Rini
As no platforms use this driver anymore, remove it. Signed-off-by: Tom Rini <trini@konsulko.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-07-17mmc: Tighten some mmc driver dependenciesTom Rini
A large number of mmc drivers cannot build without access to some platform specific header files. Express those requirements in Kconfig as well. Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-07-17mmc: Take cleanup path to free memory on error exitAndrew Goodbody
Instead of returning -EINVAL directly which will not call the cleanup path to free memory, fix the code to set the error and then goto the cleanup code. This issue found by Smatch. Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-07-17nxp: Move FSL_SEC_MON related options to arch/Kconfig.nxpTom Rini
The options related to FSL_SEC_MON are part of the chain of trust related options and should be under that menu, so move it there. Furthermore we don't need to prompt for the driver itself but do need to allow for configuration of the monitor endianess. Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-17arm: imx: Remove unused mxcmmc driverTom Rini
As no platforms use this driver anymore, remove it. Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-17drivers: net: Add T-Head DWMAC glue layerYao Zi
The Designware IP integrated in TH1520 SoC requires extra clock configuration to operate correctly. The Linux kernel's T-Head DWMAC glue driver is ported and adapted to U-Boot's API. Signed-off-by: Yao Zi <ziyao@disroot.org> Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-17clk: thead: th1520-ap: Correctly handle flags for dividersYao Zi
Unlike the gate clocks which make no use of flags, most dividers in TH1520 SoC are one-based, thus are applied with CLK_DIVIDER_ONE_BASED flag. We couldn't simply ignore the flag, which causes wrong results when calculating the clock rates. Add a member to ccu_div_internal for defining the flags, and pass it to divider_recalc_rate(). With this fix, frequency of all the clocks match the Linux kernel's calculation. Fixes: e6bfa6fc94f ("clk: thead: Port clock controller driver of TH1520 SoC") Signed-off-by: Yao Zi <ziyao@disroot.org> Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-17spi: coreqspi: add xfer function for PolarFire SoCEoin Dickson
Add xfer function to PolarFire SoC coreqspi driver. The read and write operations are limited to one byte at a time instead of four as CMD18 (multiple block read) reads garbage when four byte ops are enabled. Signed-off-by: Eoin Dickson <eoin.dickson@microchip.com> Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-17gpio: add PolarFire SoC GPIO and Core GPIO driverEoin Dickson
This driver adds GPIO support for PolarFire SoC family, this is required to add sd card support on the Beagle-V-Fire as it uses GPIO chip selects Signed-off-by: Eoin Dickson <eoin.dickson@microchip.com> Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-16dfu: Fix dfu_config_interfaces() for single interface DFU syntaxSam Protsenko
As stated in DFU documentation [1], the device interface part might be missing in dfu_alt_info: dfu_alt_info The DFU setting for the USB download gadget with a semicolon separated string of information on each alternate: dfu_alt_info="<alt1>;<alt2>;....;<altN>" When several devices are used, the format is: - <interface> <dev>'='alternate list (';' separated) So in first case dfu_alt_info might look like something like this: dfu_alt_info="mmc 0=rawemmc raw 0 0x747c000 mmcpart 1;" And in second case (when the interface is missing): dfu_alt_info="rawemmc raw 0 0x747c000 mmcpart 1;" When the interface is not specified the 'dfu' command crashes when called using 'dfu 0' or 'dfu list' syntax: => dfu list "Synchronous Abort" handler, esr 0x96000006, far 0x0 That's happening due to incorrect string handling in dfu_config_interfaces(). In case when the interface is not specified in dfu_alt_info it triggers this corner case: d = strsep(&s, "="); // now d contains s, and s is NULL if (!d) break; a = strsep(&s, "&"); // s is already NULL, so a is NULL too if (!a) // corner case a = s; // a is NULL now which causes NULL pointer dereference later in this call, due to 'a' being NULL: part = skip_spaces(part); That's because as per strsep() behavior, when delimiter ("&") is not found, the token (a) becomes the entire string (s), and string (s) becomes NULL. To fix that issue assign "a = d" instead of "a = s", because at that point variable d actually contains previous s, which should be used in this case. [1] doc/usage/dfu.rst Fixes: commit febabe3ed4f4 ("dfu: allow to manage DFU on several devices") Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Link: https://lore.kernel.org/r/20250709042342.13544-1-semen.protsenko@linaro.org Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2025-07-15Merge patch series "drivers/net/airoha_eth: fixes"Tom Rini
Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> says: Several fixes for the airoha ethernet driver. Link: https://lore.kernel.org/r/20250709092810.4032971-1-mikhail.kshevetskiy@iopsys.eu
2025-07-15drivers/net/airoha_eth: enable hw padding of short tx packetsMikhail Kshevetskiy
Transmission of short packets does not work good for XFI (GDM2) and HSGMII (GDM3) interfaces. The issue can be solved with: - padding of short packets to 60 bytes - setting of PAD_EN bit in the corresponding REG_GDM_FWD_CFG(n) register. The issue should present for the lan switch (GDM1) as well, but it does does not appear due to unknown reason. This patch set PAD_EN bit for the used GDM. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2025-07-15drivers/net/airoha_eth: fix stalling in package receivingMikhail Kshevetskiy
ARCH_DMA_MINALIGN is 64 for ARMv7a/ARMv8a architectures, but RX/TX descriptors are 32 bytes long. So they may not be aligned on an ARCH_DMA_MINALIGN boundary. In case of RX path, this may cause the following problem 1) Assume that a packet has arrived and the EVEN rx descriptor has been updated with the incoming data. The driver will invalidate and check the corresponding rx descriptor. 2) Now suppose the next descriptor (ODD) has not yet completed. Please note that all even descriptors starts on 64-byte boundary, and the odd ones are NOT aligned on 64-byte boundary. Inspecting even descriptor, we will read the entire CPU cache line (64 bytes). So we read and sore in CPU cache also the next (odd) descriptor. 3) Now suppose the next packet (for the odd rx descriptor) arrived while the first packet was being processed. So we have new data in memory but old data in cache. 4) After packet processing (in arht_eth_free_pkt() function) we will cleanup the descriptor and put it back to rx queue. This will call flush_dcache_range() function for the even descriptor, so the odd one will be flushed as well (it is in the same cache line). So the old data will be written to the next rx descriptor. 5) We get a freeze. The next descriptor is empty (so the driver is waiting for packets), but the hardware will continue to receive packets on other available descriptors. This will continue until the last available rx descriptor is full. Then the hardware will also freeze. The problem will be solved if the previous descriptor will be put back to the queue instead of the current one. If the current descriptor is even (starts on a 64-byte boundary), then putting the previous descriptor to the rx queue will affect the previous cache line. To be 100% ok, we must make sure that the previous and the one before the previous descriptor cannot be used for receiving at this moment. If the current descriptor is odd, then the previous descriptor is on the same cache line. Both (current and previous) descriptors are not currently in use, so issue will not arrise. WARNING: The following restrictions on PKTBUFSRX must be held: * PKTBUFSRX is even, * PKTBUFSRX >= 4. The bug appears on 32-bit airoha platform, but should be present on 64-bit as well. The code was tested both on 32-bit and 64-bit airoha boards. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2025-07-15drivers/net/airoha_eth: fix packet transmission errorsMikhail Kshevetskiy
The dma_map_single() function calls one of the functions * invalidate_dcache_range(), * flush_dcache_range(). Both of them expect that 'vaddr' is aligned to the ARCH_DMA_MINALIGN boundary. Unfortunately, RX/TX descriptors are 32-byte long. Thus they might not be aligned to the ARCH_DMA_MINALIGN boundary. Data flushing (or invalidating) might do nothing in this case. The same applies to dma_unmap_single() function. In the TX path case the issue might prevent package transmission (filled TX descriptor was not flushed). To fix an issue a special wrappers for * dma_map_single(), * dma_unmap_single() functions were created. The patch fix flushing/invalidatiog for the RX path as well. The bug appears on 32-bit airoha platform, but should be present on 64-bit as well. The code was tested both on 32-bit and 64-bit airoha boards. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2025-07-15drivers/net/airoha_eth: add missing terminator for compatible devices listMikhail Kshevetskiy
Compatible device list must have a terminator. If terminator is missed the u-boot driver subsystem will access random data placed after the list in the memory. The issue can be observed with the "dm compat" command. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2025-07-15net: mediatek: correct the AN8855 TPID value in port isolation settingsWeijie Gao
The TPID value should be 0x9100 instead of 0x8100 according to the datasheet. Fixes: cedafee9ff3 (net: mediatek: add support for Airoha AN8855 ethernet switch) Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-07-14ofnode: NULL check bootscr_flash_size before dereferenceAndrew Goodbody
Move the NULL check of bootscr_flash_size to before the first time it is dereferenced to avoid any possible segment violations. This issue found by Smatch. Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2025-07-14pci: Assign a default value on reads on errorAndrew Goodbody
Many callers of PCI read functions do not check the return value for error before using the variable that should contain the value read were there not to be an error. However in the error case this variable is never assigned to and so will contain uninitialised data. To provide some certainty as to behaviour in the error case assign a default value of all bits set. This issue found by Smatch. Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-14scsi: Make static functions consistent using lbaint_tAndrew Goodbody
The static helper functions are inconsistent in their use of their third parameter which is used to pass a block count. Keep consistency by always using lbaint_t here. This will fix an issue where two left shifts were overflowing the variable type in use. This issue found by Smatch Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2025-07-14cros_ec: sandbox: Use correct value for number of slotsAndrew Goodbody
In the definition of struct ec_state the number of slots that are created is VSTORE_SLOT_COUNT (==4) but the value of req->slot is checked against EC_VSTORE_SLOT_MAX (==32) so this can lead to memory access beyond that allocated. Instead change the size check to use VSTORE_SLOT_COUNT to ensure it matches what has actually been allocated. This issue found by Smatch. Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-07-14gpio: add SPL to Kconfig option descriptionPhilip Molloy
DM_GPIO_LOOKUP_LABEL and SPL_DM_GPIO_LOOKUP_LABEL had the same description and therefore appeared to be duplicates in Kconfig frontends Signed-off-by: Philip Molloy <philip.molloy@analog.com>
2025-07-14pinctrl-uclass: update comment to reflect codePhilip Molloy
The logic was updated without modifying the comment above it Fixes: 72b8c6d1ebf ("pinctrl: don't fall back to pinctrl_select_state_simple()") Signed-off-by: Philip Molloy <philip.molloy@analog.com>
2025-07-14Merge tag 'qcom-main-20250714' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-snapdragon CI: https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/pipelines/27056 - Fix unused access in ufetch - Add missing clock for SM8650 - Port the Linux SPMI GPIO driver and port over SM8550 (other platforms should follow)
2025-07-14clk: qcom: sm8650: add usb3 noc clkRui Miguel Silva
Commit [0] introduced, correctly, the bubble of qcom clock errors to make it easy to spot missing clocks in the platforms, and this is a case of that, add the GCC_CFG_NOC_USB3_PRIM_AXI_CLK clock to sm8650 clock pool. 0: 7c5460afec3f ("clk/qcom: bubble up qcom_gate_clk_en() errors") Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250618093253.225929-1-rui.silva@linaro.org Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-07-14watchdog: qcom-wdt: Drop read check on write-only WDT_EN registerBalaji Selvanathan
On some Qualcomm platforms, such as Dragonwing boards, the WDT_EN register is write-only. Reading it back after enabling the watchdog can return invalid data or cause unexpected behavior. In particular, the check: if (readl(wdt_addr(wdt, WDT_EN)) != 1) may fail even though the watchdog is correctly enabled and running. This leads to misleading error messages and unnecessary failures. Removing the read check ensures compatibility and avoids false negatives on platforms where WDT_EN is not readable. This work builds upon this previous submission: https://lore.kernel.org/u-boot/20250625094607.1348494-1-gopinath.sekar@oss.qualcomm.com/ Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> Reviewed-by: Stefan Roese <sr@denx.de> Link: https://lore.kernel.org/r/20250701065738.1644669-1-balaji.selvanathan@oss.qualcomm.com Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-07-14gpio: qcom: move pm8550 gpio to new driverNeil Armstrong
Move support of the pm8550 gpios to the newly introduced driver and drop the compatible entry and the read-only quirk at the same time from the old driver. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Rui Miguel Silva <rui.silva@linaro.org> Acked-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250630-topic-sm8x50-pmic-gpio-pinctrl-new-v2-2-cc1512931197@linaro.org Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-07-14gpio: qcom: add new driver for SPMI gpiosNeil Armstrong
The current qcom_pmic_gpio driver is too limited and doesn't support state tracking for all pins like the Linux driver. Adding full pinconf support would require adding the state and it's much simpler to restart from scratch with a new driver based on the Linux one adapted to the U-Boot GPIO and Pinctrl APIs. For now only the PMICs I've been able to validate are added in the compatible list but we should be able to add the entire list from the Linux driver. There's a few difference from the Linux driver: - no IRQ support - uses the U-Boot GPIO flags that maps very well - uses the gpio-ranges to get the pins count - no debugfs but prints the pin state via pinmux callback It uses the same CONFIG entry as the old one, since the ultimate goal is to migrate entirely on this new driver once we verify it doesn't break the older platforms. Tested-by: Alexey Minnekhanov <alexeymin@postmarketos.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Rui Miguel Silva <rui.silva@linaro.org> Acked-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250630-topic-sm8x50-pmic-gpio-pinctrl-new-v2-1-cc1512931197@linaro.org Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-07-11block: sandbox: Add support for SYS_64BIT_LBATom Rini
In order to use SYS_64BIT_LBA with this driver we need for "start" to also be of type lbaint_t and to then use the correct printf format characters. Reviewed-by: Andrew Goodbody <andrew.goodbody@linaro.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-11Kconfig: Test for !COMPILE_TEST in some locationsTom Rini
We have a few options that we cannot enable in a "allyesconfig" type build because we cannot use zero as a default value. - The logic around HAS_BOARD_SIZE_LIMIT assumes that if we have set this then we compare with it. Similarly, we need to set SPL_NO_BSS_LIMIT as the default there. - Both SYS_CUSTOM_LDSCRIPT and ENV_USE_DEFAULT_ENV_TEXT_FILE then prompt for a file name to use. - The SYS_I2C_SOFT driver is a legacy driver which requires a lot of configuration within the board config. file instead, so disable it. Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-11Merge patch series "Create uclass for HW AES cryptographic devices"Tom Rini
Svyatoslav Ryhel <clamor95@gmail.com> says: Add uclass for HW AES cryptographic devices found on some devices, like Tegra20/Tegra30 SoC AES engine. Link: https://lore.kernel.org/r/20250629105711.24687-1-clamor95@gmail.com
2025-07-11crypto: aes: Add software AES DM driverIon Agorria
This adds AES crypto engine using the AES Uclass implemented in software, serves as example implementation and for uclass tests. Those implementing HW AES crypto engine drivers can use this as basis and replace software parts with the HW specifics of their device. Signed-off-by: Ion Agorria <ion@agorria.com>
2025-07-11dm: crypto: Create AES uclassIon Agorria
Create a basic framework for a group of devices that perform AES cryptographic operations. Signed-off-by: Ion Agorria <ion@agorria.com> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-07-11Merge tag 'u-boot-imx-master-20250710' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27010 - Fix the i.MX8M Nano GPU path. - Enable RNG support for KASLR on Toradex i.MX8 boards. - Enable watchdog and clock driver for imx6ulz_smm_m2b. - Tighten dependencies on CMD_BLOB. - Remove the rest of i.MX31 support.
2025-07-10Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-shTom Rini
- SH Ether clean ups, RZ/A1 clean ups, RZ/A1 Genmai support - Gen3 EEPROM DT node clean up - V4H SA0 BootROM compatible binman etype, SCIF compatible SREC generation for Gen4
2025-07-10net: sh_eth: arm: renesas: README: Drop CFG_SH_ETHER_PHY_ADDRMarek Vasut
Drop CFG_SH_ETHER_PHY_ADDR from README and configuration files, this value is never used, PHY address is extracted from control DT instead. No functional change intended. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-07-10net: sh_eth: Drop phy_addr assignmentMarek Vasut
Drop unused struct sh_eth_info *port_info .phy_addr member assignment. PHY address is extracted from control DT. No functional change intended. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-07-10net: sh_eth: Convert cache operations to static functionsMarek Vasut
Turn the current cache operation macros into static functions to improve compiler coverage checking. This does change the driver behavior slightly, the driver now expects those cache operation functions to be available on all architectures on which it is used. This should pose no problem, as the driver is only used on 32bit and 64bit ARM, which both have those operations. The CFG_SH_ETHER_ALIGNE_SIZE is converted to SH_ETHER_ALIGN_SIZE and defined as either 64 on ARM or 16 on SH. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-07-10net: sh_eth: arm: renesas: README: Drop CFG_SH_ETHER_USE_PORTMarek Vasut
The CFG_SH_ETHER_USE_PORT configuration option is a remnant from before U-Boot DM existed and SH Ethernet made full use of it, and is no longer used, remove it. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-07-10net: sh_eth: Pass struct port_info aroundMarek Vasut
The struct sh_eth_dev .port member is always set to 0, therefore only single-ported SH Ethernet is ever used. Support for multiple SH Ethernet ports implemented on driver level is a remnant from before U-Boot DM existed. Pass struct sh_eth_info port_info around directly and remove the struct sh_eth_dev entirely. Handling of multiple ports should be done by U-Boot DM and multiple per-driver-instance private data. No functional change intended. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-07-10nvme: Fix memory leak on error path of nvme_initAndrew Goodbody
The use of log_msg_ret to log a message and return an error meant that memory allocated earlier in the function was not freed on this error path. Instead log the message in the same way that log_msg_ret would do and then goto the cleanup code to free the memory. This issue found by Smatch. Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-10net: ti: icssg: Read firmware name from device-treeMD Danish Anwar
Update the ICSSG PRU Ethernet driver to read PRU/RTU/TXPRU firmware names from the Device Tree using the "firmware-name" property, instead of relying on the hard-coded firmware names. The firmware names are parsed during prueth_probe() and stored in the prueth->firmwares for each slice. The driver now uses these dynamically loaded names when starting the PRU cores. This change improves flexibility and allows firmware selection to be controlled via the device tree, making the driver more adaptable to different platforms and firmware configurations. Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
2025-07-10adc: Tighten some adc driver dependenciesTom Rini
A few adc drivers cannot build without access to some platform specific header files. Express those requirements in Kconfig as well. Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-10ata: Correct two dependency issuesTom Rini
First, the SATA_MV driver can only build on kirkwood or mvebu platforms due to header requirements, so add that as a dependency here. Second, SYS_SATA_MAX_DEVICE is also used by the API code so allow it to be configured in that case. Reviewed-by: Tony Dinh <mibodhi@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-10crypto: aspeed: Tighten some dependencies for the aspeed platformsTom Rini
Some of the aspeed platform drivers cannot build without platform specific headers being available. Express those requirements in Kconfig as well. Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-10crypto: fsl: Only allow these to be chosen on ARM/PowerPCTom Rini
These drivers require various headers which only exist on the ARM / PowerPC platforms which implement the hardware. Express that requirement in Kconfig as well. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-10crypto: nuvoton: Tighten some dependencies for the nuvoton platformsTom Rini
The nuvoton AES driver cannot build without platform specific headers being available. Express that requirement in Kconfig as well. Signed-off-by: Tom Rini <trini@konsulko.com>