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2024-04-23mmc: msm_sdhci: print core versionCaleb Connolly
This is useful for debugging. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23mmc: msm_sdhci: use modern DT handlingCaleb Connolly
using fdtdec_* functions is incompatible with OF_LIVE and generally offers a less friendly interface. Update to use dev_read_* functions instead. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23mmc: msm_sdhci: correct vendor_spec_cap0 register for v5Caleb Connolly
The V4 and V5 controllers have quite varied register layouts. Inherit the register offsets and naming from the Linux driver. More version specific offsets can be inherited from Linux as needed. Fixes: 364c22a ("mmc: msm_sdhci: Add SDCC version 5.0.0 support") Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23clk/qcom: add driver for sm8250 GCCCaleb Connolly
Add a clock driver for the SM8250 SoC. This driver can enable necessary clocks for UART, UFS, USB, and MMC. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23clk/qcom: add driver for sm6115 GCCCaleb Connolly
Add a driver for the clock controller in the SM6115 SoC, this is used in the QRB4210 RB2 board. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23clk/qcom: add driver for qcm2290 GCCCaleb Connolly
Add a clock driver for the QCM2290 SoC which is used in the QRB2210 RB1 board. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23button: qcom-pmic: add support for pmk8350 button configsNeil Armstrong
Finally add the entries for the qcom,pmk8350-pwrkey and qcom,pmk8350-resin found on PMICs used with SM8350 and later SoCs. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23button: qcom-pmic: move node name checks to btn_data structNeil Armstrong
Move node name checks to a proper data struct with all information for the supported subnodes. Replace the key offset defines with the Linux driver ones. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23gpio: qcom_pmic_gpio: add support for pm8550-gpioNeil Armstrong
Add support for PM8550 GPIO controller variant, keep read-only until the GPIO and Pinctrl setup is fixed for new PMICs. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23pinctrl: qcom: add sm8250 pinctrl driverCaleb Connolly
This SoC features a pinctrl block with north, south, and west tiles accessible to the AP. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23pinctrl: qcom: add sm6115 pinctrl driverCaleb Connolly
This SoC features a pinctrl block with west, east, and south tiles. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23pinctrl: qcom: add qcm2290 pinctrl driverCaleb Connolly
This SoC has a basic pinctrl block with no tiles. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23pinctrl: qcom: Add SM8650 pinctrl driverNeil Armstrong
Add pinctrl driver for the TLMM block found in the SM8650 SoC. This driver only handles the gpio and qup2_se7 pinmux, and makes sure the pinconf applies on SDC2 pins. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23pinctrl: qcom: Add SM8550 pinctrl driverNeil Armstrong
Add pinctrl driver for the TLMM block found in the SM8550 SoC. This driver only handles the gpio and qup1_se7 pinmux, and makes sure the pinconf applies on SDC2 pins. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23phy: qcom: add Synopsys eUSB2 PHY driverNeil Armstrong
Add a driver for the new Synopsys eUSB2 PHY found in the SM8550 and SM8650 SoCs. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-22Merge patch series "Kconfig: some cleanups"Tom Rini
Michal Simek <michal.simek@amd.com> says: I looked as cleaning up some dependencies and I found that qconfig is reporting some issues. This series is fixing some of them. But there are still some other pending. That's why please go and fix them if they are related to your board. UTF-8: I am using uni2ascii -B < file to do conversion. When you run it in a loop you will find some other issue with copyright chars or some issues in files taken from the Linux kernel like DTs. They should be likely fixed in the kernel first. Based on discussion I am ignoring names too.
2024-04-22common: Convert *.c/h from UTF-8 to ASCII enconfingMichal Simek
Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
2024-04-22Kconfig: Make all Kconfig encoding asciiMichal Simek
Some of Kconfigs are using utf-8 encoding because of used chars. Convert all of them to ascii enconging. Based on discussion ASCII should be used in general with the exception of names. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2024-04-22Kconfig: Add missing quotes around source fileMichal Simek
All errors are generated by ./tools/qconfig.py -b -j8 -i whatever. Error look like this: drivers/crypto/Kconfig:9: warning: style: quotes recommended around 'drivers/crypto/nuvoton/Kconfig' in 'source drivers/crypto/nuvoton/Kconfig' Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-04-22Kconfig: Remove trailing whitespace in its promptMichal Simek
All errors are generated by ./tools/qconfig.py -b -j8 -i whatever. Error look like this: warning: SPL_CLK_CCF (defined at drivers/clk/Kconfig:59) has leading or trailing whitespace in its prompt Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-04-22Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini
Not many and nothing really exciting this time: there are more patches in fly, but they are not ready yet. I will also send some DT updates and new board defconfig files later, once they have seen the list. I am aware of the USB rebasing repo efforts, but would like to see how this plays out, also we have one compatibility issue that I painstakingly work around in the U-Boot tree for the last three years or so. So for now I stick to the previous approach. So now just some easy changes: support for USB peripheral mode on the Allwinner F1C100s, T113-s3 SPI boot support, and some SPL cleanup patches. The branch passed the gitlab CI run, and brief boot testing on some boards didn't turn up any issues.
2024-04-22usb: musb-new: add Allwinner F1C100s supportAndre Przywara
The Allwinner F1C100s SoC has a MUSB controller like the one in the A33, but needs an SRAM region to be claimed like the A10. We do the latter anyway, even on chips that don't need it, so there is no real difference in our compatible string matching. Add a mapping between the config struct used in the Linux to our requirements here on the way. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2024-04-21Merge tag 'video-20240421' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-video CI: https://source.denx.de/u-boot/custodians/u-boot-video/-/pipelines/20466 - simple_panel: support timing parsing from EDID - dw_hdmi: fix gcc-14 compiler warnings - dw_hdmi: support vendor PHY for HDMI - rockchip: add Rockchip INNO HDMI PHY driver - rockchip: RK3328 HDMI and VOP support - evb-rk3328: enable vidconsole support - Tegra DC and DSI improvements and Tegra 114 support - add LG LG070WX3 MIPI DSI panel driver - add Samsung LTL106HL02 MIPI DSI panel driver - add Toshiba TC358768 RGB to DSI bridge support - add basic support for the Parade DP501 transmitter - Tegra 3 panel and bridge driver improvements - simplefb: modernise DT parsing - fdt_simplefb: Enumerate framebuffer info from video handoff - preserve framebuffer if SPL is passing video hand-off - fdt_support: allow reserving FB region without simplefb
2024-04-21video: Assume video to be active if SPL is passing video hand-offDevarsh Thakkar
If SPL is passing video handoff structure to U-boot then it is safe to assume that SPL has already enabled video and that's why it is passing video handoff structure to U-boot so that U-boot can preserve the framebuffer. Signed-off-by: Devarsh Thakkar <devarsht@ti.com> Reviewed-by: Nikhil M Jain <n-jain1@ti.com>
2024-04-21video: simplefb: modernise DT parsingCaleb Connolly
simplefb was using old style FDT parsing which doesn't behave well in combination with livetree. Update it to use ofnode instead and add a missing null check for the "format" property. Standardise the error logging while we're here. Fixes: 971d7e64245d ("video: simplefb") Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-21video: renesas: shift the init sequence by one step earlierSvyatoslav Ryhel
Shift all setup stages one step earlier to better fit the existing uclass. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2024-04-21video: bridge: ssd2825: shift the init sequence by one step earlierSvyatoslav Ryhel
Shift all setup stages one step earlier to better fit the existing uclass. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2024-04-21video: endeavoru-panel: shift the init sequence by one step earlierSvyatoslav Ryhel
Shift all setup stages one step earlier to better fit the existing uclass. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2024-04-21video: bridge: add basic support for the Parade DP501 transmitterJonas Schwöbel
The Parade DP501 is a DP & DVI/HDMI dual-mode transmitter. It enables an RGB/Parallel SOC output to be converted, packed and serialized into either DP or TMDS output device. Only DisplayPort functionality of this transmitter has been implemented and tested. Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2024-04-21video: bridge: add Toshiba TC358768 RGB to DSI bridge supportSvyatoslav Ryhel
Add initial support for the Toshiba TC358768 RGB to DSI bridge. The driver is based on the mainline Linux Toshiba TC358768 bridge driver and implements the same set of features. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF700T Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2024-04-21video: panel: add Samsung LTL106HL02 MIPI DSI panel driverAnton Bambura
LTL106HL02 is a color active matrix TFT (Thin Film Transistor) liquid crystal display (LCD) that uses amorphous silicon TFT as switching devices. This model is composed of a TFT LCD panel, a driver circuit and a backlight unit. The resolution of a 10.6" contains 1920 x 1080 pixels and can display up to 16,8M color with wide viewing angle. Co-developed-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Co-developed-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Anton Bambura <jenneron@protonmail.com>
2024-04-21video: panel: add LG LG070WX3 MIPI DSI panel driverSvyatoslav Ryhel
The LD070WX3 is a Color Active Matrix Liquid Crystal Display with an integral Light Emitting Diode (LED) backlight system. The matrix employs a-Si Thin Film Transistor as the active element. It is a transmissive type display operating in the normally Black mode. This TFT-LCD has 7.0 inches diagonally measured active display area with WXGA resolution (800 by 1280 pixel array). Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2024-04-21video: tegra20: dsi: use set_backlight for backlight onlyJonas Schwöbel
Shift the backlight set further to prevent visual glitches on panel init. Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2024-04-21video: tegra20: dsi: set correct fifo depthJonas Schwöbel
According to Thierry Reding's commit in the linux kernel 976cebc35bed0456a42bf96073a26f251d23b264 "drm/tegra: dsi: Make FIFO depths host parameters" correct depth of the video FIFO is 1920 *words* no *bytes* Tested-by: Ion Agorria <ion@agorria.com> # HTC One X Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Nvidia Tegratab T114 Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2024-04-21video: tegra20: dsi: remove pre-configurationJonas Schwöbel
Configuration for DC driver command mode is not required for every panel. Removed. Tested-by: Ion Agorria <ion@agorria.com> # HTC One X Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Nvidia Tegratab T114 Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2024-04-21video: tegra20: dsi: add reset supportSvyatoslav Ryhel
Implement reset use to discard any changes which could have been applied to DSI before and can interfere with current configuration. Tested-by: Ion Agorria <ion@agorria.com> # HTC One X Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Nvidia Tegratab T114 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2024-04-21video: tegra20: dsi: add T114 supportSvyatoslav Ryhel
Existing Tegra DSI driver mostly fits T114 apart MIPI calibration which on T114 has dedicated driver. To resolve this MIPI calibration logic was split for pre-T114 and T114+ devices. Tested-by: Ion Agorria <ion@agorria.com> # HTC One X Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Nvidia Tegratab T114 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2024-04-21video: tegra20: add MIPI calibration driverSvyatoslav Ryhel
Dedicated MIPI calibration driver is used on T114 and newer. Before T114 MIPI calibration registers were part of VI and CSI. Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Nvidia Tegratab T114 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2024-04-21video: tegra20: dc: parameterize V- and H-sync polaritiesSvyatoslav Ryhel
Based on Thierry Reding's Linux commit: 'commit 1716b1891e1de05e2c20ccafa9f58550f3539717 ("drm/tegra: rgb: Parameterize V- and H-sync polarities")' Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2024-04-21video: tegra20: dc: clean framebuffer memory blockJonas Schwöbel
Fill the framebuffer memory with zeros to avoid visual glitches. Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2024-04-21video: tegra20: dc: enable backlight after DC is configuredJonas Schwöbel
The goal of panel_set_backlight() is to enable backlight. Hence, it should be called at the probe end. Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2024-04-21video: tegra20: dc: fix printing of framebuffer addressJonas Schwöbel
Framebuffer address should not be a pointer. Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2024-04-21video: tegra20: dc: configure behavior if PLLD/D2 is usedSvyatoslav Ryhel
If DISP1 is a PLLD/D2 child, it cannot go over 370MHz. The cause of this is not quite clear. This can be overcomed by further halving the PLLD/D2 if the target parent rate is over 800MHz. This way DISP1 and DSI clocks will have the same frequency. The shift divider in this case has to be calculated from the original PLLD/D2 frequency and is passed from the DSI driver. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS Grouper E1565 Tested-by: Ion Agorria <ion@agorria.com> # HTC One X Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Nvidia Tegratab T114 Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Microsoft Surface 2 Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com>
2024-04-21video: tegra20: dc: add powergateSvyatoslav Ryhel
Add powergate use on T114 to complete resetting of DC. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2024-04-21video: tegra20: dc: add PLLD2 parent supportSvyatoslav Ryhel
T30+ SOC have second PLLD - PLLD2 which can be actively used by DC and act as main DISP1/2 clock parent. Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS Grouper E1565 Tested-by: Ion Agorria <ion@agorria.com> # HTC One X Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Nvidia Tegratab T114 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2024-04-21video: tegra20: dc: pass DC id to internal devicesSvyatoslav Ryhel
Tegra SoC has 2 independent display controllers called DC_A and DC_B, they are handled differently by internal video devices like DSI and HDMI controllers so it is important for last to know which display controller is used to properly set up registers. To achieve this, a pipe field was added to pdata to pass display controller id to internal Tegra SoC devices. Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS Grouper E1565 Tested-by: Ion Agorria <ion@agorria.com> # HTC One X Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Nvidia Tegratab T114 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2024-04-21video: tegra20: consolidate DC headerSvyatoslav Ryhel
Consolidate HD headers and place the result into video/tegra20 since it is used only by devices from this directory. Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS Grouper E1565 Tested-by: Ion Agorria <ion@agorria.com> # HTC One X Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Nvidia Tegratab T114 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2024-04-21video: tegra20: dc: fix image shift on rotated panelsSvyatoslav Ryhel
Subtracting 1 from x and y fixes image shifting on rotated panels. Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS Grouper E1565 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2024-04-21video: tegra20: dc: diverge DC per-SOCSvyatoslav Ryhel
Diverge DC driver setup to better fit each of supported generations of Tegra SOC. Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS Grouper E1565 Tested-by: Ion Agorria <ion@agorria.com> # HTC One X Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Nvidia Tegratab T114 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2024-04-21video: dw_hdmi: Fix compiler warnings with gcc-14Khem Raj
GCC-14 find more warnings like "make pointer from integer without a cast" fix them by adding a type cast. Signed-off-by: Khem Raj <raj.khem@gmail.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Tom Rini <trini@konsulko.com>