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2021-06-23nvme: Correct the prps per page calculation methodWesley Sheng
Each prp is 8 bytes, calculate the number of prps per page should just divide page size by 8 there is no need to minus 1 Signed-off-by: Wesley Sheng <wesleyshenggit@sina.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-06-23nvme: fix for big endian systemsDavid Lamparter
writel() and co. already include the endian swap; doing the swap twice is, er, unhelpful. Tested on a P4080DS, which boots perfectly fine off NVMe with this. Signed-off-by: David Lamparter <equinox@diac24.net> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-06-23clk: zynq: Add clock wizard driverZhengxun
The Clocking Wizard IP supports clock circuits customized to your clocking requirements. The wizard support for dynamically reconfiguring the clocking primitives for Multiply, Divide, Phase Shift/Offset, or Duty Cycle. Limited by U-Boot clk uclass without set_phase API, this patch only provides set_rate to modify the frequency. Signed-off-by: Zhengxun <zhengxunli.mxic@gmail.com> Reviewed-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23gpio: pca953x: Add missing i2c dependencyMichal Simek
pca953x also depends on i2c that's why add dependency to Kconfig. Where GPIO is enabled but I2C compilation error pops up. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2021-06-22mtd: spi-nor-ids: Add Macronix MX66UW2G345Gzhengxun
The MX66UW2G345G is Macronix Flash with SINGLE and OCTAL I/O. Hence, add SPI_NOR_OCTAL_READ flag for this flash. Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> [jagan: change order of id flags] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: zhengxun <zhengxunli.mxic@gmail.com>
2021-06-22Revert "mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to control card ↵Fabio Estevam
clock output" This reverts commit 63756575b42b8b4fb3f59cbbf0cedf03331bc2d2. Since this commit a imx6qdl-pico board boots extremely slowly in both SPL as well as U-Boot proper. Fix this regression by reverting the offending commit for now. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Pierre-Jean Texier <texier.pj2@gmail.com>
2021-06-22mmc: mmc-uclass: change to static about dm functionJaehoon Chung
Change to static about dm function. They can be used with wrapper functions. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-06-22mmc: fsl_esdhc_imx: use mmc_send_cmd instead of dm_mmc_send_cmdJaehoon Chung
Use mmc_send_cmd instead of dm_mmc_send_cmd. It doesn't need to distinguish this function. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-06-22mmc: dwmmc: socfpga: Get "fifo-mode" property from DTLey Foon Tan
Add FIFO mode support for SoCFPGA dwmmc, read "fifo-mode" property from DT. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-06-22mmc: dw_mmc: Fixes data read when receiving DTO interrupt in FIFO modeLey Foon Tan
The data read is not working when using FIFO mode. From DesignWare databook, when a Data_Transfer_Over (DTO) interrupt is received, the software should read the remaining data from FIFO. Add DTO interrupt checking on data read path and clear interrupts before start reading from FIFO. So, it doesn't clear the next pending interrupts unintentionally after read from FIFO. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-06-22mmc: mtk-sd: increase the minimum bus frequencyWeijie Gao
With a 48MHz input clock, the lowest bus frequency can be as low as 48000000 / (4 * 4095) = 2930Hz. Such an extremely low frequency will cause the mmc framework take seconds to finish the initialization. Limiting the minimum bus frequency to a slightly higher value can solve the issue without any side effects. Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-06-19Merge tag 'u-boot-rockchip-20210618' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-rockchip into next - New SoC platform support: rk3568; - rockchip pcie Code compile issue fix; - Board fix for rk3399 Khadas Edge; - Add Rockchip NFC driver;
2021-06-18net: octeontx: smi: use dt live tree APITim Harvey
clean up octeontx_smi_probe by using the live-tree API. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-06-18net: sun8i-emac: fix MDIO frequencyHeinrich Schuchardt
Commit 4f0278dac56a ("net: sun8i-emac: Lower MDIO frequency") leads to network failure on the OrangePi PC. => dhcp sun8i_emac_eth_start: Timeout According to the commit message the change of the MDIO frequency is only required for external PHYs. Fixes: 4f0278dac56a ("net: sun8i-emac: Lower MDIO frequency") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-06-18net: synquacer: Add netsec driverJassi Brar
Add SynQuacer's NETSEC GbE controller driver. Since this driver will load the firmware from SPI NOR flash, this depends on CONFIG_SYNQUACER_SPI=y. Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-06-18net: dwc_eth_qos: Revert some changes of commit 3a97da12ee7bDaniil Stas
Revert some changes of commit 3a97da12ee7b ("net: dwc_eth_qos: add dwc eqos for imx support") that were probably added by mistake. One of these changes can lead to received data corruption (enabling FUP and FEP bits). Another causes invalid register rxq_ctrl0 settings for some platforms. And another makes some writes at unknown memory location. Fixes: 3a97da12ee7b ("net: dwc_eth_qos: add dwc eqos for imx support") Signed-off-by: Daniil Stas <daniil.stas@posteo.net> Cc: Ye Li <ye.li@nxp.com> Cc: Fugang Duan <fugang.duan@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-06-18net: dwc_eth_qos: Fix needless phy auto-negotiation restartsDaniil Stas
Disabling clk_ck clock leads to link up status loss in phy, which leads to auto-negotiation restart before each network command execution. This issue is especially big for PXE boot protocol because of auto-negotiation restarts before each configuration filename trial. To avoid this issue don't disable clk_ck clock after it was enabled. Signed-off-by: Daniil Stas <daniil.stas@posteo.net> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-06-18net: e1000: do not attempt to set hwaddr for i210 without FLASHTim Harvey
commit f1bcad22dd19 ("net: e1000: add support for writing to EEPROM") adds support for storing hwaddr in EEPROM however i210 devices do not support this and thus results in errors such as: Warning: e1000#0 failed to set MAC address' Check if a flash device is present and if not return -ENOSYS indicating this is not supported. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-06-18Fix a memory leak issue in the RX port initialization.Hou Zhiqiang
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-06-18clk: cosmetic change in uclassPatrick Delaunay
Remove the tab in clk_get_bulk to respect the coding rules. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18dfu: add error callbackPatrick Delaunay
Add error callback in dfu stack to manage some board specific behavior on DFU targets. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18dfu: dfu_mtd: set max_buf_size to erasesize also for NOR devicesPatrick Delaunay
For NOR devices the logical DFU buffer size is the sector_size, as it is done in dfu_sf.c or in spi/sf_mtd.c (sf_mtd_info.erasesize = flash->sector_size) For NAND the DFU size was already limited to erasesize as has_pages = true. So the mtd dfu backend can use this erasesize for all the MTD devices, NOR and NAND with dfu->max_buf_size = mtd->erasesize This difference was initially copied from MTD command, where data is fully available in RAM without size limitation. This patch avoids to have many sector write in dfu_mtd.c at the end of the DFU transfer and avoids issues with USB timeout or WATCHDOG. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18spi: stm32_qspi: Fix short data write operationDaniil Stas
TCF flag only means that all data was sent to FIFO. To check if the data was sent out of FIFO we should also wait for the BUSY flag to be cleared. Otherwise there is a race condition which can lead to inability to write short (one byte long) data. Signed-off-by: Daniil Stas <daniil.stas@posteo.net> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-06-18mtd: nand: NFC drivers for RK3308, RK2928 and othersYifeng Zhao
This driver supports Rockchip NFC (NAND Flash Controller) found on RK3308, RK2928, RKPX30, RV1108 and other SOCs. The driver has been tested using 8-bit NAND interface on the ARM based RK3308 platform. Support Rockchip SoCs and NFC versions: - PX30 and RK3326(NFCv900). ECC: 16/40/60/70 bits/1KB. CLOCK: ahb and nfc. - RK3308 and RV1108(NFCv800). ECC: 16 bits/1KB. CLOCK: ahb and nfc. - RK3036 and RK3128(NFCv622). ECC: 16/24/40/60 bits/1KB. CLOCK: ahb and nfc. - RK3066, RK3188 and RK2928(NFCv600). ECC: 16/24/40/60 bits/1KB. CLOCK: ahb. Supported features: - Read full page data by DMA. - Support HW ECC(one step is 1KB). - Support 2 - 32K page size. - Support 8 CS(depend on SoCs) Limitations: - No support for the ecc step size is 512. - Untested on some SoCs. - No support for subpages. - No support for the builtin randomizer. - The original bad block mask is not supported. It is recommended to use the BBT(bad block table). Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-18pci: pcie_dw_rockchip: Replace msleep occurences by udelayAnand Moon
Replace msleep occurences by udelay. drivers/pci/pcie_dw_rockchip.c:254:3: warning: implicit declaration of function 'msleep' [-Wimplicit-function-declaration] Cc: Patrick Wildt <patrick@blueri.se> Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Anand Moon <linux.amoon@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-18pci: pcie_dw_rockchip: Drop the unused variable warningAnand Moon
Drop the unused variable warning below. drivers/pci/pcie_dw_rockchip.c:161:6: warning: unused variable 'val' [-Wunused-variable] 161 | u32 val; | ^~~ Cc: Patrick Wildt <patrick@blueri.se> Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Patrick Wildt <patrick@blueri.se> Signed-off-by: Anand Moon <linux.amoon@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-18pci: pcie_dw_rockchip: Fixed the below compilation errorAnand Moon
Use the generic error number instead of specific error number. Changes fix the below error. drivers/pci/pcie_dw_rockchip.c: In function 'rk_pcie_read': drivers/pci/pcie_dw_rockchip.c:70:10: error: 'PCIBIOS_UNSUPPORTED' undeclared (first use in this function) 70 | return PCIBIOS_UNSUPPORTED; | ^~~~~~~~~~~~~~~~~~~ drivers/pci/pcie_dw_rockchip.c: In function 'rk_pcie_write': drivers/pci/pcie_dw_rockchip.c:90:10: error: 'PCIBIOS_UNSUPPORTED' undeclared (first use in this function) 90 | return PCIBIOS_UNSUPPORTED; | ^~~~~~~~~~~~~~~~~~~ Cc: Patrick Wildt <patrick@blueri.se> Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Patrick Wildt <patrick@blueri.se> Signed-off-by: Anand Moon <linux.amoon@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-18rockchip: rk3568: Add sdram driverJoseph Chen
Add the driver for rk3568 u-boot to get sdram capacity. Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-18rockchip: rk3568: add clock driverElaine Zhang
Add rk3568 clock driver and cru structure definition. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-17Merge tag 'u-boot-atmel-2021.10-a' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-atmel into next First set of u-boot-atmel features for the 2021.10 cycle: This feature set converts the boards pm9261 and pm9263 Ethernet support to DM; enables hash command for all SAM boards; fixes the NAND pmecc bit-flips correction; adds Falcon boot for sama5d3_xplained board; and other minor adjustments.
2021-06-17Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini
- fsl-qoriq: Bug fixes related pfe, eth, thermal node, vid.c, cpu release, mmc, usb, env, etc for Layerscape boards - powerpc: Update Maintainers for some boards.
2021-06-17net: tsec: add option to set device max-speed via dtsAleksandar Gerasimovski
Current tsec adapter sets adapter gigabit capabilities by default, and in reality this must not always be the case. It is possible that tsec adapter is used for 100Mbps connection, and in this case setting 1000Mbps capabilities can lead to some side effects such longer autoneg process. In our ls102x designs this problem leads to long autoneg times (> 4 sec) in case board rgmii link is 100Mbps capable only. Limiting the rgmii link capabilities provides faster and smoother link establishment. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-06-17mmc: fsl_esdhc_imx: drop CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33Yangbo Lu
There is no i.MX board using such option. Drop it. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-06-17mmc: fsl_esdhc: convert to CONFIG_FSL_ESDHC_VS33_NOT_SUPPORTYangbo Lu
For eSDHC, power supply is through peripheral circuit. Some eSDHC versions have value 0 of the bit but that does not reflect the truth. 3.3V is common for SD/MMC, and is supported for all boards with eSDHC in current u-boot. So, make 3.3V is supported in default in code. CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT can be enabled if future board does not support 3.3V. This is also a fix-up for one previous patch, which converted to use IS_ENABLED() for CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 that is not a Kconfig option. Fixes: 52faec31827e ("mmc: fsl_esdhc: replace most #ifdefs by IS_ENABLED()") Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-06-17pci: layerscape-ep: Add check of the PCIe controller enablementHou Zhiqiang
Stop to initialize the PCIe controller if it's disabled by RCW. Fixes: 118e58e26eba ("pci: layerscape: Split the EP and RC driver") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-06-17armv8: ls1012a: Pass PPFE firmware to Linux through FDTChaitanya Sakinam
Read Linux PPFE firmware from flash partition and pass it to Linux through FDT entry. So that we can avoid placing PPFE firmware in Linux rootfs. (FDT may increase at max by 64KB) Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com> Signed-off-by: Anji J <anji.jagarlmudi@nxp.com> Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-06-17clk: k210: Move k210 clock out of its own subdirectorySean Anderson
Now that we have only one clock driver, we don't need to have our own subdirectory. Move the driver back with the rest of the clock drivers. The MAINTAINERS for kendryte pinctrl is also fixed since it has always been wrong. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17clk: k210: Remove bypass driverSean Anderson
This driver no longer serves a purpose now that we have moved away from CCF. Drop it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17clk: k210: Don't set PLL rates if we are already at the correct rateSean Anderson
This speeds up boot by preventing multiple reconfigurations of the PLLs. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17clk: k210: Re-add support for setting rateSean Anderson
This adds support for setting clock rates, which was left out of the initial CCF expunging. There are several tricky bits here, mostly related to the PLLS: * The PLL's bypass is broken. If the PLL is reconfigured, any child clocks will be stopped. * PLL0 is the parent of ACLK which is the CPU and SRAM's clock. To prevent stopping the CPU while we configure PLL0's rate, ACLK is reparented to IN0 while PLL0 is disabled. * PLL1 is the parent of the AISRAM clock. This clock cannot be reparented, so we instead just disallow changing PLL1's rate after relocation (when we are using the AISRAM). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17clk: k210: Implement soc_clk_dumpSean Anderson
Since we are no longer using CCF we cannot use the default soc_clk_dump. Instead, implement our own. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17clk: k210: Move pll into the rest of the driverSean Anderson
Now that there no separate PLL driver, we can no longer make the PLL functions static. By moving the PLL driver in with the rest of the clock code, we can make these functions static again. We still keep the pll header for unit testing, but it is pretty reduced. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17clk: k210: Rewrite to remove CCFSean Anderson
This is effectively a complete rewrite to remove all dependency on CCF. The code is now smaller, and so is the binary. It also takes up less memory at runtime (since we don't have to create 40 udevices). In general, I am much happier with this driver as much of the complexity and late binding has been removed. The k210_*_params structs which were previously used to initialize CCF clocks are now used as the complete configuration. Since we can write our own division logic, we can now do away with several "half" clocks which only existed to provide constant factors of two. The clock IDs have been renumbered to remove unused clocks. This may not be the last time they are renumbered, since we have diverged with Linux. There are also still a few clocks left out which may need to be added back in. In general, I have tried to leave out behavioral changes. However, there is a small bugfix regarding ACLK. According to the technical reference manual, its mux comes *after* its divider (which is present only for PLL0). This would have required yet another intermediate clock to fix with CCF, but with the new driver it is just 2 lines of code :) Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17clk: Allow force setting clock defaults before relocationSean Anderson
Since 291da96b8e ("clk: Allow clock defaults to be set during re-reloc state for SPL only") it has been impossible to set clock defaults before relocation. This is annoying on boards without SPL, since there is no way to set clock defaults before U-Boot proper. In particular, the aisram rate must be changed before relocation on the K210, since U-Boot will hang if we try and change the rate while we are using aisram. To get around this, extend the stage parameter to allow force setting defaults, even if they would be otherwise postponed for later. A device tree property was decided against because of the concerns in the original commit thread about the overhead of repeatedly parsing the device tree. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-06-16Merge tag 'u-boot-imx-20210616' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20210616 ------------------- - imxrt : fixes, USB, imxrt1020-evk - imx8m: fix for verdin-imx8mm Add conga-QMX8 board - imx6 : documentation for pico-imx6: Add SeeedStudio NPI-IMX6ULL Support ventana: DM PCI - imx7d: added SMEGW01 board CI : https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/7765
2021-06-16ls1012a: net: pfe: remove pfe stop from bootcmdMian Yousaf Kaukab
When using bootefi to boot a EFI binary, u-boot is supposed to provide networking service for EFI application. Currently, 'pfe stop' command is called from bootcmd before running bootefi. As a result network stops working for EFI applications and console is flooded with "Rx pkt not on expected port" messages. Implement board_quiesce_devices() for ls1012a boards and call pfe_command_stop() from it instead of calling 'pfe stop' from *_bootcmd and bootcmd. Tested-by: Anji Jagarlmudi <anji.jagarlmudi@nxp.com> Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> [Fixed checkpatch space error] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-06-11dma: ti: k3-udma: Add support for native configuration of chan/flowVignesh Raghavendra
In absence of Device Manager (DM) services such as at R5 SPL stage, driver will have to natively setup TCHAN/RCHAN/RFLOW cfg registers. Add support for the same. Note that we still need to send chan/flow cfg message to TIFS via TISCI client driver in order to open up firewalls around chan/flow but setting up of cfg registers is handled locally. U-Boot specific code is in a separate file included in main driver so as to maintain similarity with kernel driver in order to ease porting of code in future. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210607141753.28796-8-vigneshr@ti.com
2021-06-11soc: ti: k3-navss-ringacc: Add support for native configuration of ringsVignesh Raghavendra
In absence of Device Manager (DM) services such as at R5 SPL stage, driver will have to natively setup Ring Cfg registers. Add support for the same. Note that we still need to send RING_CFG message to TIFS via TISCI client driver in order to open up firewalls around Rings. U-Boot specific code is in a separate file included in main driver so as to maintain similarity with kernel driver in order to ease porting of code in future. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210607141753.28796-7-vigneshr@ti.com
2021-06-11firmware: ti_sci: Add support for Resoure Management at R5 SPL stage.Vignesh Raghavendra
On J721e and J7200, MCU R5 core (boot master) itself would run Device Manager (DM) Firmware and interact with TI Foundational Security (TIFS) firmware to enable DMA and such other Resource Management (RM) services. So, during R5 SPL stage there is no such RM service available and ti_sci driver will have to directly interact with TIFS using DM to DMSC channels to request RM resources. Therefore add DT binding and driver for the same. This driver will handle Resource Management services at R5 SPL stage. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210607141753.28796-4-vigneshr@ti.com
2021-06-11firmware: ti_sci: Implement GET_RANGE with static dataVignesh Raghavendra
In case of R5 SPL, GET_RANGE API service is not available (as DM services are not yet up), therefore service such calls locally using per SoC static data. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210607141753.28796-3-vigneshr@ti.com
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