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2022-07-03mtd: rawnand: fsl_elbc: Fix detection when nand_scan_ident() has not ↵Pali Rohár
selected ecc.mode ecc.mode is set to 0 (aliased to NAND_ECC_NONE) either when function nand_scan_ident() has not selected ecc.mode or when it selected it to none ecc mode. Distinguish between these two states by checking of node property "nand-ecc-mode" which function nand_scan_ident() uses for filling ecc.mode. This change fixes usage of none ecc mode if it is specified in DTS file. Fixes: c9ea9019c5aa ("mtd: rawnand: fsl_elbc: Use ECC configuration from device tree") Signed-off-by: Pali Rohár <pali@kernel.org>
2022-06-30Merge tag 'u-boot-at91-2022.10-a' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-at91 into next First set of u-boot-at91 features for the 2022.10 cycle: This feature set includes mostly fixes and alignments: DT alignment with Linux for sama7g5, removal of invalid eeprom compatibles, removal of extra debug_uart_init calls for all at91 boards, support for pio4 driver pioE bank, and other minor fixes and enhancements for sam9x60 and sama5d2_icp boards.
2022-06-30Merge tag 'versal-qspi-for-v2022.10' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next Versal QSPI/OSPI changes for v2022.10 - Add new flash types - Add cadence ospi driver for Xilinx Versal
2022-06-30gpio: atmel_pio4: add support for PIO_PORTEMihai Sain
Add support for gpio PORT E, which is available on e.g. sama7g5 SoC. Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
2022-06-29spi: cadence-qspi: Fix programming ospi flash speedT Karthik Reddy
When the requested flash speed is 0, the baudrate division for the requested speed causing drop in the performance. So set the ospi flash to operate at max frequency when requested speed is zero. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220512100535.16364-6-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-29spi: cadence_qspi: Enable apb linear mode for apb read & write operationsT Karthik Reddy
On versal platform, enable apb linear mode for apb read and write execute operations amd disable it when using dma reads. This is done by xilinx_pm_request() secure calls when CONFIG_ZYNQMP_FIRMWARE is enabled, else we use direct raw reads and writes in case of mini U-Boot. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220512100535.16364-5-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-29spi: cadence-qspi: reset qspi flash for versal platformT Karthik Reddy
When flash operated at non default mode like DDR, flash need to be reset to operate in SDR mode to read flash ids by spi-nor framework. Reset the flash to the default state before using the flash. This reset is handled by a gpio driver, in case of mini U-Boot as gpio driver is disabled, we do raw read and write access by the registers. Versal platform utilizes spi calibration for read delay programming, so incase by default read delay property is set in DT. We make sure not to use read delay from DT by overwriting read_delay with -1. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220512100535.16364-4-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-29arm64: versal: Add versal specific cadence ospi driverT Karthik Reddy
Add support for cadence ospi driver for Versal platform. This driver provides support for DMA read operation which utilizes cadence qspi driver. If "cdns,is-dma" DT property is specified use dma for read operation from cadence_qspi driver. As cadence_qspi_apb_dma_read() is defined in cadence_ospi_versal driver add a weak function defination in cadence_qspi driver. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220512100535.16364-3-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-29spi: cadence-qspi: move cadence qspi macros to header fileT Karthik Reddy
Move all the cadence macros from cadence_qspi_apb.c to cadence_qspi.h file. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220512100535.16364-2-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-29mtd: spi-nor-ids: Add support for flashes tested by xilinxAshok Reddy Soma
Add support for various flashes from below manufacturers which are tested by xilinx for years. EON: en25q128b GIGA: gd25lx256e ISSI: is25lp008 is25lp016 is25lp01g is25wp008 is25wp016 is25wp01g is25wx256 MACRONIX: mx25u51245f mx66u1g45g mx66l2g45g MICRON: mt35xl512aba mt35xu01g SPANSION: s70fs01gs_256k SST: sst26wf016b WINBOND: w25q16dw w25q16jv w25q512jv w25q32bv w25h02jv Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/1653455832-14763-1-git-send-email-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-28Convert CONFIG_USB_MAX_CONTROLLER_COUNT to KconfigTom Rini
This converts the following to Kconfig: CONFIG_USB_MAX_CONTROLLER_COUNT Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28usb: Remove non-DM code in ehci-fsl and xhciTom Rini
The DM_USB migration deadline has passed and this is not used in SPL. Remove this now unused code. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28Convert CONFIG_FPGA_STRATIX_V to KconfigTom Rini
This converts the following to Kconfig: CONFIG_FPGA_STRATIX_V Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28video: Migrate exynos display options to KconfigTom Rini
Following how it's done for the majority of drivers, add a new VIDEO_EXYNOS option and Kconfig file under drivers/video/exynos and list the current options there. Cc: Anatolij Gustschin <agust@denx.de> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2022-06-28arm: samsung: Migrate a number of symbols to KconfigTom Rini
- In a number of cases, use CONFIG_ARCH_EXYNOS[45] rather than CONFIG_EXYNOS[45] - In other cases, test for CONFIG_ARCH_EXYNOS or CONFIG_ARCH_S5PC1XX - Migrate specific SoC CONFIG values to Kconfig - Use CONFIG_TARGET_x rather than CONFIG_x - Migrate other CONFIG_EXYNOS_x symbols to Kconfig - Reference CONFIG_EXYNOS_RELOCATE_CODE_BASE directly as EXYNOS_RELOCATE_CODE_BASE - Rename CONFIG_S5P_PA_SYSRAM to CONFIG_SMP_PEN_ADDR to match the rest of U-Boot usage. Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28arm: exynos: Remove old pwm backlight driverTom Rini
Remove the unused older exynos pwm backlight driver. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2022-06-28arm: samsung: Remove dead LCD codeTom Rini
Since bb5930d5c97f ("exynos: video: Convert several boards to driver model for video") there have been no callers of any of the exynos_lcd_* family of functions. Remove these from the boards, and then remove unused logo and related code as well. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2022-06-28block: ide: Remove ide_preinit functionTom Rini
The only platform currently that defines an ide_preinit function has an empty one that immediately returns. Remove this hook. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28ata: sata_sil: Remove useless BLK guard in sata_sil.hTom Rini
Now that the driver only supports CONFIG_BLK, remove the useless guard in sata_sil.h. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28Convert CONFIG_LBA48 et al to KconfigTom Rini
This converts the following to Kconfig: CONFIG_LBA48 CONFIG_SYS_64BIT_LBA Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28Convert CONFIG_FSL_SATA_V2 to KconfigTom Rini
This converts the following to Kconfig: CONFIG_FSL_SATA_V2 Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28ata: fsl_sata: Remove legacy non-BLK codeTom Rini
The migration deadline for this has passed and all boards have been updated, remove this legacy code and references for it. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28ata: dwc_ahsata: Remove legacy non-CONFIG_AHCI codeTom Rini
The migration deadline for this has passed and all boards have been updated, remove this legacy code and references for it. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28tpl: Ensure all TPL symbols in Kconfig have some TPL dependencyTom Rini
Tighten up symbol dependencies in a number of places. Ensure that a TPL specific option has at least a direct dependency on TPL. In places where it's clear that we depend on something more specific, use that dependency instead. Reported-by: Pali Rohár <pali@kernel.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28usb: ehci-mx5: Remove non-DM codeTom Rini
The deadline for DM_USB migration has passed and all users have been migrated. Remove now unused code. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28usb: ehci-mxc: RemoveTom Rini
There are no platforms enabling this driver, remove. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28usb: xhci-fsl: Remove non-DM codeTom Rini
The deadline for DM_USB migration has passed and all users have been migrated. Remove now unused code. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28Convert CONFIG_USB_EHCI_TXFIFO_THRESH to KconfigTom Rini
This converts the following to Kconfig: CONFIG_USB_EHCI_TXFIFO_THRESH Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28usb: ehci-fsl: Remove non-DM codeTom Rini
The deadline for DM_USB migration has passed and all users have been migrated. Remove now unused code. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28Convert CONFIG_EHCI_HCD_INIT_AFTER_RESET to KconfigTom Rini
This converts the following to Kconfig: CONFIG_EHCI_HCD_INIT_AFTER_RESET Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28Convert CONFIG_EHCI_DESC_BIG_ENDIAN et al to KconfigTom Rini
This converts the following to Kconfig: CONFIG_EHCI_DESC_BIG_ENDIAN CONFIG_EHCI_MMIO_BIG_ENDIAN Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28ehci-mxs: Remove non-DM codeTom Rini
This code is not enabled anywhere, drop it. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28Convert CONFIG_E1000_NO_NVM to KconfigTom Rini
This converts the following to Kconfig: CONFIG_E1000_NO_NVM Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28misc: i2c_eeprom: remove 24aa02e48Eugen Hristev
This compatible does not exist in the bindings. All occurences in DT have been replaced by at24c02 which is equivalent. Fixes: 7264066707 ("misc: i2c_eeprom: Add compatible for 24AA02E48") Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Michael Walle <michael@walle.cc> Reviewed-by: Heiko Schocher <hs@denx.de>
2022-06-27Merge tag 'xilinx-for-v2022.10' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2022.10 cpu: - Add driver for microblaze cpu net: - Add support for DM_ETH_PHY to AXI emac and emaclite xilinx: - Switch platforms to DM_ETH_PHY - DT chagnes in ZynqMP and Zynq - Enable support for SquashFS zynqmp: - Add support for KR260 boards - Move BSS from address 0 - Move platform identification from board code to soc driver - Improve zynqmp_psu_init_minimize versal: - Enable loading app at EL1 serial: - Setup default address and clock rates for DEBUG uarts pinctrl: - Add support for tri state and output enable properties relocate-rela: - Clean relocate-rela implementation for ARM64 - Add support for Microblaze microblaze: - Add support for runtime relocation - Rework cache handling (wiring, Kconfig) based on cpuinfo - Remove interrupt support timer: - Extract axi timer driver from Microblaze to generic location
2022-06-27timer: Add SPL_REGMAP dependency for Xilinx timerMichal Simek
Add SPL_REGMAP dependency when SPL is enabled. This can avoid compilation issues if timer is selected but SPL_REGMAP not. Reported-by: Ovidiu Panait <ovidiu.panait@windriver.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/8f6c187e04cb3127bf5148ae2dbbdf55b25ea544.1655982509.git.michal.simek@amd.com
2022-06-24soc: xilinx: zynqmp: Add machine identification supportStefan Herbrechtsmeier
Add machine identification support based on the zynqmp_get_silicon_idcode_name function and use the soc_get_machine function of the soc uclass to get silicon idcode name for the fpga init. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220620163650.18756-8-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24soc: xilinx: zynqmp: Remove redundant checks for zynqmp_mmio_readStefan Herbrechtsmeier
Remove the redundant SPL and CurrentEL checks for the zynqmp_mmio_read function call because the function itself runs the same checks. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220620163650.18756-7-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24firmware: zynqmp: Probe driver before useStefan Herbrechtsmeier
Probe the driver before use to ensure that the driver is always available and the global data are valid. Initialize the global data with zero and probe the driver if the global data are still zero. This allows a usage of the firmware functions from other drivers with arbitrary order between the drivers. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220620163650.18756-2-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24firmware: zynqmp: Check if rx channel dev pointer is validStefan Herbrechtsmeier
Check if rx channel dev pointer is valid and not if the address of the pointer is valid. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220620163650.18756-1-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24microblaze: Convert axi timer to DM driverMichal Simek
Move axi timer driver from Microblaze to generic location. Origin implementation was irq based with counting down timer. CONFIG_TIMER drivers are designed differently that timer is free running up timer with automatic reload without any interrupt. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by: Michal Simek <michal.simek@amd.com> Tested-by: Ovidiu Panait <ovidiu.panait@windriver.com> Link: https://lore.kernel.org/r/6c12fc86bbc1f17d05c25018862e7b7b03346b36.1654684731.git.michal.simek@amd.com
2022-06-24cpu: add CPU driver for microblazeOvidiu Panait
Add a basic CPU driver that retrieves information about the microblaze CPU core. cpu_ops handlers are implemented so that the "cpu" command can work properly: U-Boot-mONStR> cpu list 0: cpu@0 MicroBlaze @ 50MHz, Rev: 11.0, FPGA family: zynq7000 U-Boot-mONStR> cpu detail 0: cpu@0 MicroBlaze @ 50MHz, Rev: 11.0, FPGA family: zynq7000 ID = 0, freq = 50 MHz: L1 cache, MMU Note: cpu_ver_lookup[] and family_string_lookup[] arrays were imported from linux. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-14-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24microblaze: cache: introduce flush_dcache_range()Ovidiu Panait
Align microblaze with the other architectures and provide an implementation for flush_dcache_range(). Also, remove the microblaze exception in drivers/core/device.c. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-11-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24cpu-uclass: relocate ops pointers for CONFIG_NEEDS_MANUAL_RELOCOvidiu Panait
Relocate cpu_ops pointers when CONFIG_NEEDS_MANUAL_RELOC is enabled. The (gd->flags & GD_FLG_RELOC) check was added to make sure the reloc_done logic works for drivers that use DM_FLAG_PRE_RELOC. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-2-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24pinctrl: zynqmp: Add support for output-enable and bias-high-impedanceAshok Reddy Soma
Add support to handle 'output-enable' and 'bias-high-impedance' configurations. DT property output-enable brings out the pins from tri-state, whereas bias-high-impedance changes the pins state to tri-state. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/1a02cd41d183d397ebce23c497178281c7286692.1655286745.git.michal.simek@amd.com
2022-06-24serial: Setup serial base and freq for zynq/zynqmpMichal Simek
Setup default values for debug console, base address and frequency. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/ce93efd3ed67aa6390810ce0b79e0d00e7c36b4b.1652871485.git.michal.simek@amd.com
2022-06-24net: xilinx: axi_emaclite: Use shared MDIO bus support for axi emaclite driverT Karthik Reddy
CONFIG_DM_ETH_PHY enables support to utilize generic ethernet phy framework. Though if ethernet PHY node is in other ethernet node, it will use shared MDIO to access the PHY of other ethernet. Move ethernet print info statement from plat function to probe function, as phyaddr is not enumerated when CONFIG_DM_ETH_PHY is enabled. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/93e11ccca56b6e52b2dcc283d08d5042537f828f.1652181968.git.michal.simek@amd.com
2022-06-24net: xilinx: axi_emac: Use shared MDIO bus support for axi emac driverT Karthik Reddy
CONFIG_DM_ETH_PHY enables support to utilize generic ethernet phy framework. Though if ethernet PHY node is in other ethernet node, it will use shared MDIO to access the PHY of other ethernet. Move ethernet print info statement from plat function to probe function, as phyaddr is not enumerated when CONFIG_DM_ETH_PHY is enabled. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/ecfec78234233fefdc172c141c207b2d78ef70c5.1652181968.git.michal.simek@amd.com
2022-06-23Merge branch '2022-06-23-scmi-optee-and-smccc-updates' into nextTom Rini
This consists of two slightly related series. For the first, to quote the author: This series implements 2 features in driver/firmware/scmi. First, a single change adds support for SCMI OP-TEE transport to use OP-TEE native shared memory. See the 1st patch in this series: "firmware: scmi: optee: use TEE shared memory for SCMI messages". Then come changes for supporting multi-channel in the SCMI drivers. I've split the implementation in 11 several small incremental changes in the hope it helps the review. Few minor fixup commits are also inserted in the series. And the second series implements some smccc improvements.
2022-06-23drivers: rng: add smccc trng driverEtienne Carriere
Adds random number generator driver using Arm SMCCC TRNG interface to get entropy bytes from secure monitor. The driver registers as an Arm SMCCC feature driver to allow PSCI driver to bind a device for when secure monitor exposes RNG support from Arm SMCCC TRNG interface. Cc: Sughosh Ganu <sughosh.ganu@linaro.org> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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