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2023-08-03net: mediatek: add support for MediaTek MT7988 SoCWeijie Gao
This patch adds support for MediaTek MT7988. MT7988 features MediaTek NETSYS v3, including three GMACs, and two of them supports 10Gbps USXGMII. MT7988 embeds a MT7531 switch (not MCM) which supports accessing internal registers through MMIO instead of MDIO. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2023-08-03net: mediatek: add support for NETSYS v3Weijie Gao
This patch adds support for NETSYS v3 hardware. Comparing to NETSYS v2, NETSYS v3 has three GMACs. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2023-08-03net: mediatek: add USXGMII supportWeijie Gao
This patch adds support for USXGMII of SoC. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2023-08-03net: mediatek: add support for GMAC/USB3 PHY mux mode for MT7981Weijie Gao
MT7981 has its GMAC2 PHY shared with USB3. To enable GMAC2, mux register must be set to connect the SGMII phy to GMAC2. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2023-08-03net: mediatek: add support for SGMII 1Gbps auto-negotiation modeWeijie Gao
Existing SGMII support of mtk-eth is actually a MediaTek-specific 2.5Gbps high-speed SGMII (HSGMII) which does not support auto-negotiation mode. This patch adds SGMII 1Gbps auto-negotiation mode and rename the existing HSGMII to 2500basex. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2023-08-03net: mediatek: add missing static qualifierWeijie Gao
mt7531_mmd_ind_read and mt753x_switch_init are defined without static. Since they're not used outside this file, we should add them back. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> fixup to add static qualifier
2023-08-03net: mediatek: fix direct MDIO clause 45 access via SoCWeijie Gao
The original direct MDIO clause 45 access via SoC is missing the data output. This patch adds it back to ensure MDIO clause 45 can work properly for external PHYs. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2023-08-03net: mediatek: optimize the switch reset delay wait timeWeijie Gao
Not all switches requires 1 second delay after deasserting reset. MT7531 requires only maximum 200ms. This patch defines dedicated reset wait time for each switch chip, and will significantly improve the boot time for boards using MT7531. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2023-08-03net: mediatek: connect switch to PSE only when starting eth is requestedWeijie Gao
So far the switch is initialized in probe stage and is connected to PSE unconditionally. This will cause all packets being flooded to PSE and may cause PSE hang before entering linux. This patch changes the connection between switch and PSE: - Still initialize switch in probe stage, but disconnect it with PSE - Connect switch with PSE on eth start - Disconnect on eth stop Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2023-08-03pinctrl: mediatek: add pinctrl driver for MT7988 SoCWeijie Gao
This patch adds pinctrl and gpio support for MT7988 SoC Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2023-08-03pinctrl: mediatek: add pinmux_set ops supportWeijie Gao
This patch adds pinmux_set ops for mediatek pinctrl framework Signed-off-by: Sam Shih <sam.shih@mediatek.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2023-08-03pinctrl: mediatek: fix the return value in driving configuration functionsWeijie Gao
The original mediatek pinctrl functions for driving configuration 'mtk_pinconf_drive_set_*' do not return -ENOSUPP even if input parameters are not supported. This patch fixes the return value in those functions. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2023-08-03pinctrl: mediatek: convert most definitions to constWeijie Gao
There exists a situation of the mediatek pinctrl driver that may return wrong pin function value for the pinmux driver: - All pin function arrays are defined without const - Some pin function arrays contain all-zero value, e.g.: static int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, }; - These arrays will be put into .bss section during compilation - .bss section has no "a" attribute and does not exist in the final binary file after objcopy. - FDT binary blob is appended to the u-boot binary, which occupies the .bss section. - During board_f stage, .bss has not been initialized, and contains the data of FDT, which is not full-zero data. - pinctrl driver is initialized in board_f stage, and it will get wrong data if another driver is going to set default pinctrl. Since pinmux information and soc data are only meant to be read-only, thus should be declared as const. This will force all pinctrl data being put into .rodata section. Since .rodata has "a" attribute, even the all-zero data will be allocated and filled with correct value in to u-boot binary. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2023-08-03clk: mediatek: add clock driver support for MediaTek MT7988 SoCWeijie Gao
This patch adds clock driver support for MediaTek MT7988 SoC Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2023-08-03pwm: mtk: add support for MediaTek MT7988 SoCWeijie Gao
This patch adds PWM support for MediaTek MT7988 SoC. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2023-08-03i2c: mediatek: fix I2C usability for MT7981Weijie Gao
MT7981 actually uses MediaTek I2C controller v3 instead of v1. This patch adds support for I2C controller v3 fix fixes the I2C usability for MT7981. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2023-08-03reset: mediatek: check malloc return valaue before useWeijie Gao
This patch add missing return value check for allocating the driver's private data. -ENOMEM will be returned if malloc() fails. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2023-08-03serial: mtk: initial priv data before usingWeijie Gao
This patch ensures driver private data being fully initialized in _debug_uart_init which is not covered by .priv_auto ops. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> Reviewed-by: Stefan Roese <sr@denx.de>
2023-08-03spi: mtk_spim: clear IRQ enable bitsWeijie Gao
In u-boot we don't use IRQ. Instead, we poll busy bit in SPI_STATUS. However these IRQ enable bits may be set in previous boot stage (BootROM). If we leave these bits not cleared, although u-boot has disabled IRQ and nothing will happen, the linux kernel may encounter panic during initializing the spim driver due to IRQ event happens before IRQ handler is properly setup. This patch clear IRQ bits to prevent this from happening. Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-08-03spi: mtk_spim: get spi clk rate only onceWeijie Gao
We don't really need to switch clk rate during operating SPIM controller. Get clk rate only once at driver probing. Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-08-03board: mediatek: update config headersWeijie Gao
Remove unused information from include/configs/mtxxxx.h Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2023-08-02net: rtl8169: Add one device ID 0x8161Minda Chen
Add rtl8169 NIC device ID and reorder the device ID. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-02net: rtl8169: Fix DMA minimal aligned compile warning in RISC-VMinda Chen
For RISC-V architeture, hardware maintain the dcache coherency. Software do not flush the cache. So even cache-line size larger than descriptor size, driver can work. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-02net: rtl8169: Fix compile warning in rtl8169Minda Chen
While compiling rtl8169.c, There are many "make pointer from integer without a cast" compile warnings. fix them with adding cast. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-02starfive: pci: Add StarFive JH7110 pcie driverMason Huo
Add pcie driver for StarFive JH7110, Also add PLDA PCIe controller common driver functions. Several devices are tested: a) M.2 NVMe SSD b) Realtek 8169 Ethernet adapter. Signed-off-by: Mason Huo <mason.huo@starfivetech.com> Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Acked-by: Pali Rohár <pali@kernel.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-02i2c: designware: Add Kconfig for designware_i2c_pci.cMinda Chen
As the Designware_i2c_pci.c uses ACPI APIs, If some SoCs (StarFive JH7110) contain Designware i2c and PCI but do not use ACPI, This file cannot be compiled. So add a new Kconfig for designware_i2c_pci.c, which depends on ACPIGEN Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-01Merge tag 'x86-pull-20230801' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-x86 - MTRR fixes for x86 boards - Add a little more info to 'cbsysinfo' command
2023-08-01Merge tag 'video-20230801' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-video - dm video cosmetic style fix - bochs: remove the x86 limitation - correct kconfig text for PCI default FB size - kconfig: drop the superfluous PCI dependency - set up default FB size for Bochs
2023-08-01Merge https://source.denx.de/u-boot/custodians/u-boot-marvellTom Rini
- i2c-gpio: Correctly handle new {sda, scl}-gpios bindings (Chris) - mvebu: x240: Use i2c-gpio instead of built in controller (Chris)
2023-08-01drivers: video: tidss: tidss_drv: Use kconfig VIDEO_REMOVE to remove videoNikhil M Jain
Perform removal of DSS if kconfigs VIDEO_REMOVE or SPL_VIDEO_REMOVE is set by user. Otherwise if above Kconfigs are not selected, it is assumed that user wants splash screen to be displayed until linux kernel boots up. In such scenario, leave the power domain of DSS as "on" so that splash screen stays intact until kernel boots up. Signed-off-by: Nikhil M Jain <n-jain1@ti.com> Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
2023-08-01drivers: video: tidss: tidss_drv: Change remove methodNikhil M Jain
Change remove method of DSS video driver to disable video port instead of performing a soft reset, as soft reset takes longer duration. Video port is disabled by setting enable bit of video port to 0. Signed-off-by: Nikhil M Jain <n-jain1@ti.com> Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
2023-08-01video: bochs: Set the frame buffer size per configurationBin Meng
At present the uclass stored frame buffer size is set to a hard coded value, but we can calculate the correct value based on what is configured. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # qemu-x86_64
2023-08-01video: kconfig: Set default FB size for BochsBin Meng
Set up a default frame buffer size of 8MiB for Bochs for non-x86 architecturs as PCI is normally not enumerated before relocation on these architectures. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-01video: kconfig: Drop the superfluous dependencyBin Meng
PCI is always selected by X86 architecture hence "X86 && PCI" does not make it better. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # qemu-x86_64
2023-08-01video: kconfig: Fix wrong text for the PCI default FB sizeBin Meng
There is an example in the VIDEO_PCI_DEFAULT_FB_SIZE help text to tell people how to calculate its value but the resolution given does not match the value. Fix it. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-01video: bochs: Remove the x86 dependencyBin Meng
Now that the driver is legacy free, remove the x86 dependency so that it can be used on non-x86 architectures. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # qemu-x86_64
2023-08-01video: bochs: Avoid using IO instructions to access VGA IO portBin Meng
At present the driver uses IO instructions to access the legacy VGA IO ports, which unfortunately limits the driver to work only on x86. It turns out the IO instruction is not necessary as Bochs VGA card remaps the legacy VGA IO ports (0x3c0 -> 0x3df) to its memory mapped register space from offset 0x400. Update the driver to use MMIO access for VGA IO port. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # qemu-x86_64
2023-08-01video: bochs: Drop the useless argument of bochs_vga_write()Bin Meng
bochs_vga_write() takes 'index' as one argument, but never uses it. While we are here, use macros instead of magic numbers for the VGA IO port register name and value. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # qemu-x86_64
2023-08-01video: bochs: Drop inclusion of <asm/mtrr.h>Bin Meng
The driver does not call any MTRR APIs. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # qemu-x86_64
2023-08-01dm: video: Cosmetic style fixBin Meng
Some coding convention fixes for video_post_bind(). Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # qemu-x86_64
2023-08-01video: vesa: Use mtrr_set_next_var() for graphics memoryBin Meng
At present this uses mtrr_add_request() & mtrr_commit() combination to program the MTRR for graphics memory. This usage has two major issues as below: - mtrr_commit() will re-initialize all MTRR registers from index 0, using the settings previously added by mtrr_add_request() and saved in gd->arch.mtrr_req[], which won't cause any issue but is unnecessary - The way such combination works is based on the assumption that U-Boot has full control with MTRR programming (e.g.: U-Boot without any blob that does all low-level initialization on its own, or using FSP2 which does not touch MTRR), but this is not the case with FSP. FSP programs some MTRRs during its execution but U-Boot does not have the settings saved in gd->arch.mtrr_req[] and when doing mtrr_commit() it will corrupt what was already programmed previously. Correct this to use mtrr_set_next_var() instead. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-01video: ivybridge: Use mtrr_set_next_var() for graphics memoryBin Meng
At present this uses mtrr_add_request() & mtrr_commit() combination to program the MTRR for graphics memory. This usage has two major issues as below: - mtrr_commit() will re-initialize all MTRR registers from index 0, using the settings previously added by mtrr_add_request() and saved in gd->arch.mtrr_req[], which won't cause any issue but is unnecessary - The way such combination works is based on the assumption that U-Boot has full control with MTRR programming (e.g.: U-Boot without any blob that does all low-level initialization on its own, or using FSP2 which does not touch MTRR), but this is not the case with FSP. FSP programs some MTRRs during its execution but U-Boot does not have the settings saved in gd->arch.mtrr_req[] and when doing mtrr_commit() it will corrupt what was already programmed previously. Correct this to use mtrr_set_next_var() instead. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-01video: broadwell: Use mtrr_set_next_var() for graphics memoryBin Meng
At present this uses mtrr_add_request() & mtrr_commit() combination to program the MTRR for graphics memory. This usage has two major issues as below: - mtrr_commit() will re-initialize all MTRR registers from index 0, using the settings previously added by mtrr_add_request() and saved in gd->arch.mtrr_req[], which won't cause any issue but is unnecessary - The way such combination works is based on the assumption that U-Boot has full control with MTRR programming (e.g.: U-Boot without any blob that does all low-level initialization on its own, or using FSP2 which does not touch MTRR), but this is not the case with FSP. FSP programs some MTRRs during its execution but U-Boot does not have the settings saved in gd->arch.mtrr_req[] and when doing mtrr_commit() it will corrupt what was already programmed previously. Correct this to use mtrr_set_next_var() instead. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-07-31Merge tag 'u-boot-rockchip-20230731' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-rockchip - Update dwc3 generic driver and update support for rk3568/rk3328; - Add boards: rk3566: Pine64 Quartz64-A/B, SOQuartz on Model A/Blade/CM4-IO rk3568: Radxa E25 Carrier Board rk3588: Radxa ROCK5A - Fixes and updates for chromebook veryon/jerry/speedy; - SPI support fixes for rk3399/rk3568/rk3588; - rk3588 usbdp phy support; - dts and config updates for different boards;
2023-07-31clk: rockchip: rk3328: Handle usb480m phy clockJagan Teki
Handle USB480M clock ID in set_rate() and set_parent() to allow the dt assigned-clocks and assigned-clock-parents work on rk3328.dtsi Cc: Lukasz Majewski <lukma@denx.de> Cc: Sean Anderson <seanga2@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31phy: rockchip-inno-usb2: Add USB2 PHY for RK3328Jagan Teki
USB2.0 Host and OTG controllers in RK3328 are using USB2PHY. Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Xavier Drudis Ferran <xdrudis@tinet.cat> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31usb: dwc3-generic: Restrict single ctrl node for RK3328Jagan Teki
Like Rockchip RK3568, the RK3328 also have single node to represent the glue and ctrl for USB 3.0. So, use the driver data to use single ctrl for RK3328 DWC3. Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31power: regulator: rk8xx: Add 500us delay after LDO regulator is enabledJonas Karlman
A quick power cycle of a LDO regulator during dw-mmc signal voltage change has shown that SD-card does not always get recognized. Linux driver use an enable_time of 400us for LDO regulators. Apply a 500us delay when a LDO regulator is enabled to fix possible issues. Fixes: 94afc1cb466a ("power: regulator: rk8xx: update the driver for rk808 and rk818") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: elaine.zhang<elaine.zhang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31i2c: i2c-gpio: Correctly handle new {sda, scl}-gpios bindingsChris Packham
gpio_request_list_by_name() returns the number of gpios requested. Notably it swallows the underlying -ENOENT when the "gpios" property does not exist. Update the i2c-gpio driver to check for ret == 0 before trying the new sda-gpios/scl-gpios properties. Signed-off-by: Chris Packham <judge.packham@gmail.com>
2023-07-31usb: dwc3-generic: Add rk3568 supportJonas Karlman
RK3568 share glue and ctrl in a single node. Use glue_get_ctrl_dev to return the glue node as the ctrl node. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de>
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