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Fix some compilation warning in the old DDR training code.
Signed-off-by: Marek Behún <kabel@kernel.org>
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Import DDR training code from commit 1b69ce2fc0ec ("arm: mvebu:
ddr3_debug: remove self assignments") into
drivers/ddr/marvell/a38x/old/. The code is not used yet.
Explanation:
Since 2019, on some Turris Omnia boards we have been having problems
with newer versions of Marvell's DDR3 training code for Armada 38x,
which is ported from mv-ddr-marvell [1] to U-Boot into the
drivers/ddr/marvell/a38x/ directory:
- sometimes the DDR3 training fails on some older boards, sometime it
fails on some newer boards
- other times it succeeds, but some boards experience crashes of the
operating system after running for some time.
Using the stock version of Turris Omnia's U-Boot from solved these
issues, but this solution was not satisfactory, since we wanted
features from new U-Boot.
Back in 2020-2022 we have spent several months trying to debug the
issues, working with Marvell, on our own, and also with U-Boot
community, but these issues persist still.
One solution we used back in 2019 was a "hybrid U-Boot": the SPL part
(containing the DDR3 training code) was taken from the stock version,
while the proper part was current U-Boot at the time. This solution also
has its drawbacks, of which the main one is the need to glue binaries
from two separate builds.
Since then there have been some more changes to the DDR3 training code
in upstream mv-ddr-marvell that have been ported to U-Boot. We have
provided our users experimental builds of U-Boot in the TurrisOS so that
they could try upgrading the firmware and let us know if those problems
still exist. And they do.
We do not have the time nor manpower to debug this problem and fix it
properly. Marvell was also no able to provide a solution to this,
probably because they do not have the manpower as well.
I have therefore come up with this "not that pretty" solution: take the
DDR3 training code from an older version of U-Boot that is known to
work, put it into current U-Boot under old/ subdirectory within
drivers/ddr/marvell/a38x/, build into the SPL binary both the old and
new versions and make it possible to select the old version via an env
variable.
[1] https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell
Signed-off-by: Marek Behún <kabel@kernel.org>
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reduce binary size
Allow compiling with immutable debug settings:
- DEBUG_LEVEL is always set to DEBUG_LEVEL_ERROR
- register dumps are disabled
This can save around 10 KiB of space in the resulting binary, which is a
lot in U-Boot SPL.
Signed-off-by: Marek Behún <kabel@kernel.org>
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and make them static
The variables is_validate_window_per_if, is_validate_window_per_pup,
sweep_cnt and is_run_leveling_sweep_tests are only used if
DDR_VIEWER_TOOL macro is defined, so define them only in that case.
Make them static since they are only used in ddr3_debug.c.
Signed-off-by: Marek Behún <kabel@kernel.org>
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The variables is_default_centralization, is_tune_result and
is_bist_reset_bit are never used.
Signed-off-by: Marek Behún <kabel@kernel.org>
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won't print anything
Return from ddr3_tip_print_log() early if we won't print anything
anyway.
This way the compiler can optimize away the VALIDATE_IF_ACTIVE() calls
in the for-loop, so if the SILENT_LIB macro is defined, no code is
generated for the rest of the function, which saves some space.
Signed-off-by: Marek Behún <kabel@kernel.org>
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Timer value is a 16 bits calculated from the wanted timeout and the
system clock. On powerpc/8xx, a timeout of 2s gives a value which
is over U16_MAX so U16_MAX shall be used. But the calculation is
casted to u16 so at the end the result is 63770 instead of 128906.
So the timer gets loaded with 63770 instead of 65535. It is not
a big difference in that case, but lets make the code correct and
cast to u32 instead of u16.
Fixes: 26e8ebcd7cb7 ("watchdog: mpc8xxx: Make it generic")
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
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This patch adds support for Intel Foxville I226
devices LM,V,I,K in e1000 driver.
Signed-off-by: Marjolaine Amate <marjolaine.amate@odyssee-systemes.fr>
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https://source.denx.de/u-boot/custodians/u-boot-snapdragon
Various minor fixes and improvements:
* Fix Qualcomm SPMI v5 support
* Move default environment to a file
* Add support for special pins (e.g ufs/mmc reset/data pins)
* IPQ moves to OF_UPSTREAM and receives some cleanup and MAINTAINERS
changes
* Add a reset driver for devices without PSCI
* msm8916 USB clock improvements for mobile devices
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Commit ee1d8aa5ecf7 ("spmi: msm: support controller version 7") broke
support for channels > 128 on v5 controllers, resulting in some
peripherals (like the power button / pon) working but others (like
gpios) reading bogus data.
Correct max_channels for v5 controllers.
Fixes: ee1d8aa5ecf7 ("spmi: msm: support controller version 7")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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Most devices have buttons exposed via the PMIC, the button polling
therefore triggers a log spam if debug logging is enabled.
Demote these to debug() so that they aren't printed unless LOG_DEBUG is
defined explicitly for this file.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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Add the special pins configuration data to allow setup the bias
of the UFS and SDCard pins on the SM8650 SoC.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
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Add the special pins configuration data to allow setup the bias
of the UFS and SDCard pins on the SM8550 SoC.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
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Use the previously introduced msm_special_pin_data to setup the special
pins configuration if the SoC driver have them specified.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
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Add support for bias-pull-down as an alternate of bias-pull-up.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
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I2C clocks are not initialized by the SBL, so lets add support for clocks
required by both of the QUP I2C controllers.
BLSP1 AHB clock is already initialized by SBL, but QUP I2C driver is
requesting it so we have to add it to the enable list.
Based off QCS404 clock driver.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
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Number of Qualcomm ARMv7 SoC-s did not use PSCI but rather used PSHOLD
(Qualcomm Power Supply Hold Reset) bit to trigger reset or poweroff.
Qualcomm IPQ40XX is one of them, so provide a simple sysreset driver based
on the upstream Linux one, it is DT compatible as well.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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This seems to be necessary on my samsung-a5. Without this patch, the
first access of EHCI registers causes a bus stall and subsequent reset.
I am unsure why this wasn't already necessary for db410c, perhaps those
clocks are already enabled on boot.
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Sam Day <me@samcday.com>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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The newer "register map for simple gate clocks" support added for qcom
clocks is used. As a result gcc_apq8016 now has a mixture of the old and
new styles. I didn't (and still don't!) feel comfortable enough in this
area to update the existing code.
Signed-off-by: Sam Day <me@samcday.com>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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Use existing nvidia,head device tree property to get DC controller id.
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
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Jiaxun Yang <jiaxun.yang@flygoat.com> says:
Hi all,
This series enabled qemu-xtensa board.
For dc232b CPU it needs to be built with toolchain[1].
This is a side product of me investigating architectures
physical address != virtual address in U-Boot. Now we can
get it covered under CI and regular tests.
VirtIO devices are not working as expected, due to U-Boot's
assumption on VA == PA everywhere, I'm going to get this fixed
later.
My Xtensa knowledge is pretty limited, Xtensa people please
feel free to point out if I got anything wrong.
Thanks
[1]: https://github.com/foss-xtensa/toolchain/releases/download/2020.07/x86_64-2020.07-xtensa-dc232b-elf.tar.gz
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Implement various CPU related functions.
I'm actually just using it to get cpu clock frequency.
Tested-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
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Add xtensa semihosting driver.
It can't use regular semihosting driver as Xtensa's has it's own
semihosting ABI.
Tested-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
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This part of driver model is a little subtle, so add some more comments
to promote better understanding.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Tom Rini <trini@konsulko.com> says:
Prior to this series we had some de-facto required cache functions that
were either unimplemented on some architectures or differently named.
This would lead in some cases to having multiple "weak" functions
available as well. Rework things so that an architecture must provide
these functions and it is up to that architecture if a "weak" default
function makes sense, or not.
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The implementation of icache_invalid appears to be doing what other
architectures call invalidate_icache_all so rename to match.
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
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It should read "in SPL" and not "wuth SPL".
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Prior to that, seeing the debug() messages required to enable DM_DEBUG
which defines DEBUG (and then _DEBUG) which in turn makes failing
assert() calls reset U-Boot which isn't necessarily what is desired.
Instead, let's migrate to dm_warn which is using log_debug when unset or
log_warn when set.
While at it, reword the DM_DEBUG symbol in Kconfig to explain what it
now actually does.
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
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outp always point to an unsigned type in ofnode_read_u* functions but
the format specifier is currently always using signed type.
This is an issue since the signed type can only contain half of the
unsigned type values above 0.
However, this now breaks another usecase. Indeed,
ofnode_read_s32_default is actually passing an s32 but it'll be printed
as a u32 instead. But since the function is called u32, it makes more
sense to have it print an unsigned value.
This was discovered because arm,smc-id = <0x82000010>; on RK3588S is
above the max signed value and therefore would return a negative signed
decimal value instead of its proper unsigned one.
Fixes: fa12dfa08a7b ("dm: core: support reading a single indexed u64 value")
Fixes: 4bb7075c830c ("dm: core: support reading a single indexed u32 value")
Fixes: 7e5196c409f1 ("dm: core: Add ofnode function to read a 64-bit int")
Fixes: 9e51204527dc ("dm: core: Add operations on device tree references")
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
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A driver can have multiple compatible. When the id->compatible matches
for that driver, the first compatible supported by the driver is
currently returned, which gives the following confusing message:
- found match at 'rk3588_syscon': 'rockchip,rk3588-sys-grf' matches 'rockchip,rk3588-pmugrf'
Considering that the compatible passed in argument is necessarily the
one that exactly matched to enter this code path, there's no need to do
some elaborate logic, just print the driver name and the compatible
passed in argument.
Fixes: d3e773613b6d ("dm: core: Use U-Boot logging instead of pr_debug()")
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
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With a recent change, regulators_enable_boot_on() returns an error if a
regulator is already set. Check for and handle this situation.
Fixes: d99fb64a98a power: regulator: Only run autoset once for each regulator
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
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This should use the driver macros so that the driver appears in the
linker list. Fix this.
Fixes: 8587839f19d ("pinctrl: meson: add axg support")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240623203033.1566505-8-sjg@chromium.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
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Drop this useless usb.h and now make dwc3_meson_g12a_force_mode
static since only used in the dwc3-meson-g12a.c file.
Reviewed-by: Marek Vasut <marex@denx.de>
Link: https://lore.kernel.org/r/20240620-u-boot-usb-gxl-phy-set-mode-v2-5-b81c027bc02c@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
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Drop this useless usb-gx.h and now make dwc3_meson_gxl_force_mode
static since only used in the dwc3-meson-gxl.c file.
Reviewed-by: Marek Vasut <marex@denx.de>
Link: https://lore.kernel.org/r/20240620-u-boot-usb-gxl-phy-set-mode-v2-4-b81c027bc02c@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
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Remove the public phy_meson_gxl_usb2_set_mode and move
the implementation in the the set_mode callback.
Reviewed-by: Marek Vasut <marex@denx.de>
Link: https://lore.kernel.org/r/20240620-u-boot-usb-gxl-phy-set-mode-v2-3-b81c027bc02c@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
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Use the PHY set_mode call instead of calling directly in the
PHY shared function.
Reviewed-by: Marek Vasut <marex@denx.de>
Link: https://lore.kernel.org/r/20240620-u-boot-usb-gxl-phy-set-mode-v2-2-b81c027bc02c@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
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Implement set_mode callback by calling the current public
function, use a temporary function name that will be removed
when the public phy_meson_gxl_usb2_set_mode is finally removed
in a following change.
Reviewed-by: Marek Vasut <marex@denx.de>
Link: https://lore.kernel.org/r/20240620-u-boot-usb-gxl-phy-set-mode-v2-1-b81c027bc02c@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
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Prepare v2024.07-rc5
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Jayesh Choudhary <j-choudhary@ti.com> says:
Hello there,
This series add the U-Boot support for our new platform of K3-SOC
family - J722S-EVM which is a superset of AM62P. It shares the same
memory map and thus the nodes are being reused from AM62P includes
instead of duplicating the definitions.
Some highlights of J722S SoC (in addition to AM62P SoC features) are:
- Two Cortex-R5F for Functional Safety or general-purpose usage and
two C7x floating point vector DSP with Matrix Multiply Accelerator
for deep learning.
- Vision Processing Accelerator (VPAC) with image signal processor
and Depth and Motion Processing Accelerator (DMPAC).
- 7xUARTs, 3xSPI, 5xI2C, 2xUSB2, 2xCAN-FD, 3xMMC and SD, GPMC for
NAND/FPGA connection, OSPI memory controller, 5xMcASP for audio,
4xCSI-RX for Camera, 1 PCIe Gen3 controller, USB3.0 eCAP/eQEP,
ePWM, among other peripherals.
TRM: <https://www.ti.com/lit/zip/sprujb3>
Schematics: <https://www.ti.com/lit/zip/sprr495>
Boot test log:
<https://gist.github.com/Jayesh2000/0313e58fde377f877a9a8f1acc2579ef>
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Include the static DMA channel data for using DMA at SPL stage
for J722S SoC family.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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The J722S family of SoCs uses the same DDR controller as found on the
AM62A family. Enable this option when building for the J722S family.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
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Include the clock and lpsc tree files needed for the wkup spl to
initialize the proper PLLs and power domains to boot the SoC.
Reviewed-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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Add the power domain platform data entries in alphabetical order.
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
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Use IS_ENABLED macro for the platform clock-data list and add them
in alphabetical order.
Reviewed-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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Include the part number for TI's j722s family of SoC
to identify it during boot.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
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Add JTAG_ID_PARTNO_* in alphabetical order.
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
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For some reason none of these debug prints have newlines, resulting in a
"fun" surprise when attempting to debug this driver.
The other parts of the dwc3 driver have newlines, add them here too (and
fix some minor nearby indent issues to make checkpatch happy).
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Marek Vasut <marex@denx.de>
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The message 'No working controllers found' provides no clue that this
refers to USB controllers.
Provide a message that refers to USB.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
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This commit adds support for a property 'phy-reset-gpios' to reset PHY
chipset.
Signed-off-by: Heesub Shin <heesub@gmail.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
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