summaryrefslogtreecommitdiff
path: root/drivers
AgeCommit message (Collapse)Author
2022-06-23firmware: scmi: mailbox transport: implement multi-channelEtienne Carriere
Updates SCMI mailbox transport driver to get SCMI channel reference at initialization and use when posting SCMI messages. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-06-23firmware: scmi: add multi-channel supportEtienne Carriere
Adds resources for SCMI protocols to possibly use a dedicated SCMI channel instead of the default channel allocated by the SCMI agent during initialization. As per DT binding documentation, some SCMI transports can define a specific SCMI communication channel for given SCMI protocols. It allows SCMI protocols to pass messages concurrently each other. This change introduces new scmi agent uclass API function devm_scmi_of_get_channel() for SCMI drivers probe sequences to get a reference to the SCMI channel assigned to its related SCMI protocol. The function queries the channel reference to its SCMI transport driver through new scmi agent uclass operator .of_get_channel that uses Device Tree information from related SCMI agent node. Operator .of_get_channel returns a reference to the SCMI channel assigned to SCMI protocol used by the caller device. SCMI transport drivers that do not support multi-channel are not mandated to register this operator. When so, API function devm_scmi_of_get_channel() returns NULL and SCMI transport driver are expected to retrieve by their own means the reference to the unique SCMI channel, for example using platform data as these drivers currently do in U-Boot source tree. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-06-23firmware: scmi: factorize scmi transport look upEtienne Carriere
Defines local helper function find_scmi_transport_device() with the instructions to find the SCMI transport device from a SCMI protocol device. Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-06-23firmware: scmi: prepare uclass to pass channel referenceEtienne Carriere
Changes SCMI transport operator ::process_msg to pass the SCMI channel reference provided by caller SCMI protocol device. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-06-23firmware: scmi: prepare scmi uclass API to multi-channelEtienne Carriere
Changes SCMI driver API function devm_scmi_process_msg() to add an SCMI channel reference argument for when SCMI agent supports SCMI protocol specific channels. First argument of devm_scmi_process_msg() is also change to point to the caller SCMI protocol device rather than its parent device (the SCMI agent device). The argument is a pointer to opaque struct scmi_channel known from the SCMI transport drivers. It is currently unused and caller a pass NULL value. A later change will enable such support once SCMI protocol drivers have means to get the channel reference during initialization. Cc: Lukasz Majewski <lukma@denx.de> Cc: Sean Anderson <seanga2@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-06-23firmware: scmi: optee: fix inline description of PTA_SCMI_CMD_GET_CHANNELEtienne Carriere
Removes inaccurate inline description of OP-TEE SCMI PTA command PTA_SCMI_CMD_GET_CHANNEL. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-06-23firmware: scmi: optee: use TEE shared memory for SCMI messagesEtienne Carriere
Changes implementation when using TEE dynamically allocated shared memory to synchronize with the Linux implementation where the legacy SMT protocol cannot be used with such memory since it is expected from device mapped memory whereas OP-TEE shared memory is cached and hence should not be accessed using memcpy_toio()/memcpy_fromio(). This change implements the MSG shared memory protocol introduced in Linux [1]. The protocol uses a simplified SMT header of 32bit named MSG_SMT to carry SCMI protocol information and uses side channel means to carry exchanged buffer size information, as TEE invocation API parameters when used in the SCMI OP-TEE transport. Link: [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=f301bba0ca7392d16a6ea4f1d264a91f1fadea1a Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-06-22misc: nuvoton: Add NPCM7xx otp controller driverJim Liu
Add Nuvoton BMC npcm750 otp driver Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-06-22crypto: nuvoton: Add NPCM7xx SHA driverJim Liu
add nuvoton BMC npcm750 SHA driver Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-06-22crypto: nuvoton: Add NPCM7xx AES driverJim Liu
add nuvoton BMC npcm750 AES driver Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-06-22spi: gxp_spi: Add GXP SPI controller driverNick Hawkins
The GXP supports 3 separate SPI interfaces to accommodate the system flash, core flash, and other functions. The SPI engine supports variable clock frequency, selectable 3-byte or 4-byte addressing and a configurable x1, x2, and x4 command/address/data modes. The memory buffer for reading and writing ranges between 256 bytes and 8KB. This driver supports access to the core flash. Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
2022-06-22timer: gxp: Add HPE GXP timer supportNick Hawkins
Add support for the HPE GXP SOC timer. The GXP supports several different kinds of timers but for the purpose of this driver there is only support for the General Timer. The timer has a 1us resolution and is 56 bits. Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
2022-06-20Merge branch 'master' into nextTom Rini
Merge in v2022.07-rc5.
2022-06-20Merge tag 'u-boot-stm32-20220620' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-stm into next - Add STM32MP13 SoCs support with associated board STM32M135F-DK - Correct livetree support in stm32mp1 boards - Activate livetree for stm32mp15 DHSOM boards
2022-06-20mmc: fsl_esdhc: Add new config option for default fallback modePali Rohár
Currently default fallback SDHC mode is 1-bit. Add new config option CONFIG_SYS_FSL_ESDHC_DEFAULT_BUS_WIDTH to allow specifying default fallback mode. This is useful e.g. for SPL builds which loads other parts from SD card during boot process. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-06-20mmc: fsl_esdhc: Set fallback mode to 1-bitPali Rohár
8-bit mode is not supported by SD cards and on P2020 are four SDHC pins shared with SPI (so if P2020 board have also SPI then only 4-bit SDHC mode is provided). So 8-bit SDHC mode is really bad default. When max bus width is not provided then set mode to 1-bit. This mode is supported by all cards, so it is the best option for fallback mode. Also P2020 bootrom sets mode to 1-bit when booting from SD/MMC card. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-06-20mtd: rawnand: fsl_elbc: Fix DM support in DTS code pathPali Rohár
For proper DM support it is required to fill also mtd->dev member. Otherwise DM would not see nand device at all. Signed-off-by: Pali Rohár <pali@kernel.org>
2022-06-20arm: layerscape: Add sfp driverSean Anderson
This adds a driver for the Security Fuse Processor (SFP) present on LS1012A, LS1021A, LS1043A, and LS1046A processors. It holds the Super-Root Key (SRK), One-Time-Programmable Master Key (OTPMK), and other "security" related fuses. Similar devices (sharing the same name) are present on other processors, but for the moment this just supports the LS2 variants. The mirror registers are loaded during power-on reset. All mirror registers must be programmed or read at once. Because of this, `fuse prog` will program all fuses, even though only one might be specified. To prevent accidentally burning through all your fuse programming cycles with something like `fuse prog 0 0 A B C D`, we limit ourselves to one programming cycle per reset. Fuses are numbered based on their address. The fuse at 0x1e80200 is 0, the fuse at 0x1e80204 is 1, etc. The TA_PROG_SFP supply must be enabled when programming fuses, but must be disabled when reading them. Typically this supply is enabled by inserting a jumper or by setting a register in the board's FPGA. I've also added support for using a regulator. This could be helpful for automatically issuing the FPGA write, or for toggling a GPIO controlling the supply. I suggest using the following procedure for programming: 1. Override the fuses you wish to program => fuse override 0 2 A B C D 2. Inspect the values and ensure that they are what you expect => fuse sense 0 2 4 3. Enable TA_PROG_SFP 4. Issue a program command using OSPR0 as a dummy. Since it contains the write-protect bit you will usually want to write it last anyway. => fuse prog 0 0 0 5. Disable TA_PROG_SFP 6. Read back the fuses and ensure they are correct => fuse read 0 2 4 Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-06-17Merge commit '32e0379143b433e29d76404f5f4c279067e48853' of ↵Tom Rini
https://github.com/tienfong/uboot_mainline
2022-06-17stm32mp1: fix reference for STMicroelectronicsPatrick Delaunay
Replace reference to the correct name STMicroelectronics Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17misc: stm32mp13: introduce STM32MP13 RCC driverPatrick Delaunay
Add the MISC RCC driver for STM32MP13, and bind it to the RCC reset driver, required for initial support. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Acked-by: Sean Anderson <seanga2@gmail.com> Change-Id: Ida11c15462caf140f87b1e3239efa2b8a689acb9
2022-06-17clk: Add directory for STM32 clock driversPatrick Delaunay
Add a directory in drivers/clk to regroup the clock drivers for all STM32 Soc with CONFIG_ARCH_STM32 (MCUs with cortex M) or CONFIG_ARCH_STM32MP (MPUs with cortex A). Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Grzegorz Szymaszek <gszymaszek@short.pl> Acked-by: Sean Anderson <seanga2@gmail.com> Change-Id: I955af307963f732167396f0157a30cf2fc91f150
2022-06-17mmc: stm32_sdmmc2: make reset property optionalPatrick Delaunay
Although not recommended, the reset property could be made optional. This way the driver will probe even if no reset property is provided in an sdmmc node in DT. This reset is already optional in Linux. Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-06-17ram: stm32mp1: add support of STM32MP13xPatrick Delaunay
Add support for new compatible "st,stm32mp13-ddr" to manage the DDR sub system (Controller and PHY) in STM32MP13x SOC: - only one AXI port - support of 16 port output (MEMC_DRAM_DATA_WIDTH = 2) The STM32MP15x SOC have 2 AXI ports and 32 bits support. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17ddr: altera: soc64: Integer fix overflow that caused DDR size mismatchedDinesh Maniyam
Convert the constant integer to 'phys_size_t' to avoid overflow when calculating the SDRAM size. Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-17drivers: cache: ncore: Disable snoop filterDinesh Maniyam
There is hardware bug in NCORE CCU IP and it is causing an issue in the coherent directory tracking of outstanding cache lines. The workaround is disabling snoop filter. Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-17pinctrl: stm32: add support of STM32MP135Patrick Delaunay
Add support for "st,stm32mp135-pinctrl" for STM32MP13x Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-16usb: host: ehci-generic: Make resets and clocks optionalAndre Przywara
The generic EHCI binding does not *require* resets and clocks properties, and indeed for instance the Allwinner A20 SoCs does not need or define any resets in its DT. Don't easily give up if clk_get_bulk() or reset_get_bulk() return an error, but check if that is due to the DT simply having no entries for either of them. This fixes USB operation on all boards with an Allwinner A10 or A20 SoC, which were reporting an error after commit ba96176ab70e2999: ======================= Bus usb@1c14000: ehci_generic usb@1c14000: Failed to get resets (err=-2) probe failed, error -2 ======================= Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-16crypto: fsl_hash: Remove unnecessary alignment check in caam_hash()Stefan Roese
While working on an LX2160 based board and updating to latest mainline I noticed problems using the HW accelerated hash functions on this platform, when trying to boot a FIT Kernel image. Here the resulting error message: Using 'conf-freescale_lx2160a.dtb' configuration Trying 'kernel-1' kernel subimage Verifying Hash Integrity ... sha256Error: Address arguments are not aligned CAAM was not setup properly or it is faulty error! Bad hash value for 'hash-1' hash node in 'kernel-1' image node Bad Data Hash ERROR: can't get kernel image! Testing and checking with Gaurav Jain from NXP has revealed, that this alignment check is not necessary here at all. So let's remove this check completely. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Gaurav Jain <gaurav.jain@nxp.com> Cc: dullfire@yahoo.com Reviewed-by: Gaurav Jain <gaurav.jain@nxp.com>
2022-06-16Merge tag 'u-boot-imx-20220616' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20220616 ------------------- Fixes for 2022.07 + Toradex apalis-imx8 (missed in last PR) CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/12322
2022-06-16ddr: altera: Stratix10: Use phys_size_t for memory sizeTien Fong Chee
Replace with phys_size_t for all memory size variables declaration for the sake of scalability. phys_size_t is defined in /arch/arm/include/asm/types.h. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-16ddr: altera: Ignore bit[7-4] for both seq2core & core2seq handshake in HPSTien Fong Chee
Bit[7-4] for both register seq2core and core2seq handshake in HPS are not required for triggering DDR re-calibration or resetting EMIF. So, ignoring these bits just for playing it safe. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-15Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-pmicTom Rini
2022-06-15intel: n5x: ddr: update licenseTien Fong Chee
All the source code of sdram_n5x.c are from Intel, update the license to use both GPL2.0 and BSD-3 Clause because this copy of code may used for open source and internal project. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-15spi: nxp_fspi: Fix clock imbalanceMarek Vasut
The nxp_fspi_default_setup() is only ever called from nxp_fspi_probe(), where the IP clock are initially disabled. Drop the second disabling of clock to prevent clock enable/disable imbalance reported by clock core: " clk qspi_root_clk already disabled " Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-06-15mmc: fsl_esdhc_imx: Implement wait_dat0 mmc opsLoic Poulain
Implement wait_dat0 mmc ops callbac, allowing to reduce SPL boot time. Before (using grabserial): [0.000001 0.000001] U-Boot SPL 2021.04-xxxx [0.028257 0.028257] DDRINFO: start DRAM init [0.028500 0.000243] DDRINFO: DRAM rate 3000MTS [0.304627 0.276127] DDRINFO:ddrphy calibration done [0.305647 0.001020] DDRINFO: ddrmix config done [0.352584 0.046937] SEC0: RNG instantiated [0.374299 0.021715] Normal Boot [0.374675 0.000376] Trying to boot from MMC2 [1.250580 0.875905] NOTICE: BL31: v2.4(release):lf-5.10.72-2.2.0-0-g5782363f9 [1.251985 0.001405] NOTICE: BL31: Built : 08:02:40, Apr 12 2022 [1.522560 0.270575] [1.522734 0.000174] [1.522788 0.000054] U-Boot 2021.04-xxxx After: [0.000001 0.000001] U-Boot SPL 2021.04-xxxx [0.001614 0.001614] DDRINFO: start DRAM init [0.002377 0.000763] DDRINFO: DRAM rate 3000MTS [0.278494 0.276117] DDRINFO:ddrphy calibration done [0.279266 0.000772] DDRINFO: ddrmix config done [0.338432 0.059166] SEC0: RNG instantiated [0.339051 0.000619] Normal Boot [0.339431 0.000380] Trying to boot from MMC2 [0.412587 0.073156] NOTICE: BL31: v2.4(release):lf-5.15.5-1.0.0-0-g05f788b [0.414191 0.001604] NOTICE: BL31: Built : 10:35:26, Apr 6 2022 [0.700685 0.286494] [0.700793 0.000108] [0.700845 0.000052] U-Boot 2021.04-xxxx Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-06-15mmc: Add support for wait_dat0 callbackLoic Poulain
There is no wait_dat0 mmc ops, causing operations waiting for data line state change (e.g mmc_switch_voltage) to fallback to a 250ms active delay. mmc_ops still used when DM_MMC is not enabled, which is often the case for SPL. The result can be unexpectly long SPL boot time. This change adds support for wait_dat0() mmc operation. Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-06-15mmc: fix error message for unaligned erase requestPatrick Delaunay
Fix the end address in the message for unaligned erase request in mmc_berase() when start + blkcnt is aligned to erase_grp_size. for example: - start = 0x2000 - 26 - count = 26 - erase_grp_size = 0x400 Caution! Your devices Erase group is 0x400 The erase range would be change to 0x2000~0x27ff But no issue when the end address is not aligned, for example - start = 0x2000 - 2 * 26 - count = 26 - erase_grp_size = 0x400 Caution! Your devices Erase group is 0x400 The erase range would be change to 0x2000~0x23ff Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-14clk: imx8mp: use usb_core_ref for usb_root_clkAndrey Zhizhikin
Upstream commit 7a2c3be95a50 ("clk: imx8mp: Fill in DWC3 USB, USB PHY, HSIOMIX clock") added usb_core_ref for USB Controller but never set it to be used as a clock source, using rather "osc_32k" instead. This produces following boot log message: "clk_register: failed to get osc_32k device (parent of usb_root_clk)" Fix the USB controller clock source by using usb_core_ref instead of osc_32k. Fixes: 7a2c3be95a50 ("clk: imx8mp: Fill in DWC3 USB, USB PHY, HSIOMIX clock") Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Cc: Fabio Estevam <festevam@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-06-14clk: imx8mp: fix root clock names for ecspiAndrey Zhizhikin
Root clock name contained underscore, which does not match to the actual clock name. Correct the name to match what is present in the FDT. Fixes: 87f958810fcb ("clk: imx8mp: Add ECSPI clocks") Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Cc: Fabio Estevam <festevam@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: uboot-imx <uboot-imx@nxp.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-06-14phy: adin: add support for clock outputJosua Mayer
The ADIN1300 supports generating certain clocks on its GP_CLK pin, as well as providing the reference clock on CLK25_REF. Add support for selecting the clock via device-tree properties. This patch is based on the Linux implementation for this feature, which has been added to netdev/net-next.git [1]. [2] https://patchwork.kernel.org/project/netdevbpf/cover/20220517085143.3749-1-josua@solid-run.com/ Signed-off-by: Josua Mayer <josua@solid-run.com>
2022-06-14phy: adin: fix broken support for adi, phy-mode-overrideNate Drude
Currently, the adin driver fails to compile. The original patch introducing the adin driver used the function phy_get_interface_by_name to support the adi,phy-mode-override property. Unfortunately, a few days before the adin patch was accepted, another patch removed support for phy_get_interface_by_name: https://github.com/u-boot/u-boot/commit/123ca114e07ecf28aa2538748d733e2b22d8b8b5 This patch refactors adin_get_phy_mode_override, implementing the logic in the new function, ofnode_read_phy_mode, from the patch above. Signed-off-by: Nate Drude <nate.d@variscite.com> Tested-by: Josua Mayer <josua@solid-run.com> Signed-off-by: Josua Mayer <josua@solid-run.com>
2022-06-14pmic: pca9450: add DM_I2C dependencies in KconfigRasmus Villemoes
The pca9450 driver uses dm_i2c_{read,write}, which are (unsurprisingly) only available with DM_I2C. Make sure one can't create an unbuildable .config by adding proper dependencies. While here, append "in SPL" to the prompt for the SPL_ variant so it doesn't read the same as the one for the non-SPL_ variant. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-06-13arm: tegra: Update some DT compatiblesPeter Robinson
Some of the DT compatibles have changed upstream so add new DT compatibles to ensure things continue to keep working if the device trees are updated. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2022-06-13pci: tegra: Update error prints with new linesPeter Robinson
Add new lines to make errorr messages easier to read. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2022-06-10firmware: ti_sci_static_data: add static DMA chan dataVignesh Raghavendra
Add range of DMA channels available for R5 SPL usage before DM firmware is loaded. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-06-10dma: ti: Add PSIL data for AM62x DMASSVignesh Raghavendra
Add PSIL data for AM62x SoC. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-06-10arm: mach-k3: am62: Introduce autogenerated SoC dataSuman Anna
Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-06-10arm: mach-k3: Introduce the basic files to support AM62Suman Anna
The AM62 SoC family is the follow on AM335x built on K3 Multicore SoC architecture platform, providing ultra-low-power modes, dual display, multi-sensor edge compute, security and other BOM-saving integration. The AM62 SoC targets broad market to enable applications such as Industrial HMI, PLC/CNC/Robot control, Medical Equipment, Building Automation, Appliances and more. Some highlights of this SoC are: * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Pin-to-pin compatible options for single and quad core are available. * Cortex-M4F for general-purpose or safety usage. * Dual display support, providing 24-bit RBG parallel interface and OLDI/LVDS-4 Lane x2, up to 200MHz pixel clock support for 2K display resolution. * Selectable GPUsupport, up to 8GFLOPS, providing better user experience in 3D graphic display case and Android. * PRU(Programmable Realtime Unit) support for customized programmable interfaces/IOs. * Integrated Giga-bit Ethernet switch supporting up to a total of two external ports (TSN capable). * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio, 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. * Dedicated Centralized System Controller for Security, Power, and Resource Management. * Multiple low power modes support, ex: Deep sleep,Standby, MCU-only, enabling battery powered system design. AM625 is the first device of the family. Add DT bindings for the same. More details can be found in the Technical Reference Manual: https://www.ti.com/lit/pdf/spruiv7 Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Gowtham Tammana <g-tammana@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2022-06-10soc: ti: k3-socinfo: Add entry for AM62X SoC familySuman Anna
Add support for AM62x SoC identification. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-06 13:22:10 +0000