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2025-07-09Merge patch series "board: ti: am33xx: Add Ethernet support for Beaglebone ↵Tom Rini
Green Eco" Romain Gantois <romain.gantois@bootlin.com> says: This is version one of my series which enables Ethernet support on the BBGE board. This requires three main changes: - Describing the MAC<->PHY link and DP83867 PHY accurately in the device tree - Enabling the RGMII1 pinmux configuration - Enabling the DP83867 driver These changes are all applied in patch 2. Patch 1 enables excluding the DP83867 driver from SPL. This is done to avoid size issues when adding the DP83867 driver to the am335x-evm defconfig. Link: https://lore.kernel.org/r/20250626-bbge-ethernet-v1-0-5b544fb1898f@bootlin.com
2025-07-09net: phy: dp83867: Allow excluding driver from SPLRomain Gantois
The DP83867 PHY driver is used by the BeagleBoneGreen Eco board, but adding it to the am335x-evm defconfig causes SPL to overflow its size limits. Add a separate option to enable this driver in SPL, so that it can be enabled in U-Boot without adding unnecessary volume to SPL. Signed-off-by: Romain Gantois <romain.gantois@bootlin.com> Tested-by: Judith Mendez <jm@ti.com>
2025-07-08pci_endpoint: pci_cdns_ti_ep: Fix the include path for header fileHrushikesh Salunke
The commit under fixes tag includes "pcie-cadence.h" using angle brackets. Since the header file is not in standard include path change it to double quotes to ensure proper inclusion and avoid build issues, especially on older compilers. Fixes: a4a0edc6046 ("pci_endpoint: Add TI K3 Cadence PCIe Endpoint Controller driver") Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com>
2025-07-08cadence_qspi: fix odd byte read issue in STIG modeVenkatesh Yadav Abbarapu
In DDR mode, even bytes are read using DMA, while the remaining odd bytes are read using STIG mode. However, the data is not correctly transferred into the flash read data lower register because the supplementary byte of the STIG opcode is not being written to the opcode extension register, resulting in incorrect data being read. To resolve this issue, when using STIG transactions, the corresponding supplementary byte of any STIG opcode must be defined in the Opcode Extension Register (Lower). Issue has been observed on the Macronix MX66UM2G45G flashes. Signed-off-by: Prasad Kummari <prasad.kummari@amd.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Link: https://lore.kernel.org/r/20250702053953.640046-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-07-08spi: cadence_qspi: Set tshsl_ns to at least one sclk_nsVenkatesh Yadav Abbarapu
tshsl_ns is the clock delay for chip select deassert. This is the delay in master reference clocks for the length that the master mode chip select outputs are de-asserted between transactions. The minimum delay is always SCLK period to ensure the chip select is never re-asserted within one SCLK period. That is why tshsl_ns delay should be at least one sclk_ns value. If it is less than sclk_ns, set it equal to sclk_ns. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Link: https://lore.kernel.org/r/20250702065717.3871435-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-07-08spi: cadence_qspi: Fix odd byte write issue in STIG modeVenkatesh Yadav Abbarapu
Starting from 'commit <8077d296adff> ("spi: cadence-quadspi: Use STIG mode for all ops with small payload") the utilization of STIG mode has been implemented for read and write operations involving less than 8 bytes of data. However, following this commit, encountering timeout issues occurs when writing odd bytes of data in DDR mode, as indicated below: "jedec_spi_nor flash@0: flash operation timed out SF: 3 bytes @ 0x0 Written: ERROR -110" To resolve this issue, the number of bytes to write has been updated specifically for DDR mode. Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar@amd.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Link: https://lore.kernel.org/r/20250704040444.671604-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-07-08drivers: fpga: intel_sdm_mb: Check SIP SMC status in send_bitstream()Naresh Kumar Ravulapalli
While sending bitstream via SIP SMC, busy status received does not correspond to error, instead it means transfer is accepted but SDM doesn't have any more free buffer space. Hence, data transmission is continued when busy status is received. Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com> Link: https://lore.kernel.org/r/20250701044311.3670-1-nareshkumar.ravulapalli@altera.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-07-08mmc: zynq_sdhci: Reset the host controllerVenkatesh Yadav Abbarapu
Reset the host controller at the early stage of probe so that the configuration will be done properly for reboot cases. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Link: https://lore.kernel.org/r/20250626062440.295301-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-07-08firmware: xilinx: Prepare code for new SMC firmware formatMichal Simek
Separate code to own function to be able to add new enhancement format. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/cf99fe1af82bc004de3e313d4018464f4504f380.1750858165.git.michal.simek@amd.com
2025-07-08firmware: xilinx: Tighten dependencies for ZYNQMP_FIRMWARETom Rini
The ZYNQMP_FIRMWARE code cannot build without platform specific headers being available. Express that requirement in Kconfig as well. Signed-off-by: Tom Rini <trini@konsulko.com> Link: https://lore.kernel.org/r/20250702010410.18828-1-trini@konsulko.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-07-08clk: zynqmp: Add support for dpll clock sourcePadmarao Begari
The clock driver fails to correctly calculate the PLL clock rate for peripherals when using the DPLL as the clock source. The DPLL operates within the full power domain, while peripheral clocks reside in the low power domain. To ensure accurate PLL clock rate computation when the peripheral clock source is set to DPLL, the DPLL-to-LPD cross divisor is used. Signed-off-by: Padmarao Begari <padmarao.begari@amd.com> Link: https://lore.kernel.org/r/20250618094329.296731-1-padmarao.begari@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-07-08clk: versal: Fix clock driver dependencyMichal Simek
Driver fully depends on firmware driver to be present that's why change imply to depends on to cover it. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/bd18a4ce3e65411bb956636d4a2ef4b5fbe8b9e1.1749104235.git.michal.simek@amd.com
2025-07-07Merge branch 'next'Tom Rini
2025-07-03cache: Update dependency for ANDES_L2_CACHETom Rini
The cache driver here can only build on RISCV due to header dependencies. Express that requirement in Kconfig as well. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-03pinctrl: Port pin controller driver for T-Head TH1520 SoCYao Zi
The SoC pads of TH1520 are separated into three groups (AP 1, AP 2 and AON) controlled by independent pin controllers. This patch ports their driver from Linux kernel with most code for setting pinconf and pinmux kept as is. The dt-binding of TH1520 pin controller uses a schema where pins to configure are specfied as strings and looked up at runtime, which the generic pinctrl helpers of U-Boot cannot parse, thus a customized set_state() callback is implemented to parse pinconfig nodes and setup the configuration. Signed-off-by: Yao Zi <ziyao@disroot.org> Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-02mmc: socfpga_dw_mmc: Retrieve clock manager address via DTAlif Zakuan Yuslaimi
Update the MMC driver to retrieve the clock manager base address via probing the clock manager node in the device tree. Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-07-02Revert "drivers: mmc: rpmb: Use R1 response"Jan Kiszka
This reverts commit ae93d8106bdb5926efef9222d553adb295ebce96. It is no longer needed since 24b1e0c7e2e3. Since the obsolete include pulled in byteorder.h which is needed by now, include this one directly. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-07-01mtd/spinand: gigadevice: sync supported chips with linux 6.9Chuanhong Guo
Adding support for: GD5F1GQ4RExxG GD5F2GQ4UExxG GD5F2GQ4RExxG GD5F1GQ5RExxG GD5F2GQ5UExxG GD5F2GQ5RExxG GD5F4GQ6UExxG GD5F4GQ6RExxG GD5F1GM7UExxG GD5F1GM7RExxG GD5F2GM7UExxG GD5F2GM7RExxG GD5F4GM8UExxG GD5F4GM8RExxG GD5F2GQ5xExxH GD5F1GQ5RExxH GD5F1GQ4RExxH Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
2025-06-29arm: pinctrl: Define .mux_mask field for NXP's SoCLukasz Majewski
The commit e8a9521e649f ("vf500/vf610: synchronise device trees with linux") has synchronized U-Boot's DTS with v5.19 Linux kernel. It turned out that in Linux's upstream iomuxc node description the 'fsl,mux_mask' was missing, so the U-Boot's pinctrl driver for NXP's Vybrid SoC was not working properly. As by default the mux mask was set to 0, for example the vf610 based boards (like BK4) were bricked, due to misconfiguration of gpio at early boot stage. The fix for all NXP eligible boards is to define .mux_mask field for soc specific *pinctrl_soc_info structure and use it directly in pinctrl MMIO driver, without the need to read the "fsl,mux_mask" property from device tree. This change brings the NXP's pinctrl driver in U-Boot closer to Linux upstream one. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com> #for i.MX8ULP
2025-06-27Merge patch series "Fix io accessors for KVM"Tom Rini
Ilias Apalodimas <ilias.apalodimas@linaro.org> says: Instructions that lead ito an exception in the hypervisor can't modify two CPU registers at once for the ARM ISA. These instructions cannot be emulated by KVM as they do not produce syndrome information data that KVM can use to infer the destination register, the faulting address, whether it was a load or store, or if it's a 32 or 64 bit general-purpose register. As a result an external abort is injected from QEMU, via ext_dabt_pending. Link: https://lore.kernel.org/r/20250618065828.1312146-1-ilias.apalodimas@linaro.org
2025-06-27nxp: Prepare macros for KVM changesIlias Apalodimas
A following patch is replacing our IO accessors with do { ... } while(0) ones in order to make them usable with KVM. That leads to an error eventually looking like this: arch/arm/include/asm/io.h:62:9: error: expected expression before 'do' 62 | do { \ | ^~ arch/arm/include/asm/io.h:211:41: note: in expansion of macro '__raw_writel' 211 | #define out_arch(type,endian,a,v) __raw_write##type(cpu_to_##endian(v),a) | ^~~~~~~~~~~ arch/arm/include/asm/io.h:223:25: note: in expansion of macro 'out_arch' 223 | #define out_be32(a,v) out_arch(l,be32,a,v) | ^~~~~~~~ drivers/spi/fsl_dspi.c:127:17: note: in expansion of macro 'out_be32' 127 | out_be32(addr, val) : out_le32(addr, val); | ^~~~~~~~ So adjust the current macros and code to be compatible with the upcoming change. Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2025-06-27Merge patch series "drivers: pci: pcie_dw_common: Add ↵Tom Rini
dw_pcie_link_set_max_link_width()" This patch set from Marek Vasut <marek.vasut+renesas@mailbox.org> introduces dw_pcie_link_set_max_link_width() similar to the Linux Kernel and then migrates the current platform drivers to use it. Next it adds support for Renesas R-Car Gen4 platforms and enables it on one. Link: https://lore.kernel.org/r/20250617081641.8385-1-marek.vasut+renesas@mailbox.org
2025-06-27pci: pcie-rcar-gen4: Add Renesas R-Car Gen4 DW PCIe controller driverMarek Vasut
Add R-Car Gen4 PCIe controller support for host mode. This controller is based on Synopsys DesignWare PCIe. However, this particular controller has a number of vendor-specific registers, and as such, requires initialization code, including PHY firmware loading. The PHY firmware loading is implemented in an entirely generic manner, by calling a firmware loading script, which the user can configure in a way they require. This provides the user with flexibility of loading the PCIe firmware from whichever storage device they need to load it from. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-06-27pci: pcie_dw_rockchip: Use dw_pcie_link_set_max_link_width()Marek Vasut
Use dw_pcie_link_set_max_link_width() instead of local implementation of the same functionality. This does change the behavior slightly, as the dw_pcie_link_set_max_link_width() implementation also programs the LNKCAP register MLW, this should however be correct and is now aligned with Linux kernel behavior. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-06-27pci: pcie_dw_qcom: Use dw_pcie_link_set_max_link_width()Marek Vasut
Use dw_pcie_link_set_max_link_width() instead of local implementation of the same functionality. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-06-27pci: pcie_dw_meson: Use dw_pcie_link_set_max_link_width()Marek Vasut
Use dw_pcie_link_set_max_link_width() instead of local implementation of the same functionality. This does change the behavior slightly, as the dw_pcie_link_set_max_link_width() implementation also programs the LNKCAP register MLW, this should however be correct and is now aligned with Linux kernel behavior. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-06-27drivers: pci: pcie_dw_common: Add dw_pcie_link_set_max_link_width()Marek Vasut
Add dw_pcie_link_set_max_link_width() implementation ported from Linux kernel as of commit 89db0793c9f2 ("PCI: dwc: Add missing PCI_EXP_LNKCAP_MLW handling"). This is common code which is already duplicated in multiple drivers. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-06-26Merge patch series "Add TI K3 PCIe Endpoint Controller support for AM64X"Tom Rini
Hrushikesh Salunke <h-salunke@ti.com> says: This series adds support for the Endpoint mode on Cadence PCIe controller on TI's K3 family of SoCs. The driver is an adaptation of the Linux driver (drivers/pci/controller/cadence/pci-j721e.c) and has been implemented specifically for Endpoint mode of operation on AM64X. A minor set of changes will be sufficient to support other K3 SoCs as well. This patch is tested on AM64X EVM. Following are the log corresponding to this feature. https://gist.github.com/hrushikesh221/e8557cbe7667877c50f7d7e9bb96d060 Link: https://lore.kernel.org/r/20250616164929.631791-1-h-salunke@ti.com
2025-06-26pci_endpoint: Add TI K3 Cadence PCIe Endpoint Controller driverHrushikesh Salunke
Add support for Endpoint mode of operation in the Cadence PCIe Controller present on TI's K3 SoCs. This driver is an adaptation of the Linux kernel v6.15 driver (drivers/pci/controller/cadence/pci-j721e.c). Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
2025-06-26phy: cadence: torrent: add support for three or more links using 2 protocolsHrushikesh Salunke
This is a port of the corresponding commit in the Linux kernel which adds the same support for the Cadence Torrent driver[0]. The commit message below is taken as-is from the Linux kernel commit being ported. The Torrent SERDES can support at most two different protocols (PHY types). This only mandates that the device-tree sub-nodes used to represent the configuration should describe links with at-most two different protocols. The existing implementation however imposes an artificial constraint that allows only two links (device-tree sub-nodes). As long as at-most two protocols are chosen, using more than two links to describe them in an alternating configuration is still a valid configuration of the Torrent SERDES. A 3-Link 2-Protocol configuration of the 4-Lane SERDES can be: Lane 0 => Protocol 1 => Link 1 Lane 1 => Protocol 1 => Link 1 Lane 2 => Protocol 2 => Link 2 Lane 3 => Protocol 1 => Link 3 A 4-Link 2-Protocol configuration of the 4-Lane SERDES can be: Lane 0 => Protocol 1 => Link 1 Lane 1 => Protocol 2 => Link 2 Lane 2 => Protocol 1 => Link 3 Lane 3 => Protocol 2 => Link 4 [0] https://github.com/torvalds/linux/commit/5b7b83a9839be643410c31d56f17c2d430245813 Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
2025-06-25rtc: add ds1672 driverTim Harvey
Add support for Dallas/Maxim ds1672 32bit counter RTC. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2025-06-24i2c: mux: Fix the crash when the i2c-arbitrator node is presentVenkatesh Yadav Abbarapu
Observing the crash when we add the i2c-arbitrator node in the device tree as per the DT bindings. The issue is with the child node of i2c-arbitrator@72 i.e., i2c@f1950000->i2c-arbitrator@72->i2c-arb, as the arbitrator uses the uclass of mux(UCLASS_I2C_MUX) and the mux uclass driver checks for the "reg" property using the i2c_mux_child_post_bind() function, if it won't find the "reg" property it will return -EINVAL which is leading to the crash. So, add the logic to check whether the child node has the "reg" property, if the "reg" property exists then read the "reg" and update the channel. https://www.kernel.org/doc/Documentation/devicetree/bindings/i2c/i2c-arb.txt Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2025-06-24Merge tag 'qcom-next-23Jun-1' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-snapdragon into next This PR introduces 3 new platforms, two from the new Dragonwing IQx series (QCS615 and QCS8300) as well as the IPQ5424. Additionally: * Support for booting downstream Android boot images on some phones is added * Capsule update support is expanded to be more generic, determining which partition U-Boot was flashed to automatically and supporting many more boards. * Minor capsule update bugs are fixed * A watchdog driver is added and gets timeout support * Autoboot now requires pressing "space" specifically to stop booting as a workaround for some boards getting rogue key presses which would cause autoboot to fail * Documentation is added for the Dragonwing boards * The RB1/2 now use USB gadget mode rather than host * A bug is fixed where GPIO reads could return incorrect values
2025-06-24clk/qcom: sm8250: Fix variable name of msm_clk_dataLuca Weiss
Update the variable name to sm8250_gcc_data as it's in the sm8250 driver. Fixes: dcd688229cb ("clk/qcom: add driver for sm8250 GCC") Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Casey Connolly <casey.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250611-qcom-clk-variable-names-v1-2-37615b74daad@fairphone.com Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-24clk/qcom: sc7280: Fix variable name of msm_clk_dataLuca Weiss
Update the variable name to sc7280_gcc_data as it's in the sc7280 driver. Fixes: f50e7be6bb1 ("clk/qcom: add initial clock driver for sc7280") Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Casey Connolly <casey.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250611-qcom-clk-variable-names-v1-1-37615b74daad@fairphone.com Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-24dfu: scsi: don't call scsi_scan()Caleb Connolly
Calling scsi_scan() results in all the block devices (and EFI block devices) being destroyed and re-created. This breaks the EFI filesystem drivers during capsule update. Remove the call, since boards really should be calling scsi_scan() themselves during board_init(). Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> Link: https://lore.kernel.org/r/20250411-b4-qcom-capsule-update-improvements-v2-3-27f6b2fcc4a9@linaro.org Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-24clk/qcom: qcs615: Add GCC clock driver for QCS615Aswin Murugan
Port Linux's gcc-qcs615.c driver to U-Boot for basic bring-up. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250521035324.1182833-4-aswin.murugan@oss.qualcomm.com Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-24phy: qcom: Enable QMP UFS PHY driver for QCS615Aswin Murugan
Enable QMP phy for QCS615, referenced from Linux. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250521035324.1182833-3-aswin.murugan@oss.qualcomm.com Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-24phy: qcom: Enable QMP UFS PHY driver for QCS8300Balaji Selvanathan
Enable QMP phy for QCS8300, referenced from Linux. Reviewed-by: Casey Connolly <casey.connolly@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250529154931.1879976-5-quic_bselvana@quicinc.com Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-24clk/qcom: qcs8300: Add GCC clock driver for QCS8300Balaji Selvanathan
* Port Linux's gcc-qcs8300.c driver to U-Boot for basic bring-up. * Enable QCS8300 clocks in qcom_defconfig. Reviewed-by: Casey Connolly <casey.connolly@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250529154931.1879976-4-quic_bselvana@quicinc.com Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-24gpio: msm_gpio: return correct value for gpio readAswin Murugan
In the current implementation, the GPIO read operation considers both the input and outbut bits (bits 0 and 1). It should only consider the state of input bit, i.e bit 0. To address this, mask input bit alone and read it. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Reviewed-by: Casey Connolly <casey.connolly@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250508113646.1462518-1-aswin.murugan@oss.qualcomm.com Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-23Merge tag 'v2025.07-rc5' into nextTom Rini
Prepare v2025.07-rc5 With this merge, tighten up the LTO_FLAGS removal we added to not trigger on ARMv7 (which is Thumb-2 and should be fine).
2025-06-23drivers: watchdog: qcom: Add timeout configuration support in watchdogBalaji Selvanathan
This patch enhances the Qualcomm watchdog driver by introducing support for dynamic timeout configuration. Specifically: - Calculates and sets the bark and bite timeout values based on the clock rate and the requested timeout in milliseconds. - Adds retrieval of the watchdog clock rate during probe using the common clock framework. - Adds a default timeout value for ARCH_SNAPDRAGON in WATCHDOG_TIMEOUT_MSECS. These changes improve the configurability and accuracy of the watchdog timer on Qualcomm platforms. This work builds upon the previous submission: https://lore.kernel.org/all/20250422-b4-qcom-wdt-v3-1-730d4d5a858d@paulsajna.com/ Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250527124926.128413-1-balaji.selvanathan@oss.qualcomm.com Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-23watchdog: qcom: introduce qcom-wdt driverCasey Connolly
Some Qualcomm device vendors decide to turn the watchdog on in the bootloader, resulting in the device being reset if it isn't petted every ~30 seconds. Introduce a driver to keep the watchdog happy and prevent this annoying behaviour. Signed-off-by: Paul Sajna <hello@paulsajna.com> Co-authored-by: Paul Sajna <hello@paulsajna.com> Tested-by: Paul Sajna <hello@paulsajna.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250422-b4-qcom-wdt-v3-1-730d4d5a858d@paulsajna.com Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-23pinctrl: qcom: Add ipq5424 pinctrl driverVaradarajan Narayanan
Add pinctrl driver for the TLMM block found in the ipq5424 SoC. Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Reviewed-by: Casey Connolly <casey.connolly@linaro.org> Link: https://lore.kernel.org/r/20250304110105.2762124-6-quic_varada@quicinc.com Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-23clk/qcom: add initial clock driver for ipq5424Varadarajan Narayanan
Add initial set of clocks and resets for enabling U-Boot on ipq5424 based RDP platforms. Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Reviewed-by: Casey Connolly <casey.connolly@linaro.org> Link: https://lore.kernel.org/r/20250304110105.2762124-5-quic_varada@quicinc.com Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-22net: designware: fix bus address dereferenceBaruch Siach
Device bus address might not be valid for direct access when the bus address and CPU address are not the same. Use dev_bus_to_phys() to translate bus address back to CPU address. Fixes: 3d98b8c504e15 ("net: designware: Invalidate RX buffer cache before freeing the DMA descriptor") Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2025-06-20Merge patch series "Consistent Kconfig environment options CONFIG_ENV_ prefix"Tom Rini
Marek Vasut <marek.vasut+renesas@mailbox.org> says: Rename the environment related variables and add ENV_ prefix, so that all configuration options which are related to environment would have an CONFIG_ENV_ prefix. No functional change. Link: https://lore.kernel.org/r/20250609192701.20260-1-marek.vasut+renesas@mailbox.org
2025-06-20env: Rename SYS_MMC_ENV_DEV to ENV_MMC_DEVICE_INDEXMarek Vasut
Rename the variable and add ENV_ prefix, so that all configuration options which are related to environment would have an CONFIG_ENV_ prefix. No functional change. Use ENV_MMC_DEVICE_INDEX to clarify this is the SD/MMC device index, a number, as enumerated by U-Boot. Update the help text accordingly. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-06-20Merge tag 'u-boot-at91-2025.10-a' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-at91 into next First set of u-boot-at91 features for the 2025.10 cycle: This feature set includes the addition of new sam9x7 SoC and a new board named sam9x7-curiosity. There is also new support for sam9x60 compatible at91 watchdog.
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-07 18:46:55 +0000