summaryrefslogtreecommitdiff
path: root/drivers
AgeCommit message (Collapse)Author
2023-03-28Merge tag 'u-boot-at91-2023.07-a' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-at91 into next First set of u-boot-at91 features for the 2023.07 cycle: This feature set includes the clock changes required for sam9x60 SoC to support USB host.
2023-03-27Merge branch 'master' into nextTom Rini
2023-03-27clk: at91: sam9x60: Add initial setup of UPLL and USBCK ratesSergiu Moga
In order for some of the functionalities, such as the USB clocks, to work properly we need some clocks to be properly initialised at the very beginning of booting. Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2023-03-27clk: at91: pmc: export clock setup to pmcClaudiu Beznea
Clock setup was intended for setting clocks at boot time on SAMA7G5, e.g. for root clocks like PLLs, that were used to feed IPs needed alive in u-boot (e.g. Ethernet clock feed by a PLL). Export this functionality to all at91 clocks as it may be necessary on other SoCs. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2023-03-27clk: at91: sam9x60: Register the required clocks for USBSergiu Moga
Register into DM the clocks required to properly enable USB functionality within the bootloader. Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2023-03-27clk: at91: Add support for sam9x60 USB clockSergiu Moga
Implement sam9x60 USB clock driver. This clock has three parents: PLLA, UPLL and MAINXTAL. The driver is aware of the three possible parents with the help of the two mux tables provied to the driver during the registration of the clock. Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2023-03-24Merge branch 'rpi-2023.04' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-raspberrypi - Fixes for booting newer revs of the SoC in the Raspberry Pi 4 - Propagate some firmware DT properties to the loaded DT - Update the Zero2W upstream DT name
2023-03-24mmc: bcm2835-host: let firmware manage the clock divisorVincent Fazio
Newer firmware can manage the SDCDIV clock divisor register, allowing the divisor to scale with the core as necessary. Leverage this ability if the firmware supports it. Adapted from the following raspberrypi Linux kernel commit: bcm2835-sdhost: Firmware manages the clock divisor https://github.com/raspberrypi/linux/commit/08532d242d7702ae0add95096aa49c5e96e066e2 Signed-off-by: Vincent Fazio <vfazio@xes-inc.com> Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
2023-03-24ddr: marvell: a38x: Remove unused file seq_exec.hPali Rohár
DDR code does not use seq_exec.h, so remove it. Signed-off-by: Pali Rohár <pali@kernel.org>
2023-03-22dma: ti: k3-udma: Fix channel hang on teardownVignesh Raghavendra
Setting RX flow error handling will stall the channel until descriptors are available to move RX data. Setting this bit causes issues when tearing down ethernet DMA channel at the end of TFTP transfer as unrelated network packets can cause teardown to stall indefinitely waiting for driver to queue add more desc leading to channel hang with error logs: udma_stop_dev2mem TIMEOUT ! udma_stop_dev2mem: peer not stopped TIMEOUT ! udma_stop_dev2mem TIMEOUT ! Fix this by clearing rx_error_handling similar to how its done for UDMA as part of udma_alloc_rchan_sci_req() This fixes occasional TFTP Failures seen when downloading multiple files one after the other on AM64/AM62 SoCs. Fixes: 9a92851c33e8 ("dma: ti: k3-udma: Add BCDMA and PKTDMA support") Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-03-21Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-shTom Rini
A single reset controller driver (part of the clock driver) fix for v2023.04 release.
2023-03-20clk: renesas: Pack reset identifier before look upMarek Vasut
The reset identifier must be processed via MOD_CLK_PACK() before it is used to look up register and bit within reset_regs or reset_clear_regs arrays, otherwise completely bogus register and bit is picked from the arrays, one which may even be out of range. Fixes: 326e05c5e21 ("clk: renesas: Add and enable CPG reset driver") Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-19rockchip: timer: rockchip_timer: fix compatible and driver nameJohan Jonker
In the binding for the Rockchip timer the compatible string consists of a SoC orientated string and a fall back string "rockchip,rk3288-timer", so remove all unneeded ones and fix driver name. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-03-19rockchip: sdhci: rk3568: bypass DLL when clk <= 52 MHzVasily Khoruzhick
For Rockchip platform, DLL bypass bit and start bit need to be set if DLL is not locked. With this change applied eMMC in my NanoPi R5S can run at 52 MHz. Based on linux commit b75a52b0dda3 ("mmc: sdhci-of-dwcmshc: Update DLL and pre-change delay for rockchip platform") Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-03-19clk: rockchip: rk3568: add stubs for CLK_PCIEPHY_REF clocksVasily Khoruzhick
Device tree contains assigned-clock-rates property for these, but default value will work just fine Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2023-03-19mmc: rockchip_dw_mmc: Fix get_mmc_clk return valueJonas Karlman
The get_mmc_clk ops is expected to set a clock rate and return the configured rate as an unsigned value. However, if clk_set_rate fails, e.g. using a fixed rate clock, a negative error value is returned. The mmc core will treat this as a valid unsigned rate and tries to configure a divider based on this bogus clock rate. Use 0 as the return value when setting clock rate fails, the mmc core will configure to use bypass mode instead of using a bogus divider. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-03-19clk: rockchip: rk3588: Fix clk_aux16m in clock driverJonas Karlman
The rate and error value is not returned for aux16m clocks, fix this. Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-03-19clk: rockchip: rk3568: Fix reset handlerPeter Geis
The reset handler for rk3568 is missing its private data. This leads to an abort when a reset is triggered. => reset resetting ... "Synchronous Abort" handler, esr 0x96000045 elr: 0000000000a2bc04 lr : 0000000000a2bbd4 (reloc) elr: 00000000eff9bc04 lr : 00000000eff9bbd4 x0 : 00000000fdd20000 x1 : 0000000014000001 x2 : 000000000000fdb9 x3 : 00000000edf77e88 x4 : 00000000edf50e78 x5 : 00000000edf77530 x6 : 000000000000001d x7 : 00000000edf8a1d0 x8 : 00000000ffffffd8 x9 : 0000000000000008 x10: 000000000000000d x11: 0000000000000006 x12: 000000000001869f x13: 0000000086c290c5 x14: 000000009118e878 x15: 0000000000000000 x16: 00000000eff9bbb8 x17: 0000000012f8c119 x18: 00000000edf50dc0 x19: 0000000000000000 x20: 0000000000000001 x21: 0000000000000000 x22: 00000000edf85900 x23: 0000000000000001 x24: 00000000effe8bbc x25: 0000000000000000 x26: 00000000edf85940 x27: 0000000000000000 x28: 0000000000000000 x29: 00000000edf3c8e0 Code: d65f03c0 d5033fbf b9400661 529d9502 (b8216802) Resetting CPU ... Add the missing dev_set_priv to the rk3568 clk driver to fix this. Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver") Signed-off-by: Peter Geis <pgwipeout@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # radxa-cm3 Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2023-03-18serial: sh: Make indent consistentMarek Vasut
Make the indent of these macro elements consistent with the rest of this table. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-18serial: sh: Add DEBUG_UART supportMarek Vasut
Add support for debug output very early during boot using the DEBUG_UART mechanism. This uses a static fixed UART port configuration selected via Kconfig options and dedicated print functions from debug_uart.h. This is useful e.g. when debugging problems so early during boot, that not even the DM is initialized at that point, and thus DM_SERIAL is not available either. This functionality is disabled by default. To activate it, define the following Kconfig options and select SCIF type using CFG_SCI/CFG_SCIF_A/ CFG_HSCIF/<nothing for regular SCIF>: CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_SCIF=y CONFIG_DEBUG_UART_BASE=0xe6540000 CONFIG_DEBUG_UART_CLOCK=24000000 The later two options define the SCIF physical base address and SCIF input clock in Hz. Optionally, to validate DEBUG_UART works, enable the following as well to get early serial output message by default: CONFIG_DEBUG_UART_ANNOUNCE=y Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-18serial: sh: Rename CONFIG_SCI and CONFIG_SCIF_USE_EXT_CLK to CFG_ variantsMarek Vasut
Both CONFIG_SCI and CONFIG_SCIF_USE_EXT_CLK options do not have a matching Kconfig entry because they are internal to the SCIF driver. Change their prefix to CFG_, i.e. CFG_SCIF_USE_EXT_CLK and CFG_SCI, to reflect that and avoid interferring with Kconfig symbols. Since neither of those options are defined elsewhere, no functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-18pinctrl: renesas: Replace ifdeffery with IS_ENABLED()Marek Vasut
Switch ifdef in sh_gpio_get_value() to IS_ENABLED() macro. The CONFIG_RCAR_GEN3 will never have SPL counterpart, so the IS_ENABLED() macro is the right one here. No functional change, except for improved build test coverage. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-18net: ravb: Support fixed PHY in R-CarMikhail Lappo
Calling old U-Boot API doesn't allow to use fixed PHY. Searching by mask is the part of new function, after scanning FDT for a fixed PHY definition Fixes: e821a7bdb13 ("net: ravb: Detect PHY correctly") Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Mikhail Lappo <mikhail.lappo@esrlabs.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> [Hai Pham: Drop phy_connect_dev since it's called in phy_connect] Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> [Marek: Use mask -1 instead of 0 to reinstate the search behavior over all PHY addresses. Add Fixes tag, sort the tag list.]
2023-03-18i2c: rcar_i2c: Sort Kconfig depends list ascendingMarek Vasut
Sort the list of "depends" symbols in ascending order. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2023-03-18i2c: rcar_iic: Sort Kconfig depends list ascendingMarek Vasut
Sort the list of "depends" symbols in ascending order. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2023-03-18clk: renesas: rcar-gen3: Replace SSCG caching with MDSEL/PE cachingMarek Vasut
Do not cache the single CPG MODE register bit 12, instead cache the entire register value, and only pick the matching bit from the cached value when core clock of type MDSEL or PE are used. Both MDSEL and PE clock type currently define .offset field as 12 on Gen3, which means this code will use bit 12 on Gen3 again, however there are additional clock on Gen4 which use different bits, and having this flexibility in place now will be useful when adding Gen4. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-16Merge tag 'xilinx-for-v2023.07-rc1' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2023.07-rc1 cmd: - Print results in hex instead of dec in smc command firmware: - Cover missing ZYNQMP_FIRMWARE dependencies fpga: - fix loads for unencrypted use case relocation - Add support for BE systems spi: - Fix xilinx_spi init reset sequence arasan nand: - Remove hardcoded bbt option - Set ofnode value xilinx: - Enable SMC command - Fix some sparse issues zynqmp: - Remove cdns,zynq-gem compatible string - Add optee node - Some DT cleanups zynq: - Some DT cleanups microblaze - Remove MANUAL_RELOC option
2023-03-16Revert 9f62a472dfb2 ("video: Remove duplicate cursor-positioning function")Tom Rini
This reverts commit 9f62a472dfb26ec14408a27938ddd2a25700009d. The changes here aren't quite right, and on platforms such as Raspberry Pi where we can have both serial and video output, the change above causes output to change. This can be seen as the hush tests we have now fail. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-14Merge tag 'v2023.04-rc4' into nextTom Rini
Prepare v2023.04-rc4 Signed-off-by: Tom Rini <trini@konsulko.com>
2023-03-13video: Clear the vidconsole rather than the videoSimon Glass
It is better to clear the console device rather than the video device, since the console has the text display. We also need to reset the cursor position with the console, but not with the video device. Add a new function to handle this and update the 'cls' command to use it. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-13video: Remove duplicate cursor-positioning functionSimon Glass
There are two functions for positioning the cursor on the console. Remove one of them. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-13video: Allow a copy framebuffer with pre-allocated fbSimon Glass
At present it is not possible for the video driver to use a pre-allocated frame buffer (such as is done with EFI) with the copy framebuffer. This can be useful to speed up the display. Adjust the implementation so that copy_size can be set to the required size, with this being allocated if the normal framebuffer size is 0. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-13efi: Support copy framebufferSimon Glass
Add support for this to EFI in case it becomes useful. At present it just slows things down. You can enable CONFIG_VIDEO_COPY to turn it on. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-13efi: Use a fixed value for the timer clockSimon Glass
It is not yet clear how to read the timer via EFI. The current value seems much too high on a Framework laptop I tried. Adjust it to a lower hard-coded value for now. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-13efi: Support a 64-bit frame buffer addressSimon Glass
The current vesa structure only provides a 32-bit value for the frame buffer. Many modern machines use an address outside the range. It is still useful to have this common struct, but add a separate frame-buffer address as well. Add a comment for vesa_setup_video_priv() while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-13efi: video: Return mode info for app alsoSimon Glass
The mode info is currently not initialised for the app. Fix this by returning it from the function. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-13efi: video: Move payload code into a functionSimon Glass
Put this into a function, as we have done for the app implementation. Comment both functions. FOr now the app still does not access it correctly. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-10Merge https://source.denx.de/u-boot/custodians/u-boot-usbTom Rini
Two minimal Kconfig/Makefile fixes for USB.
2023-03-10ARM: dts: renesas: Enable sysinfo on R-Car V3H Condor/Condor-ITam Nguyen
Add new sysinfo IDs for R-Car V3H Condor/Condor-I . Enable support for sysinfo on R-Car V3H Condor/Condor-I. The sysinfo is used e.g. to access and decode board-specific information and then in turn used by board-info to print those information. Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> [Marek: Drop compatible from I2C node, this is in r8a77980.dtsi already. Drop status = "okay" from EEPROM node. Add dts: tag. Update the commit message, note the new sysinfo IDs. Fix Kconfig EEPROM address to be 0x50 and match the DT, sync config.]
2023-03-10sysinfo: rcar3: Fix Draak and Eagle board codeTam Nguyen
Correct the board code ID based on the hardware documentation Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-10pinctrl: renesas: Drop non-existent PFC info table entriesMarek Vasut
Remove PFC info table entries which are never instantiated, since there are no drivers for those. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-10clk: renesas: Always select DM_RESET to prevent inobvious failure of ↵Marek Vasut
rst_gen3 subdriver The CLK_RCAR_GEN3 registers two subdrivers, clk_gen3 and rst_gen3. The former depends on the clock framework, which is always enabled in this context of clock framework driver, while the later depends on reset framework which may not always be enabled. Ensure the reset framework is also always enabled to prevent inobvious early boot time bind failure of the CPG driver, which leads to system showing no activity and is difficult to debug. Note that one possible approach to debug this is to use CONFIG_DEBUG_UART and add debug printascii()s into the drivers/clk/renesas/clk-rcar-gen3.c . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-10mmc: renesas-sdhi: Add proper probe error fail pathMarek Vasut
In case one of the calls in probe fail, trigger a fail path and undo all the steps done in probe until the point of failure. The current implementation failed to stop controller clock and free claimed clock, so fix that. Furthermore, print return code in error prints for easier debugging. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-10mmc: renesas-sdhi: Always configure default SDnH clock rate to 800 MHzMarek Vasut
The prior stage bootloader might have left the SDnCKCR register in completely arbitrary state before passing control to U-Boot, which includes the register being populated with incorrect values. Currently the SDHI driver will attempt to use clock framework to configure SDn clock, which may fail in case SDnCKCR contains invalid values for the SDnH clock, because the clock framework would not be able to determine SDnH clock rate and would get -EINVAL instead, which in turn would not allow the clock framework to determine the correct SDn clock divider ratio. This failure occurs specifically in case SDnCKCR reads back 0x209 . Correct the problem by first setting default SDnH clock rate to 800 MHz, thus assuring the SDnCKCR SDnH bits are correct, and only afterward set up the SDn clock rate to default 200 MHz. Note that the SDHI driver may reconfigure SDnH clock later based on IOS settings obtained from the attached card, the 800 MHz set up here is only the default value. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-10usb: move CONFIG_USB_HUB_DEBOUNCE_TIMEOUT to USBHeinrich Schuchardt
This configuration setting is only relevant if the board supports USB. It should not be in the main menu but in the USB menu. The setting is only relevant in USB host mode. Fixes: 5454dea3137d ("usb: hub: allow to increase HUB_DEBOUNCE_TIMEOUT") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-03-09xilinx: zynqmp: Add missing prototype for zynqmp_mmio_writeAlgapally Santosh Sagar
Add missing prototype to fix the sparse warning, warning: no previous prototype for 'zynqmp_mmio_write' [-Wmissing-prototypes]. Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230301103334.1455-2-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-09mtd: nand: arasan: Set ofnode valueAshok Reddy Soma
Ofnode value is not set, so all the DT properties are not being read and due to this default values are being used. Find nand node and set chip->flash_node value. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230224050709.30014-3-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-09mtd: nand: arasan: Remove hardcoded bbt optionAshok Reddy Soma
Bad block table option is hardcoded to read from flash with NAND_BBT_USE_FLASH option. This decision should be done based on DT property. Remove this hardcoding, to be able to use DT property. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230224050709.30014-2-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-09spi: xilinx_spi: Fix spi resetJiajie Chen
It was incorrectly using an old priv->regs pointer, which was initialized to zero. SPI resets won't happen on first call. Signed-off-by: Jiajie Chen <c@jia.je> Link: https://lore.kernel.org/r/20230227150938.211820-1-c@jia.je Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-09fpga: zynqmppl: fix fpga loads command for unencrypted use caseNeal Frager
When using the fpga loads command, the driver is passing the AES encryption key address is all cases. However, for the authenticated, but not encrypted use case, there is no AES encryption key, and this value is 0. When AES encryption is not used on the fpga bitstream, the pmufw assumes that the AES key address is a bitstream size value like what is used by the unsecure fpga load command. To fix the problem, this patch checks to see if the AES key address is zero. If the AES key address is zero, it means that AES is not being used on the bitstream and the bitstream size should be passed instead. Thus, matching the fpga load functionality. Signed-off-by: Neal Frager <neal.frager@amd.com> Acked-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230214131959.40298-1-neal.frager@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-07 02:32:04 +0000