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Use byteorder conversion function instead of manually assembling data
from/to MCU.
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
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Add header containing all MCU command definitions and use it in board
code and in MCU driver.
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
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https://source.denx.de/u-boot/custodians/u-boot-dfu
u-boot-dfu-next-20240402
- Implement Qualcomm wrapper for dwc3
- Multiple sector size support for UMS
- CDC ACM gadget initialization fix
- Refactor board code from dwc3 to prepare better interrupt support
- Bugfix for for qcom-smmu when compiling with -DDEBUG
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Merge in all changes from the next branch now that the release is out.
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dm_usb_gadget_handle_interrupts
The only call site of dwc3_uboot_handle_interrupt() is the
dm_usb_gadget_handle_interrupts(), fold the former into the
later. This makes dwc3_uboot_handle_interrupt() unavailable
to be called from board code as well.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> # vim3
Link: https://lore.kernel.org/r/20240317044357.547037-2-marek.vasut+renesas@mailbox.org
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
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The dm_usb_gadget_handle_interrupts() has no place in board code. Move
this into DWC3 driver. The OMAP implementation is special, add new weak
dwc3_uboot_interrupt_status() function to decide whether DWC3 interrupt
handling should be called, and override it in OMAP DWC3 code, to repair
the special OMAP interrupt handling code until OMAP gets switched over
to DM UDC proper.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> # vim3
Tested-by: Caleb Connolly <caleb.connolly@linaro.org> # qcom sdm845
Link: https://lore.kernel.org/r/20240317044357.547037-1-marek.vasut+renesas@mailbox.org
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
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Change to regulator_set_enable_if_allowed to avoid enable failure,
in case same phy supply shared by multiple FEC controllers.
Signed-off-by: Ye Li <ye.li@nxp.com>
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imx_tmu_arch_init does not implement for iMX8MQ, error is returned
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add a new kconfig option to allow non-secure world access
to the CAAM Job Ring.
This is needed, for example, when running linux without
OP-TEE services, as it's done on Colibri iMX7.
Fixes: 51f1357f3428 ("Revert "drivers/crypto/fsl: assign job-rings to non-TrustZone"")
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
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Fix spelling errors in comments.
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com>
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Pull the PHY GPIO reset code into separate function, since
this is and will be reused multiple times. Set up default
reset assert and deassert timing to generous 20ms and 1ms
for maximum compatibility in case those DT properties are
missing.
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
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This patch adds support for i225-IT in e1000 driver.
Add e1000_phy_igc.
Signed-off-by: Marjolaine Amate <marjolaine.amate@odyssee-systemes.fr>
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From the ethernet header is not on aligned, because the length
of the ethernet header is 14 bytes.
Therefore, unaligned access must be done here.
Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
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There is no need to perform the endian twice here.
Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
Reviewed-by: Dan Carpenter <dan.carpenter@linaro.org>
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They are not required to be global, make them static.
Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
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3 operations needed by `net stats` are implemented. New `net stats`
output some useful info.
Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
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register internal MDIO bus device if it is a subnode.
Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
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shrink the first argument of log_msg_ret(), add dev_xxx() functions for
error reporting.
Fixes: 9d8f78a2a79f7 ("net: add hifemac Ethernet driver for HiSilicon platform")
Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
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The initial commit used log_msg_ret() wrongly. Fix that by moving error
report to a separate dev_err() call and shrink the first argument of
log_msg_ret() to no more than 4 chars.
Fixes: 6b5c8d98e204 ("net: add hifemac_mdio MDIO bus driver for HiSilicon platform")
Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
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As with fixed-link phy device, the NC-SI phy devive does not
require an mdio bus. So, a condition is added to check the
NC-SI phy id to avoid accessing the bus pointer that is NULL.
Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
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Booting R-Car Gen3 arm64 U-Boot with CONFIG_UBSAN=y resulted in:
=====================================================================
UBSAN: Undefined behaviour in drivers/net/phy/phy.c:728:19
left shift of 1 by 31 places cannot be represented in type 'int'
=====================================================================
Fix it by appending the UL suffix to the numeric literal. While at it,
convert the type of "addr" variable from signed to unsigned, to protect
against shifting the numeric literal by a negative value (which would
lead to yet another undefined behavior).
Fixes: 1adb406b0141 ("phy: add phy_find_by_mask/phy_connect_dev")
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
* Using U-suffix for integer is sufficient.
* ffs() of non-zero value cannot be 0. But addr being unsigned is
* preferable.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
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Configure LEDs on BCM54210E so they would blink on activity
and indicate link speed. Without this the LEDs are always on
if cable is plugged in.
Signed-off-by: Marek Vasut <marex@denx.de>
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The issue occurs the UAF (use-after-free) to cause double free
when do the realloc function for the pointers during the
reinitialization NC-SI process, and it will cause the memory
management occurs error.
So, nullify these pointers after free.
Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
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Prepare v2024.04-rc5
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This message is used to commit into the fuses any new SRK revocation and
FW version information that have been found into the NXP (ELE FW) and
OEM containers.
Signed-off-by: Mathieu Othacehe <othacehe@gnu.org>
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Since now we have the modern pcie_dw_imx.c driver for iMX SoCs,
encourage people to switch to that for any further new iMX SoC support
or even for the older iMX6 SoCs too.
Suggested-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Marek Vasut <marex@denx.de>
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pcie_imx doesn't seem to share any useful code for iMX8 SoC and it is
tied to quite old port of pcie_designware driver from Linux which
suffices only iMX6 specific needs.
But currently we have the common DWC specific bits which alligns pretty
well with DW PCIe controller on iMX8MP SoC. So lets reuse those common
bits instead as a new driver for iMX8 SoCs. It should be fairly easy to
add support for other iMX8 variants to this driver.
iMX8MP SoC also comes up with standalone PCIe PHY support, so hence we
can reuse the generic PHY infrastructure to power on PCIe PHY.
Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice*
Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
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Add initial support for i.MX8M{M/P} PCIe PHY. On i.MX8M{M/P} SoCs PCIe
PHY initialization moved to this standalone PHY driver.
Inspired from counterpart Linux kernel v6.8-rc3 driver:
drivers/phy/freescale/phy-fsl-imx8m-pcie.c. Use last Linux kernel driver
reference commit 7559e7572c03 ("phy: Explicitly include correct DT
includes").
Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice*
Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
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Expose the high performance PLL as clock framework clock, so the
PCIe PHY can use it when there is no external refclock provided.
Inspired from counterpart Linux kernel v6.8-rc3 driver:
drivers/pmdomain/imx/imx8mp-blk-ctrl.c. Use last Linux kernel driver
reference commit 7476ddfd36ac ("pmdomain: imx8mp-blk-ctrl: Convert to
platform remove callback returning void").
Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice*
Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
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Add support for GPCv2 power domains and clock handling for PCIe and
PCIe PHY.
Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice*
Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
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Add support for i.MX8MP reset controller, it has same reset IP inside
as the other iMX7 and iMX8M variants but with different module layout.
Inspired from counterpart Linux kernel v6.8-rc3 driver:
drivers/reset/reset-imx7.c. Use last Linux kernel driver reference
commit bad8a8afe19f ("reset: Explicitly include correct DT includes").
Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice*
Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
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imx7_reset_{deassert/assert}_imx* are a bit more confusing when compared
with imx*_reset_{deassert/assert}. So refactor driver to use function
names easier to understand. This shouldn't affect the functionality
though.
Suggested-by: Marek Vasut <marex@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
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Add support for PCIe clocks required to enable PCIe support on
iMX8MP SoC.
Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice*
Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
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Add APIs to set a firmware_name to a rproc and boot the rproc with the
same firmware.
Clients can call rproc_set_firmware() API to set firmware_name for a rproc
whereas rproc_boot() will load the firmware set by rproc_set_firmware() to
a buffer by calling request_firmware_into_buf(). rproc_boot() will then
load the firmware file to the remote processor and start the remote
processor.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
Acked-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
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The K3 J721S2 SoCs have two C71x DSP subsystems in MAIN voltage domain,
and there are no C66x DSP subsystems on these SoCs. The C71x DSP subsystem
is a slighly updated version of the C71x DSP subsystem on J721e. The
C71x DSPs are 64 bit machine with fixed and floating point DSP
operations.
Extend support to the C71x DSPs with J721S2 compatible strings.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
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The K3 J721S2 SoCs have three dual-core R5F subsystems, one in MCU
voltage domain and the other two in MAIN voltage domain. These R5F
clusters are similar to the R5F clusters in J7200 SoCs.
Compatible Info is updated to support J721S2 SoCs.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
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Since commit cc7df0b9e8bc ("serial: lpuart: Enable IPG clock")
the apalis-imx8qm board no longer boots.
The reason is that the imx8qm clock driver does not handle the
LPUART IPG clocks inside get_rate(), set_rate() and enable() functions.
Fix the boot regression by adding the LPUART IPG entries.
Fixes: cc7df0b9e8bc ("serial: lpuart: Enable IPG clock")
Reported-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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Since commit cc7df0b9e8bc ("serial: lpuart: Enable IPG clock")
the colibri-imx8qxp board no longer boots.
The reason is that the imx8qxp clock driver does not handle the
LPUART IPG clocks inside get_rate(), set_rate() and enable() functions.
Fix the boot regression by adding the LPUART IPG entries.
Fixes: cc7df0b9e8bc ("serial: lpuart: Enable IPG clock")
Reported-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Hiago De Franco <hiago.franco@toradex.com> # Toradex Colibri iMX8X
Acked-by: Sean Anderson <seanga2@gmail.com>
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The priv struct was wrong in dump_boot_mappings(). Causing errors when
compiling with -DDEBUG. Fix this.
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Link: https://lore.kernel.org/r/20240320-b4-qcom-usb-v4-5-41be480172e1@linaro.org
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
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UFS storage often uses a 4096-byte sector size, add support for dynamic
sector sizes based loosely on the Linux implementation.
Support for dynamic sector sizes changes the types used in some
divisions, resulting in the compiler attempting to use
libgcc helpers (__aeabi_ldivmod).
Replace these divisions with calls to lldiv() to handle this correctly.
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Link: https://lore.kernel.org/r/20240320-b4-qcom-usb-v4-4-41be480172e1@linaro.org
[mkorpershoek: squashed the lldiv() fix from caleb]
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
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To actually use the gadget the peripheral driver must be probed and we
must call g_dnl_clear_detach(). Otherwise acm_stdio_start() will always
fail to find a UDC on DT platforms.
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Link: https://lore.kernel.org/r/20240320-b4-qcom-usb-v4-3-41be480172e1@linaro.org
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
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https://source.denx.de/u-boot/custodians/u-boot-efi into next
Pull request efi-next-20240321
Documentation:
* Avoid short reference link names in device-tree documentation.
UEFI/Video:
* Support code page 437 code points 1 - 31 used by GRUB
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The Qualcomm specific dwc3 wrapper isn't hugely complicated, implemented
the missing initialisation for host and gadget mode.
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Link: https://lore.kernel.org/r/20240320-b4-qcom-usb-v4-1-41be480172e1@linaro.org
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
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efi_console / UEFI applications (grub2, sd-boot, ...) pass UTF-8
character sequences to vidconsole which results in wrong glyphs for code
points outside of ASCII. The truetype console expects Unicode code
points and bitmap font based consoles expect code page 437 code points.
To support both convert UTF-8 to UTF-32 and pass Unicode code points in
vidconsole_ops.putc_xy(). These can be used directly in console_truetype
and after conversion to code page 437 in console_{normal,rotate}.
This fixes rendering of international, symbol and box drawing characters
used by UEFI applications.
Signed-off-by: Janne Grunau <j@jannau.net>
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Signed-off-by: Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com>
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https://source.denx.de/u-boot/custodians/u-boot-socfpga into next
- A new driver in the misc to register setting from device tree. This
also provides user a clean interface and all register settings are
centralized in one place, device tree.
- Enable Agilex5 platform for Intel product. Changes, modification and
new files are created for board, dts, configs and makefile to create
the base for Agilex5.
Build-tested on SoC64 boards, boot tested on some of them.
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This patch is to enable Agilex5 platform for Intel
product. Changes, modification and new files are
created for board, dts, configs and makefile to
create the base for Agilex5.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
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Add socfpga_dtreg driver enablement for Intel SoCFPGA.
Signed-off-by: Wan Yee Lau <wan.yee.lau@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
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The polling rate is already specified in some devicetrees, like
imx8mp.dtsi for example, but was not selected so far. For the
trippoints, the cpu-thermal node is used. Also get the polling rate from
this node. Use the default of 5000ms if the polling rate should not be
specified in the devicetree.
NOTE: The polling rate from the devicetree will be used after this
patch. In imx8*.dtsi devicetrees the polling delay is set to 2000ms for
example.
Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
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https://source.denx.de/u-boot/custodians/u-boot-rockchip into next
Please pull the updates for rockchip platform:
- Add board: rk3588 Generic, Cool Pi CM5, Theobroma-Systems RK3588 Jaguar SBC,
Toybrick TB-RK3588X;
rk3588s Cool Pi 4B;
rk3566 Pine64 PineTab2;
- Add saradc v2 support;
- Add PMIC RK806 support;
- rk3588 disable force_jtag by default;
- Migrate to use IO-domain driver for all boards;
- Use common bss and stack addresses for rk33xx and rk35xx boards;
- Other updates for driver, config and dts;
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