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2023-03-19rockchip: timer: rockchip_timer: fix compatible and driver nameJohan Jonker
In the binding for the Rockchip timer the compatible string consists of a SoC orientated string and a fall back string "rockchip,rk3288-timer", so remove all unneeded ones and fix driver name. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-03-19rockchip: sdhci: rk3568: bypass DLL when clk <= 52 MHzVasily Khoruzhick
For Rockchip platform, DLL bypass bit and start bit need to be set if DLL is not locked. With this change applied eMMC in my NanoPi R5S can run at 52 MHz. Based on linux commit b75a52b0dda3 ("mmc: sdhci-of-dwcmshc: Update DLL and pre-change delay for rockchip platform") Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-03-19clk: rockchip: rk3568: add stubs for CLK_PCIEPHY_REF clocksVasily Khoruzhick
Device tree contains assigned-clock-rates property for these, but default value will work just fine Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2023-03-19mmc: rockchip_dw_mmc: Fix get_mmc_clk return valueJonas Karlman
The get_mmc_clk ops is expected to set a clock rate and return the configured rate as an unsigned value. However, if clk_set_rate fails, e.g. using a fixed rate clock, a negative error value is returned. The mmc core will treat this as a valid unsigned rate and tries to configure a divider based on this bogus clock rate. Use 0 as the return value when setting clock rate fails, the mmc core will configure to use bypass mode instead of using a bogus divider. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-03-19clk: rockchip: rk3588: Fix clk_aux16m in clock driverJonas Karlman
The rate and error value is not returned for aux16m clocks, fix this. Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-03-19clk: rockchip: rk3568: Fix reset handlerPeter Geis
The reset handler for rk3568 is missing its private data. This leads to an abort when a reset is triggered. => reset resetting ... "Synchronous Abort" handler, esr 0x96000045 elr: 0000000000a2bc04 lr : 0000000000a2bbd4 (reloc) elr: 00000000eff9bc04 lr : 00000000eff9bbd4 x0 : 00000000fdd20000 x1 : 0000000014000001 x2 : 000000000000fdb9 x3 : 00000000edf77e88 x4 : 00000000edf50e78 x5 : 00000000edf77530 x6 : 000000000000001d x7 : 00000000edf8a1d0 x8 : 00000000ffffffd8 x9 : 0000000000000008 x10: 000000000000000d x11: 0000000000000006 x12: 000000000001869f x13: 0000000086c290c5 x14: 000000009118e878 x15: 0000000000000000 x16: 00000000eff9bbb8 x17: 0000000012f8c119 x18: 00000000edf50dc0 x19: 0000000000000000 x20: 0000000000000001 x21: 0000000000000000 x22: 00000000edf85900 x23: 0000000000000001 x24: 00000000effe8bbc x25: 0000000000000000 x26: 00000000edf85940 x27: 0000000000000000 x28: 0000000000000000 x29: 00000000edf3c8e0 Code: d65f03c0 d5033fbf b9400661 529d9502 (b8216802) Resetting CPU ... Add the missing dev_set_priv to the rk3568 clk driver to fix this. Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver") Signed-off-by: Peter Geis <pgwipeout@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # radxa-cm3 Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2023-03-10Merge https://source.denx.de/u-boot/custodians/u-boot-usbTom Rini
Two minimal Kconfig/Makefile fixes for USB.
2023-03-10ARM: dts: renesas: Enable sysinfo on R-Car V3H Condor/Condor-ITam Nguyen
Add new sysinfo IDs for R-Car V3H Condor/Condor-I . Enable support for sysinfo on R-Car V3H Condor/Condor-I. The sysinfo is used e.g. to access and decode board-specific information and then in turn used by board-info to print those information. Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> [Marek: Drop compatible from I2C node, this is in r8a77980.dtsi already. Drop status = "okay" from EEPROM node. Add dts: tag. Update the commit message, note the new sysinfo IDs. Fix Kconfig EEPROM address to be 0x50 and match the DT, sync config.]
2023-03-10sysinfo: rcar3: Fix Draak and Eagle board codeTam Nguyen
Correct the board code ID based on the hardware documentation Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-10pinctrl: renesas: Drop non-existent PFC info table entriesMarek Vasut
Remove PFC info table entries which are never instantiated, since there are no drivers for those. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-10clk: renesas: Always select DM_RESET to prevent inobvious failure of ↵Marek Vasut
rst_gen3 subdriver The CLK_RCAR_GEN3 registers two subdrivers, clk_gen3 and rst_gen3. The former depends on the clock framework, which is always enabled in this context of clock framework driver, while the later depends on reset framework which may not always be enabled. Ensure the reset framework is also always enabled to prevent inobvious early boot time bind failure of the CPG driver, which leads to system showing no activity and is difficult to debug. Note that one possible approach to debug this is to use CONFIG_DEBUG_UART and add debug printascii()s into the drivers/clk/renesas/clk-rcar-gen3.c . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-10mmc: renesas-sdhi: Add proper probe error fail pathMarek Vasut
In case one of the calls in probe fail, trigger a fail path and undo all the steps done in probe until the point of failure. The current implementation failed to stop controller clock and free claimed clock, so fix that. Furthermore, print return code in error prints for easier debugging. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-10mmc: renesas-sdhi: Always configure default SDnH clock rate to 800 MHzMarek Vasut
The prior stage bootloader might have left the SDnCKCR register in completely arbitrary state before passing control to U-Boot, which includes the register being populated with incorrect values. Currently the SDHI driver will attempt to use clock framework to configure SDn clock, which may fail in case SDnCKCR contains invalid values for the SDnH clock, because the clock framework would not be able to determine SDnH clock rate and would get -EINVAL instead, which in turn would not allow the clock framework to determine the correct SDn clock divider ratio. This failure occurs specifically in case SDnCKCR reads back 0x209 . Correct the problem by first setting default SDnH clock rate to 800 MHz, thus assuring the SDnCKCR SDnH bits are correct, and only afterward set up the SDn clock rate to default 200 MHz. Note that the SDHI driver may reconfigure SDnH clock later based on IOS settings obtained from the attached card, the 800 MHz set up here is only the default value. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-10usb: move CONFIG_USB_HUB_DEBOUNCE_TIMEOUT to USBHeinrich Schuchardt
This configuration setting is only relevant if the board supports USB. It should not be in the main menu but in the USB menu. The setting is only relevant in USB host mode. Fixes: 5454dea3137d ("usb: hub: allow to increase HUB_DEBOUNCE_TIMEOUT") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-03-01sandbox: fix building with CONFIG_SPL_TIMER=yHeinrich Schuchardt
Building sandbox_defconfig with CONFIG_SPL_TIMER=y results in an error include/dm/platdata.h:63:33: error: static assertion failed: "Cannot use U_BOOT_DRVINFO with of-platdata. Please use devicetree instead" Add a missing condition in the sandbox driver. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-01arm64: a37xx: pinctrl: probe after bindingRobert Marko
Currently, pinctrl drivers are getting probed during post-bind, however that is being reverted, and on A37XX pinctrl driver is the one that registers the GPIO driver during the probe. So, if the pinctrl driver doesn't get probed GPIO-s won't get registered and thus they cannot be used. This is a problem on the Methode eDPU as it just uses SB pins as GPIO-s and without them being registered networking won't work as it only has one SFP slot and the TX disable GPIO is on the SB controller. So, lets just add a flag only to A37XX driver to probe after binding in order for the GPIO driver to always get registered. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-28clk: rockchip: rk3568: add more supported clk rates for sdmmc and emmcVasily Khoruzhick
SDHCI driver may attempt to set 26MHz clock, but clk_rk3568 will return error in this case. Apparently, SDHCI silently ignores the error and as a result eMMC initialization fails. Add 25 MHz and 26 MHz clk rates for sdmmc and emmc on rk3568 to fix that. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: efuse: Add support for RK3036Jonas Karlman
Add support for rk3036 compatible. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: efuse: Add support for RK3128Jonas Karlman
Add support for rk3128 compatible. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: efuse: Add support for RK3328Jonas Karlman
Add support for rk3328 compatible. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: efuse: Add support for RK3288 and moreJonas Karlman
Add support for rk3066a, rk3188, rk322x and rk3288 compatible. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: efuse: Refactor to use driver data and opsJonas Karlman
Refactor the driver to use driver data and ops to simplify handling of SoCs that require a unique read op. Move handling of the aligned bounce buffer to main read op in order to keep the SoC unique read op simple. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: otp: Add dump_otp debug commandJonas Karlman
Add a simple debug command to dump the content of the otp. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: otp: Add support for RK3588Jonas Karlman
Add support for rk3588 compatible. Adjust offset using driver data in main read op. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: otp: Add support for RK3568Jonas Karlman
Add support for rk3568 compatible. Handle allocation of an aligned bounce buffer in main read op in order to keep the SoC unique read op simple. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: otp: Refactor to use driver data and opsJonas Karlman
Refactor the driver to use driver data and ops to simplify handling of SoCs that require a unique read op. Use readl_poll_sleep_timeout instead of a custom poll loop, and add validation of input parameter to main read op. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28ram: rockchip: Add rk3588 ddr driver supportJagan Teki
Add ddr driver for rk3588 to get the ram capacity. Co-developed-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28clk: rockchip: pll: Add pll_rk3588 type for rk3588Jagan Teki
Add RK3588 pll set and get rate clock support. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28clk: rockchip: Add rk3588 clk supportJagan Teki
Add clock driver support for Rockchip RK3588 SoC. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28gpio: gpio-rockchip: parse gpio-ranges for bank idChris Morgan
Use the new devicetree property of gpio-ranges to determine the GPIO bank ID. Preserve the "old" way of doing things too, so that boards can be migrated and tested gradually (I only have a 3566 and 3326 to test). Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: rk3568: add rk3568 pinctrl driverJagan Teki
Add driver supporting pin multiplexing on rk3568 platform. Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Co-developed-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28drivers: phy: add naneng combphy for rk3568Jagan Teki
RK3568 has three combo phys, and PCIe/USB3/SATA/QSGMII controllers share one pipe interface for each combo phy, here is the diagram of the complex connection. +----------------+ | | +------+ | USB3 OTG CTRL0 |---->| | | | | | +------------+ +----------------+ | PIPE | | | | MUX |---->| Combo PHY0 | +----------------+ | | | | | | | | +------------+ | SATA CTRL0 |---->| | | | +------+ +----------------+ +----------------+ | | +------+ | USB3 HOST CTRL1|---->| | | | | | +------------+ +----------------+ | PIPE | | | | MUX |---->| Combo PHY1 | +----------------+ | | | | | |---->| | +------------+ | SATA CTRL1 | -->| | | | | +------+ +----------------+ | | +----------------+ | | | | +------+ | QSGMII CTRL |---->| | | | | | +------------+ +----------------+ | PIPE | | | | MUX |---->| Combo PHY2 | +----------------+ | | | | | |---->| | +------------+ | SATA CTRL2 | -->| | | | | +------+ +----------------+ | | +----------------+ | | | | | PCIe2 1-Lane |--- | | +----------------+ Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Co-developed-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28phy: rockchip-inno-usb2: Add USB2 PHY for rk3568Manoj Sai
RK3568 has two USB 2.0 PHYs, and each PHY has two ports, the OTG port of PHY0 support OTG mode with charging detection function, they are similar to previous Rockchip SoCs. However, there are three different designs for RK3568 USB 2.0 PHY. 1. RK3568 uses independent USB GRF module for each USB 2.0 PHY. 2. RK3568 accesses the registers of USB 2.0 PHY IP directly by APB. 3. The two ports of USB 2.0 PHY share one interrupt. This patch only PHY1 with necessary attributes required to function USBPHY1 on U-Boot. Co-developed-by: Ren Jianing <jianing.ren@rock-chips.com> Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com> Co-developed-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28phy: rockchip: inno-usb2: Add support #address_cells = 2Jagan Teki
New Rockchip devices have the usb phy nodes as standalone devices. These nodes have register nodes with #address_cells = 2, but only use 32 bit addresses. Adjust the driver to check if the returned address is "0", and adjust the index in that case. Derived and adjusted the similar change from linux-next with below commit <9c19c531dc98> ("phy: phy-rockchip-inno-usb2: support #address_cells = 2") Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28mmc: rockchip_dw_mmc: fix DDR52 8-bit mode handlingJohn Keeping
The RK3288 TRM states that, for 8-bit DDR modes: The CLKDIV register should always be programmed with a value higher than zero (0); that is, a clock divider should always be used for 8-bit DDR mode. In Linux, the driver applies this logic for all SoCs using the driver and does not distinguish RK3288, so presumably this requirement is the same for all other Rockchip SoCs using this IP. Add the necessary code to double the clock frequency when 8-bit DDR is selected. The dw_mmc core already handles setting CLKDIV correctly given the input clock and desired bus clock. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-02-23ARM: tegra: provide default USB gadget setupMaxim Schwalm
All Nvidia boards use the same manufacturer, vendor ID and product ID for the gadgets. Make them the defaults to remove some boilerplate from the defconfigs. Inspired by commit e02687bda96c ("sunxi: provide default USB gadget setup") which did the same for Allwinner boards. Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124 Signed-off-by: Maxim Schwalm <maxim.schwalm@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23spi: tegra20_slink: accept any word lengthSvyatoslav Ryhel
Original t20 slink could work with commands only fully divisible by 8. This patch removes such restriction, so commands of any bitlength now can be passed and processed. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: tegra: Fix Tegra PWM parent clockSvyatoslav Ryhel
Default parent clock for the PWM on Tegra is a 32kHz clock and is unable to support the requested PWM period. Fix PWM support on Tegra20, Tegra30, Tegra114, Tegra124 and Tegra210 by updating the parent clock for the PWM to be the PLL_P. This commit is equivalent to Linux kernel commit: https://lore.kernel.org/all/20221010100046.6477-1-jonathanh@nvidia.com/ Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # ASUS TF201 T30 Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-22usb: dwc3: Use the devm_gpiod_get_optional() API for reset gpioVenkatesh Yadav Abbarapu
As the "reset-gpios" property is optional, don't return the error and just skip the gpio reset sequence. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
2023-02-17cpsw_mdio.c: Use correct reg in cpsw_mdio_get_aliveUlf Samuelsson
cpsw_mdio_get_alive reads the wrong register. See page 2316 in SPRUH73Q AM335x TRM Signed-off-by: Ulf Samuelsson <ulf@emagii.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2023-02-17driver: cache-v5l2: Fix type casting warning on RV32Yu Chien Peter Lin
This patch fixes following warning for the riscv32 toolchain. drivers/cache/cache-v5l2.c:122:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 122 | regs = (struct l2cache *)dev_read_addr(dev); | ^ Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-02-17riscv: ae350: dts: Update L2 cache compatible stringYu Chien Peter Lin
Update the compatible string of L2 cache. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17driver: cache: cache-v5l2: Update memory-mapped scheme to support Gen2 platformYu Chien Peter Lin
The L2C configuration register has MAP field to indicate its version is v0 (Gen1) or v1 (Gen2) L2-cache. This patch makes the driver compatible with both memory-mapped scheme. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"Leo Yu-Chi Liang
There is no need for RISCV_NDS_CACHE config to control cache switches. Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-13i2c: i2c-cdns.c: Update driver to read fifo-depth from device treePei Yue Ho
Enable driver to fetch the optional parameter (fifo-depth) from device tree. If the parameter is not found in the device tree, it will use the default value declared in the driver. Signed-off-by: Pei Yue Ho <peiyue.ho@starfivetech.com> Reviewed-by: Wei Liang Lim <weiliang.lim@starfivetech.com> Reviewed-by: Eng Lee Teh <englee.teh@starfivetech.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2023-02-13i2c:aspeed:support ast2600 i2c new register mode driverRyan Chen
Add i2c new register mode driver to support AST2600 i2c new register mode. AST2600 i2c controller have legacy and new register mode. The new register mode have global register support 4 base clock for scl clock selection, and new clock divider mode. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2023-02-13i2c: mxc_i2c: Use hex notation for the base addressFabio Estevam
Printing the I2C controller base address in decimal notation is not helpful. Change it to hex notation, which is the standard format found in the Reference Manual and devicetree. Signed-off-by: Fabio Estevam <festevam@denx.de> Acked-by: Dhruva Gole <d-gole@ti.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2023-02-12Merge tag 'clk-2023.04-rc1' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-clk Clock changes for 2023.04-rc1 This contains various fixes and small features. I've included a reset patch as well since it was in the same series as a clock patch.
2023-02-12Merge branch 'for-2023.04' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-mpc8xx - A fix for a long standing bug that has been exposed by commit 50128aeb0f8 ("cyclic: get rid of cyclic_init()") preventing 8xx boards from booting since u-boot 2023.01 - A GPIO driver for powerpc 8xx chip - Fixup for powerpc 8xx SPI driver - A new powerpc 8xx board - The two devices having that board.
2023-02-12reset: Allow reset_get_by_name() with NULL nameSamuel Holland
This allows devm_reset_control_get(dev, NULL) to work and get the first reset control, which is common in code ported from Linux. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20230122000252.53642-2-samuel@sholland.org
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