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2023-03-18serial: sh: Make indent consistentMarek Vasut
Make the indent of these macro elements consistent with the rest of this table. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-18serial: sh: Add DEBUG_UART supportMarek Vasut
Add support for debug output very early during boot using the DEBUG_UART mechanism. This uses a static fixed UART port configuration selected via Kconfig options and dedicated print functions from debug_uart.h. This is useful e.g. when debugging problems so early during boot, that not even the DM is initialized at that point, and thus DM_SERIAL is not available either. This functionality is disabled by default. To activate it, define the following Kconfig options and select SCIF type using CFG_SCI/CFG_SCIF_A/ CFG_HSCIF/<nothing for regular SCIF>: CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_SCIF=y CONFIG_DEBUG_UART_BASE=0xe6540000 CONFIG_DEBUG_UART_CLOCK=24000000 The later two options define the SCIF physical base address and SCIF input clock in Hz. Optionally, to validate DEBUG_UART works, enable the following as well to get early serial output message by default: CONFIG_DEBUG_UART_ANNOUNCE=y Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-18serial: sh: Rename CONFIG_SCI and CONFIG_SCIF_USE_EXT_CLK to CFG_ variantsMarek Vasut
Both CONFIG_SCI and CONFIG_SCIF_USE_EXT_CLK options do not have a matching Kconfig entry because they are internal to the SCIF driver. Change their prefix to CFG_, i.e. CFG_SCIF_USE_EXT_CLK and CFG_SCI, to reflect that and avoid interferring with Kconfig symbols. Since neither of those options are defined elsewhere, no functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-18pinctrl: renesas: Replace ifdeffery with IS_ENABLED()Marek Vasut
Switch ifdef in sh_gpio_get_value() to IS_ENABLED() macro. The CONFIG_RCAR_GEN3 will never have SPL counterpart, so the IS_ENABLED() macro is the right one here. No functional change, except for improved build test coverage. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-18net: ravb: Support fixed PHY in R-CarMikhail Lappo
Calling old U-Boot API doesn't allow to use fixed PHY. Searching by mask is the part of new function, after scanning FDT for a fixed PHY definition Fixes: e821a7bdb13 ("net: ravb: Detect PHY correctly") Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Mikhail Lappo <mikhail.lappo@esrlabs.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> [Hai Pham: Drop phy_connect_dev since it's called in phy_connect] Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> [Marek: Use mask -1 instead of 0 to reinstate the search behavior over all PHY addresses. Add Fixes tag, sort the tag list.]
2023-03-18i2c: rcar_i2c: Sort Kconfig depends list ascendingMarek Vasut
Sort the list of "depends" symbols in ascending order. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2023-03-18i2c: rcar_iic: Sort Kconfig depends list ascendingMarek Vasut
Sort the list of "depends" symbols in ascending order. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2023-03-18clk: renesas: rcar-gen3: Replace SSCG caching with MDSEL/PE cachingMarek Vasut
Do not cache the single CPG MODE register bit 12, instead cache the entire register value, and only pick the matching bit from the cached value when core clock of type MDSEL or PE are used. Both MDSEL and PE clock type currently define .offset field as 12 on Gen3, which means this code will use bit 12 on Gen3 again, however there are additional clock on Gen4 which use different bits, and having this flexibility in place now will be useful when adding Gen4. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-16Merge tag 'xilinx-for-v2023.07-rc1' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2023.07-rc1 cmd: - Print results in hex instead of dec in smc command firmware: - Cover missing ZYNQMP_FIRMWARE dependencies fpga: - fix loads for unencrypted use case relocation - Add support for BE systems spi: - Fix xilinx_spi init reset sequence arasan nand: - Remove hardcoded bbt option - Set ofnode value xilinx: - Enable SMC command - Fix some sparse issues zynqmp: - Remove cdns,zynq-gem compatible string - Add optee node - Some DT cleanups zynq: - Some DT cleanups microblaze - Remove MANUAL_RELOC option
2023-03-16Revert 9f62a472dfb2 ("video: Remove duplicate cursor-positioning function")Tom Rini
This reverts commit 9f62a472dfb26ec14408a27938ddd2a25700009d. The changes here aren't quite right, and on platforms such as Raspberry Pi where we can have both serial and video output, the change above causes output to change. This can be seen as the hush tests we have now fail. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-14Merge tag 'v2023.04-rc4' into nextTom Rini
Prepare v2023.04-rc4 Signed-off-by: Tom Rini <trini@konsulko.com>
2023-03-13video: Clear the vidconsole rather than the videoSimon Glass
It is better to clear the console device rather than the video device, since the console has the text display. We also need to reset the cursor position with the console, but not with the video device. Add a new function to handle this and update the 'cls' command to use it. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-13video: Remove duplicate cursor-positioning functionSimon Glass
There are two functions for positioning the cursor on the console. Remove one of them. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-13video: Allow a copy framebuffer with pre-allocated fbSimon Glass
At present it is not possible for the video driver to use a pre-allocated frame buffer (such as is done with EFI) with the copy framebuffer. This can be useful to speed up the display. Adjust the implementation so that copy_size can be set to the required size, with this being allocated if the normal framebuffer size is 0. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-13efi: Support copy framebufferSimon Glass
Add support for this to EFI in case it becomes useful. At present it just slows things down. You can enable CONFIG_VIDEO_COPY to turn it on. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-13efi: Use a fixed value for the timer clockSimon Glass
It is not yet clear how to read the timer via EFI. The current value seems much too high on a Framework laptop I tried. Adjust it to a lower hard-coded value for now. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-13efi: Support a 64-bit frame buffer addressSimon Glass
The current vesa structure only provides a 32-bit value for the frame buffer. Many modern machines use an address outside the range. It is still useful to have this common struct, but add a separate frame-buffer address as well. Add a comment for vesa_setup_video_priv() while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-13efi: video: Return mode info for app alsoSimon Glass
The mode info is currently not initialised for the app. Fix this by returning it from the function. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-13efi: video: Move payload code into a functionSimon Glass
Put this into a function, as we have done for the app implementation. Comment both functions. FOr now the app still does not access it correctly. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-10Merge https://source.denx.de/u-boot/custodians/u-boot-usbTom Rini
Two minimal Kconfig/Makefile fixes for USB.
2023-03-10ARM: dts: renesas: Enable sysinfo on R-Car V3H Condor/Condor-ITam Nguyen
Add new sysinfo IDs for R-Car V3H Condor/Condor-I . Enable support for sysinfo on R-Car V3H Condor/Condor-I. The sysinfo is used e.g. to access and decode board-specific information and then in turn used by board-info to print those information. Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> [Marek: Drop compatible from I2C node, this is in r8a77980.dtsi already. Drop status = "okay" from EEPROM node. Add dts: tag. Update the commit message, note the new sysinfo IDs. Fix Kconfig EEPROM address to be 0x50 and match the DT, sync config.]
2023-03-10sysinfo: rcar3: Fix Draak and Eagle board codeTam Nguyen
Correct the board code ID based on the hardware documentation Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-10pinctrl: renesas: Drop non-existent PFC info table entriesMarek Vasut
Remove PFC info table entries which are never instantiated, since there are no drivers for those. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-10clk: renesas: Always select DM_RESET to prevent inobvious failure of ↵Marek Vasut
rst_gen3 subdriver The CLK_RCAR_GEN3 registers two subdrivers, clk_gen3 and rst_gen3. The former depends on the clock framework, which is always enabled in this context of clock framework driver, while the later depends on reset framework which may not always be enabled. Ensure the reset framework is also always enabled to prevent inobvious early boot time bind failure of the CPG driver, which leads to system showing no activity and is difficult to debug. Note that one possible approach to debug this is to use CONFIG_DEBUG_UART and add debug printascii()s into the drivers/clk/renesas/clk-rcar-gen3.c . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-10mmc: renesas-sdhi: Add proper probe error fail pathMarek Vasut
In case one of the calls in probe fail, trigger a fail path and undo all the steps done in probe until the point of failure. The current implementation failed to stop controller clock and free claimed clock, so fix that. Furthermore, print return code in error prints for easier debugging. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-10mmc: renesas-sdhi: Always configure default SDnH clock rate to 800 MHzMarek Vasut
The prior stage bootloader might have left the SDnCKCR register in completely arbitrary state before passing control to U-Boot, which includes the register being populated with incorrect values. Currently the SDHI driver will attempt to use clock framework to configure SDn clock, which may fail in case SDnCKCR contains invalid values for the SDnH clock, because the clock framework would not be able to determine SDnH clock rate and would get -EINVAL instead, which in turn would not allow the clock framework to determine the correct SDn clock divider ratio. This failure occurs specifically in case SDnCKCR reads back 0x209 . Correct the problem by first setting default SDnH clock rate to 800 MHz, thus assuring the SDnCKCR SDnH bits are correct, and only afterward set up the SDn clock rate to default 200 MHz. Note that the SDHI driver may reconfigure SDnH clock later based on IOS settings obtained from the attached card, the 800 MHz set up here is only the default value. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-10usb: move CONFIG_USB_HUB_DEBOUNCE_TIMEOUT to USBHeinrich Schuchardt
This configuration setting is only relevant if the board supports USB. It should not be in the main menu but in the USB menu. The setting is only relevant in USB host mode. Fixes: 5454dea3137d ("usb: hub: allow to increase HUB_DEBOUNCE_TIMEOUT") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-03-09xilinx: zynqmp: Add missing prototype for zynqmp_mmio_writeAlgapally Santosh Sagar
Add missing prototype to fix the sparse warning, warning: no previous prototype for 'zynqmp_mmio_write' [-Wmissing-prototypes]. Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230301103334.1455-2-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-09mtd: nand: arasan: Set ofnode valueAshok Reddy Soma
Ofnode value is not set, so all the DT properties are not being read and due to this default values are being used. Find nand node and set chip->flash_node value. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230224050709.30014-3-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-09mtd: nand: arasan: Remove hardcoded bbt optionAshok Reddy Soma
Bad block table option is hardcoded to read from flash with NAND_BBT_USE_FLASH option. This decision should be done based on DT property. Remove this hardcoding, to be able to use DT property. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230224050709.30014-2-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-09spi: xilinx_spi: Fix spi resetJiajie Chen
It was incorrectly using an old priv->regs pointer, which was initialized to zero. SPI resets won't happen on first call. Signed-off-by: Jiajie Chen <c@jia.je> Link: https://lore.kernel.org/r/20230227150938.211820-1-c@jia.je Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-09fpga: zynqmppl: fix fpga loads command for unencrypted use caseNeal Frager
When using the fpga loads command, the driver is passing the AES encryption key address is all cases. However, for the authenticated, but not encrypted use case, there is no AES encryption key, and this value is 0. When AES encryption is not used on the fpga bitstream, the pmufw assumes that the AES key address is a bitstream size value like what is used by the unsecure fpga load command. To fix the problem, this patch checks to see if the AES key address is zero. If the AES key address is zero, it means that AES is not being used on the bitstream and the bitstream size should be passed instead. Thus, matching the fpga load functionality. Signed-off-by: Neal Frager <neal.frager@amd.com> Acked-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230214131959.40298-1-neal.frager@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-09arm64: zynqmp: Add missing ZYNQMP_FIRMWARE dependenciesAlgapally Santosh Sagar
There are missing Kconfig dependencies in the code which is using firmware interface. The commit 71efd45a5fc7 ("arm64: zynqmp: Change firmware dependency") add option to also disable ZYNQMP_FIRMWARE. But not all Kconfig dependencies were properly described and also sdhci and gem drivers didn't protect the code properly. So, add the missing ZYNQMP_FIRMWARE dependencies. Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230201095553.11219-1-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-07Merge tag 'next-20230307' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-video into next - video console refactoring and optimization - support for fonts wider than 1 byte - use named header for 8x16 font data - support multiple fonts configuration - move get_font_size() to truetype driver ops - support font size configuration at runtime - add 16x32 Terminus font from linux - add 12x22 Sun font from linux - add 12x22 console simple font test
2023-03-07video console: add 16x32 Terminus font from linuxDzmitry Sankouski
Modern mobile phones typically have high pixel density. Bootmenu is hardly readable on those with 8x16 font. Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-07video console: add 12x22 Sun font from linuxDzmitry Sankouski
Modern mobile phones typically have high pixel density. Bootmenu is hardly readable on those with 8x16 font. Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-07video console: allow font size configuration at runtimeDzmitry Sankouski
Allow font size configuration at runtime for console_simple.c driver. This needed for unit testing different fonts. Configuring is done by `font` command, also used for font selection in true type console. Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-07video console: move vidconsole_get_font_size() logic to driver opsDzmitry Sankouski
Since multiple vidconsole drivers exists, vidconsole_get_font_size() implementation cannot longer live in vidconsole_uclass.c file. Move current vidconsole_get_font_size logic to truetype driver ops. Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-07video console: implement multiple fonts configurationDzmitry Sankouski
This needed for unit testing different fonts. Configured fonts are placed in an array of fonts. First font is selected by default upon console probe. Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> [agust: fixed build error when bmp logo disabled] Signed-off-by: Anatolij Gustschin <agust@denx.de>
2023-03-07video console: add support for fonts wider than 1 byteDzmitry Sankouski
Devices with high ppi may benefit from wider fonts. Current width implementation is limited by 1 byte, i.e. 8 bits. New version iterates VIDEO_FONT_BYTE_WIDTH times, to process all width bytes, thus allowing fonts wider than 1 byte. Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-07video console: refactoring and optimizationDzmitry Sankouski
- move common code to vidconsole_internal.h and console_core.c - unite probe functions - get rid of code duplications in switch across bpp values - extract common pixel fill logic in two functions one per horizontal and vertical filling - rearrange statements in put_xy* methods in unified way - replace types - uint*_t to u* Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-06mmc: remove SDHCI SPEARPatrick Delaunay
As the file spear_sdhci.c file is already removed, delete the associated configuration CONFIG_MMC_SDHCI_SPEAR. Fixes: c942fc925e7dab ("mmc: spear: remove the entire spear_sdhci.c file") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-03-06clk: ast2600: Keep PLL power onDylan Hung
According to the PLL vendor, we should keep the PLL power on, so we shouldn't toggle the power-down bit during PLL initialization. Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au>
2023-03-06ram: ast2600: Keep MPLL power onDylan Hung
According to the PLL vendor, we should keep the PLL power on, so we shouldn't toggle the power-down bit during PLL initialization. Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au>
2023-03-06timer: fttmr010: return a previously deleted driver now ported to DMSergei Antonov
The fttmr010 timer driver was deleted by commit 29fc6f24926e ("ARM: remove a320evb board support") The original source file was: arch/arm/cpu/arm920t/a320/timer.c Return the driver to the codebase in a DM compatible form. A platform using fttmr010 will be submitted later. This hardware is described in the datasheet [1], starting from page 348. According to the datasheet, there is a Revision Register at offset 0x3C, which is not present in 'struct fttmr010'. Add it and debug() print revision in probe function. [1] https://bitbucket.org/Kasreyn/mkrom-uc7112lx/src/master/documents/FIC8120_DS_v1.2.pdf Signed-off-by: Sergei Antonov <saproj@gmail.com>
2023-03-03Merge branch '2023-03-02-kconfig-and-CONFIG-cleanups' into nextTom Rini
- Partial merge of a series of mine to select some framework options that shouldn't be prompted for (and remove some unused code related to that), and a partial merge of a series from Simon to remove some dead code and address various CONFIG_IS_ENABLED/IS_ENABLED issues in code.
2023-03-03dm: Add a TPL symbol for simple-busSimon Glass
This is used in some x86 code, so add a symbol for it. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-03net: Add an SPL config for atherosSimon Glass
Add a new SPL_PHY_ATHEROS to avoid a build error on am335x_evm with split config. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-03-02sandbox: Tidy up I2C optionsSimon Glass
At present we enable the sandbox I2C driver for all builds. Add a separate Kconfig option to control this, so that it can be disabled in TPL, where it is not needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2023-03-02sandbox: Tidy up RTC optionsSimon Glass
At present we enable the sandbox RTC driver for all builds. Add a separate Kconfig option to control this, so that it can be disabled in TPL, where it is not needed. Signed-off-by: Simon Glass <sjg@chromium.org>
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