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2025-03-18Merge tag 'u-boot-ufs-next-20250318' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-ufs into next - initial cleanup and defines sync with Linux v6.12
2025-03-18ufs: core: sync ufshci.h with Linux v6.12Neil Armstrong
Sync ufshci.h with the version found in the Linux v6.12 version commit adc218676eef ("Linux 6.12"). It adds new defines, and moves defines to the same place as the Linux header. No functional changes intended. Acked-by: Neha Malcom Francis <n-francis@ti.com> Tested-by: Love Kumar <love.kumar@amd.com> [narmstrong: do not rename CFG_RESULT_CODE_MASK] Link: https://lore.kernel.org/r/20241230-topic-ufs-cleanup-v2-6-4c6d7994a45d@linaro.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-03-18ufs: core: sync unipro.h with Linux v6.12Neil Armstrong
Sync unipro.h with the version found in the Linux v6.12 version commit adc218676eef ("Linux 6.12"). It adds new defines, and moves defines to the same place as the Linux header. No functional changes intended. Acked-by: Neha Malcom Francis <n-francis@ti.com> Tested-by: Love Kumar <love.kumar@amd.com> Link: https://lore.kernel.org/r/20241230-topic-ufs-cleanup-v2-5-4c6d7994a45d@linaro.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-03-18ufs: core: move ufshci defines in a separate headerNeil Armstrong
Splitting the header will help synchronizing the defines again with Linux. Acked-by: Neha Malcom Francis <n-francis@ti.com> Tested-by: Love Kumar <love.kumar@amd.com> Link: https://lore.kernel.org/r/20241230-topic-ufs-cleanup-v2-4-4c6d7994a45d@linaro.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-03-18ufs: core: cosmetic fixupsNeil Armstrong
Fixes some alignment warnings, missing comments on write barrier, missing parenthesis around macro parameters and a comment typo. No functional changes intended. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Tested-by: Love Kumar <love.kumar@amd.com> Link: https://lore.kernel.org/r/20241230-topic-ufs-cleanup-v2-3-4c6d7994a45d@linaro.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-03-18ufs: core: mark unexported functions as staticNeil Armstrong
Mark the remaining local functions as static to avoid build warnings. Also drop the EXPORT_SYMBOL of ufshcd_map_desc_id_to_length. Tested-by: Love Kumar <love.kumar@amd.com> Link: https://lore.kernel.org/r/20241230-topic-ufs-cleanup-v2-2-4c6d7994a45d@linaro.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-03-18ufs: core: include missing include/ufs.hNeil Armstrong
Add missing ufs.h causing build warning on some symbols. Tested-by: Love Kumar <love.kumar@amd.com> Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Link: https://lore.kernel.org/r/20241230-topic-ufs-cleanup-v2-1-4c6d7994a45d@linaro.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-03-18serial: Add missing TPL_SYS_NS16550_SERIAL symbolTom Rini
On PowerPC platforms with TPL enabled and SPL_SYS_NS16550_SERIAL enabled, today this builds under TPL as well due to how $(XPL_) is defined. Add the TPL_SYS_NS16550_SERIAL itself for consistency and clarity. Signed-off-by: Tom Rini <trini@konsulko.com>
2025-03-17Merge branch 'next' of git://source.denx.de/u-boot-usb into nextTom Rini
- Add USB support on Starfive JH7110
2025-03-17Merge branch 'nand-next' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-nand-flash into next CI: https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/pipelines/25178 This merge request add support for cadence raw nand driver for agilex board and add a fix to meson driver.
2025-03-17usb: cdns: starfive: Add cdns USB driverMinda Chen
Add Starfive cdns USB3 wrapper driver. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Marek Vasut <marex@denx.de> Tested-by: E Shattow <lucent@gmail.com>
2025-03-17usb: cdns: starfive: Get dr mode from wrapper device dts nodeMinda Chen
Cdns core driver also get dr mode from wrapper devcie dts node to make it is same with Starfive cdns USB Linux kernel driver, Starfive 7110 OF_UPSTREAM is enabled Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Marek Vasut <marex@denx.de>
2025-03-17phy: starfive: Add Starfive JH7110 PCIe 2.0 PHY driverMinda Chen
Add Starfive JH7110 PCIe 2.0 PHY driver, which is generic PHY driver and can be used as USB 3.0 driver. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Tested-by: E Shattow <lucent@gmail.com>
2025-03-17phy: starfive: Add Starfive JH7110 USB 2.0 PHY driverMinda Chen
Add Starfive JH7110 USB 2.0 PHY driver, which is generic PHY driver. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Tested-by: E Shattow <lucent@gmail.com>
2025-03-17usb: cdns3: Set USB PHY mode in cdns3_drd_update_mode()Minda Chen
USB PHY maybe need to set PHY mode in different USB dr mode. So translate USB PHY mode to generic PHY mode and call generic_phy_set_mode(). Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Marek Vasut <marex@denx.de>
2025-03-16mtd: rawnand: meson: always use OOB bytes during writeArseniy Krasnov
If 'oob_required' is not set by the caller (for example 'oobbuf' is NULL), then driver doesn't copy OOB data from 'oob_poi' to special controller structures, so zeroes will be written as OOB. But, generic raw NAND logic in 'nand_base.c' already handles case when OOB is not required to write by filling 'oob_poi' with 0xFF's. So let's remove 'oob_required' check to always read 'oob_poi' data for OOB. Kernel driver (drivers/mtd/nand/raw/meson_nand.c) works in the same way, so need to keep same behaviour here. Fixes: c2e8c4d09a7a ("mtd: rawnand: Meson NAND controller support") Signed-off-by: Arseniy Krasnov <avkrasnov@salutedevices.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-03-15drivers: mtd: nand: Kconfig: Add SYS_NAND_PAGE_SIZE dependencyDinesh Maniyam
Add SYS_NAND_PAGE_SIZE dependency for cadence NAND. This config is needed as the SPL driver will use this parameter to read uboot-proper image in NAND during booting. Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
2025-03-15drivers: mtd: nand: Enabled Kconfig and Makefile for Cadence-SPLDinesh Maniyam
Enable the Kconfig and Makefile for the Cadence-Nand SPL support in agilex5 family device. Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
2025-03-15drivers: mtd: nand: spl: Add support for nand SPL load imageDinesh Maniyam
Add support for spl nand to load binary image from NAND to RAM. Leverage the existing nand_spl_load_image from nand_spl_loaders.c Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
2025-03-15drivers: mtd: nand: base: Add support for Hardware ECC for check bad blockDinesh Maniyam
Leverage linux code to support hardware ECC interface to verify nand bad block. Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
2025-03-15drivers: nand: Enabled Kconfig and Makefile for cdns-nandDinesh Maniyam
Enable the Kconfig and Makefile for the Cadence NAND driver for the agilex5 family device. Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
2025-03-15drivers: mtd: nand: cadence: Use bounce bufferDinesh Maniyam
Enable nand to use bounce buffer. In bounce buffer, read/write buf will use cadence->buf which has been allocated using malloc. This will align the memory and avoid memory to be allocated in different addresses. Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
2025-03-15drivers: mtd: nand: cadence: Poll for desc complete statusDinesh Maniyam
Poll for thread complete status to ensure the descriptor processing is complete. If complete then can ensure controller already update the descriptor status. Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
2025-03-15drivers: mtd: nand: cadence: Flush & invalidate dma descriptorDinesh Maniyam
Ensure ddr memory is updated with the data from dcache. This would help to ensure cdma always reading the latest dma descriptor from ddr memory. Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
2025-03-15drivers: mtd: nand: cadence: Support cmd SET_FEATURES & GET_FEATURESDinesh Maniyam
Support NAND_CMD_SET_FEATURES & NAND_CMD_GET_FEATURES. These commands is one of the basic commands of NAND. The parameters get from these commands will be used to set timing mode of NAND data interface. Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
2025-03-15drivers: mtd: nand: cadence: Add support for NAND_CMD_RESETDinesh Maniyam
Support nand reset command for Cadence Nand Driver. Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
2025-03-15drivers: mtd: nand: cadence: Add support for NAND_CMD_PARAMDinesh Maniyam
Add support for reading param page of NAND device. These paramaters are unique and used for identification purpose. Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
2025-03-15drivers: mtd: nand: cadence: Add support for readid commandDinesh Maniyam
Add support for readid command in Cadence NAND driver. The id is unique and used for flash identification. Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
2025-03-15drivers: mtd: nand: cadence: Add support for read status commandDinesh Maniyam
Add support for read status command in Cadence NAND driver. This status bit is important to check whether the flash is write-protected. Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
2025-03-15drivers: mtd: nand: Add driver for Cadence NandDinesh Maniyam
Enable driver for Cadence NAND for the family device agilex5. This driver is leveraged from the path /drivers/mtd/nand/raw/cadence-nand-controller.c from the stable version 6.11.2. Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
2025-03-14common: console: Delete obsolete VIDCONSOLE_AS_{LCD, NAME} optionsDragan Simic
The configuration options CONFIG_VIDCONSOLE_AS_LCD and CONFIG_VIDCONSOLE_AS_ NAME have been marked as obsolete and scheduled for deletion in late 2020. That's already long overdue and the last remaining consumers of these options have already migrated to using "vidconsole" in their "stdout" and "stderr" environment variables, so let's delete these two configuration options. Signed-off-by: Dragan Simic <dsimic@manjaro.org> Acked-by: Soeren Moch <smoch@web.de> # tbs2910
2025-03-13Merge tag 'u-boot-imx-next-20250313' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/25142 - Support Toradex i.MX6 Apalis/Colibri v1.2 SoM. - Guard tee.bin inclusion on imx9, - Remove unneeded regulator entry on DH i.MX6 DHCOM DRC02 devicetree. - Add i.MX mailbox driver - Convert ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE to Kconfig. - Cope with existing optee node on imx8m.
2025-03-13memory: ti-gpmc: Alloc per driver private structVignesh Raghavendra
Driver uses dev_get_priv() but never allocates it in its declaration leading to various crashes. Fix this by explicitly allocating the storage. Fixes: 9b0b5648d6e4 ("memory: Add TI GPMC driver") Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-03-13mailbox: add i.MX Messaging Unit (MU) driverPeng Fan
This patch provides a driver for i.MX Messaging Unit (MU) using the commom mailbox framework. This is ported from Linux (v6.12.8) driver drivers/mailbox/imx-mailbox.c. Its commit SHA is: 39d7d6177f0c ("mailbox: imx: use device name in interrupt name") Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Alice Guo <alice.guo@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2025-03-13mmc: fsl_esdhc: Migrate ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE to KconfigTom Rini
The flag for enabling the ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE quirk can be handled easily enough in Kconfig. This lets us remove a function but not obviously correct usage of the IS_ENABLED() macro. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-03-12Merge tag 'u-boot-stm32-20250312' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-stm into next CI: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/25112 - Add drivers for MFD STM32 TIMERS and STM32 PWM and enable them on stm32mp135f-dk - Restrict _debug_uart_init() usage in STM32 serial driver - Add support for environment in eMMC on STM32MP13xx DHCOR SoM - Introduce DH STM32MP15xx DHSOM board specific defconfigs - Fix CONFIG_BOOTCOUNT_ALTBOOTCMD update on DH STM32MP1 DHSOM - Update maintainer for board stm32f746-disco - Fix Linux cmdline for stm32f769-disco - Cleanup in stm32f***-u-boot.dtsi and in board_late_init() by removing legacy led and button management.
2025-03-12Merge patch series "drivers: Driver support for ADI SC5xx SoCs"Tom Rini
Greg Malysa <malysagreg@gmail.com> says: This series adds all of the supported peripheral drivers for the sc5xx series of SoCs from Analog Devices and other drivers that are used by the evaluation kits, such as a GPIO expander used by the EZLITE carrier boards. This series passes gitlab CI tests. Link: https://lore.kernel.org/r/20250226173150.13198-1-malysagreg@gmail.com
2025-03-12mmc: Add support for ADI SC5XX-family processor SDHCI peripheralsNathan Barrett-Morrison
Co-developed-by: Greg Malysa <malysagreg@gmail.com> Signed-off-by: Greg Malysa <malysagreg@gmail.com> Co-developed-by: Ian Roberts <ian.roberts@timesys.com> Signed-off-by: Ian Roberts <ian.roberts@timesys.com> Signed-off-by: Vasileios Bimpikas <vasileios.bimpikas@analog.com> Signed-off-by: Utsav Agarwal <utsav.agarwal@analog.com> Signed-off-by: Arturs Artamonovs <arturs.artamonovs@analog.com> Signed-off-by: Oliver Gaskell <Oliver.Gaskell@analog.com> Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
2025-03-12spi: Add support for ADI SC5XX-family processor SPI peripheralsNathan Barrett-Morrison
This adds support for the ADI-specific SPI driver present in the ADI SC5xx line of SoCs. This IP block is distinct from the QSPI/OSPI block that uses the Cadence driver. Both may be used at once with appropriate pin muxing configuration. Co-developed-by: Greg Malysa <malysagreg@gmail.com> Signed-off-by: Greg Malysa <malysagreg@gmail.com> Co-developed-by: Angelo Dureghello <angelo.dureghello@timesys.com> Signed-off-by: Angelo Dureghello <angelo.dureghello@timesys.com> Co-developed-by: Ian Roberts <ian.roberts@timesys.com> Signed-off-by: Ian Roberts <ian.roberts@timesys.com> Co-developed-by: Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com> Signed-off-by: Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com> Signed-off-by: Vasileios Bimpikas <vasileios.bimpikas@analog.com> Signed-off-by: Utsav Agarwal <utsav.agarwal@analog.com> Signed-off-by: Arturs Artamonovs <arturs.artamonovs@analog.com> Signed-off-by: Oliver Gaskell <Oliver.Gaskell@analog.com> Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
2025-03-12remoteproc: Add in SHARC loading for ADI SC5XX-family processorsNathan Barrett-Morrison
This adds the ability to load ldr-formatted files to the SHARC coprocessors using the rproc interface. Only a minimal subset of rproc functionality is supported: loading and starting the remote core. Secure boot and signed ldr verification are not available at this time through the U-Boot interface. Co-developed-by: Greg Malysa <malysagreg@gmail.com> Signed-off-by: Greg Malysa <malysagreg@gmail.com> Co-developed-by: Ian Roberts <ian.roberts@timesys.com> Signed-off-by: Ian Roberts <ian.roberts@timesys.com> Co-developed-by: Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com> Signed-off-by: Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com> Signed-off-by: Vasileios Bimpikas <vasileios.bimpikas@analog.com> Signed-off-by: Utsav Agarwal <utsav.agarwal@analog.com> Signed-off-by: Arturs Artamonovs <arturs.artamonovs@analog.com> Signed-off-by: Oliver Gaskell <Oliver.Gaskell@analog.com> Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
2025-03-12dma: Add driver for ADI SC5xx-family SoC MDMA functionalityGreg Malysa
Add a rudimentary MDMA driver for the Analog Devices SC5xx SoCs, primarily intended for use with and tested against the QSPI/OSPI IP included in the SoC. Co-developed-by: Ian Roberts <ian.roberts@timesys.com> Signed-off-by: Ian Roberts <ian.roberts@timesys.com> Co-developed-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com> Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com> Signed-off-by: Vasileios Bimpikas <vasileios.bimpikas@analog.com> Signed-off-by: Utsav Agarwal <utsav.agarwal@analog.com> Signed-off-by: Arturs Artamonovs <arturs.artamonovs@analog.com> Signed-off-by: Greg Malysa <malysagreg@gmail.com> Signed-off-by: Oliver Gaskell <Oliver.Gaskell@analog.com>
2025-03-12watchdog: Add support for ADI SC5XX-family watchdog peripheralNathan Barrett-Morrison
Co-developed-by: Greg Malysa <malysagreg@gmail.com> Signed-off-by: Greg Malysa <malysagreg@gmail.com> Co-developed-by: Ian Roberts <ian.roberts@timesys.com> Signed-off-by: Ian Roberts <ian.roberts@timesys.com> Signed-off-by: Vasileios Bimpikas <vasileios.bimpikas@analog.com> Signed-off-by: Utsav Agarwal <utsav.agarwal@analog.com> Signed-off-by: Arturs Artamonovs <arturs.artamonovs@analog.com> Signed-off-by: Oliver Gaskell <Oliver.Gaskell@analog.com> Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com> Reviewed-by: Stefan Roese <sr@denx.de>
2025-03-12net: Add support for ADI SC5xx SoCs with DWC QoS ethernetGreg Malysa
The ADI SC598 includes a Designware QoS 5.20a IP block. This commit adds support for using the existing ethernet QoS driver with the SC598 SoC. Co-developed-by: Ian Roberts <ian.roberts@timesys.com> Signed-off-by: Ian Roberts <ian.roberts@timesys.com> Co-developed-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com> Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com> Signed-off-by: Vasileios Bimpikas <vasileios.bimpikas@analog.com> Signed-off-by: Utsav Agarwal <utsav.agarwal@analog.com> Signed-off-by: Arturs Artamonovs <arturs.artamonovs@analog.com> Signed-off-by: Oliver Gaskell <Oliver.Gaskell@analog.com> Signed-off-by: Greg Malysa <malysagreg@gmail.com>
2025-03-12i2c: Add support for ADI SC5XX-family I2C peripheralNathan Barrett-Morrison
Co-developed-by: Greg Malysa <malysagreg@gmail.com> Signed-off-by: Greg Malysa <malysagreg@gmail.com> Co-developed-by: Ian Roberts <ian.roberts@timesys.com> Signed-off-by: Ian Roberts <ian.roberts@timesys.com> Co-developed-by: Angelo Dureghello <angelo.dureghello@timesys.com> Signed-off-by: Angelo Dureghello <angelo.dureghello@timesys.com> Signed-off-by: Vasileios Bimpikas <vasileios.bimpikas@analog.com> Signed-off-by: Utsav Agarwal <utsav.agarwal@analog.com> Signed-off-by: Arturs Artamonovs <arturs.artamonovs@analog.com> Signed-off-by: Oliver Gaskell <Oliver.Gaskell@analog.com> Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2025-03-12usb: musb-new: Add support for Analog Devices SC5xx SoCsNathan Barrett-Morrison
This adds support for the MUSB-based USB controller found in the Analog Devices SC57x and SC58x SoCs. Co-developed-by: Greg Malysa <malysagreg@gmail.com> Signed-off-by: Greg Malysa <malysagreg@gmail.com> Co-developed-by: Ian Roberts <ian.roberts@timesys.com> Signed-off-by: Ian Roberts <ian.roberts@timesys.com> Signed-off-by: Vasileios Bimpikas <vasileios.bimpikas@analog.com> Signed-off-by: Utsav Agarwal <utsav.agarwal@analog.com> Signed-off-by: Arturs Artamonovs <arturs.artamonovs@analog.com> Signed-off-by: Oliver Gaskell <Oliver.Gaskell@analog.com> Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
2025-03-12gpio: Add support for ADI ADP5588 GPIO expander chipsNathan Barrett-Morrison
This adds support for the ADP588 GPIO expander from Analog Devices. It is accessed over I2C and provides up to 18 pins. It is largely a port of the Linux driver developed by Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Ian Roberts <ian.roberts@timesys.com> Signed-off-by: Greg Malysa <malysagreg@gmail.com> Signed-off-by: Vasileios Bimpikas <vasileios.bimpikas@analog.com> Signed-off-by: Utsav Agarwal <utsav.agarwal@analog.com> Signed-off-by: Arturs Artamonovs <arturs.artamonovs@analog.com> Signed-off-by: Oliver Gaskell <Oliver.Gaskell@analog.com> Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
2025-03-12gpio: Add support for SC5XX-family processor GPIO driverGreg Malysa
This adds support for using the GPIO pins on the SC5XX family of SoCs from Analog Devices. Co-developed-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com> Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com> Co-developed-by: Ian Roberts <ian.roberts@timesys.com> Signed-off-by: Ian Roberts <ian.roberts@timesys.com> Signed-off-by: Vasileios Bimpikas <vasileios.bimpikas@analog.com> Signed-off-by: Utsav Agarwal <utsav.agarwal@analog.com> Signed-off-by: Arturs Artamonovs <arturs.artamonovs@analog.com> Signed-off-by: Oliver Gaskell <Oliver.Gaskell@analog.com> Signed-off-by: Greg Malysa <malysagreg@gmail.com>
2025-03-12pinctrl: Add support for ADI SC5XX-family pinctrlGreg Malysa
This adds support for pin configuration on the Analog Devices SC5XX SoC family. This commit is largely a port of the Linux driver, which has not yet been submitted upstream. Co-developed-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com> Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com> Co-developed-by: Ian Roberts <ian.roberts@timesys.com> Signed-off-by: Ian Roberts <ian.roberts@timesys.com> Signed-off-by: Vasileios Bimpikas <vasileios.bimpikas@analog.com> Signed-off-by: Utsav Agarwal <utsav.agarwal@analog.com> Signed-off-by: Arturs Artamonovs <arturs.artamonovs@analog.com> Signed-off-by: Oliver Gaskell <Oliver.Gaskell@analog.com> Signed-off-by: Greg Malysa <malysagreg@gmail.com>
2025-03-12Merge patch series "pci_auto: Downgrade prefetch if necessary"Tom Rini
This series from Patrick Rudolph <patrick.rudolph@9elements.com> fixes an issue with how we treat PCIe vs PCI in some cases and fixes the qemu-arm-sbsa reference platform support. Link: https://lore.kernel.org/r/20250226135647.194842-1-patrick.rudolph@9elements.com
2025-03-12pci_auto: Downgrade prefetch if necessaryPatrick Rudolph
Legacy PCI devices, like qemu's Bochs VGA device, are allowed to have prefetchable 32-bit BARs, while PCIe devices are not allowed to have 32-bit prefetchable BARs. Typically prefetchable BARs are 64-bit and typically the prefetch MMIO window is also 64-bit and placed above 4GiB, as it's the case on qemu sbsa-ref. Currently the U-Boot code assumes that prefetchable BARs are 64-bit BARs and always tries to assign them into the prefetch MMIO window. When a 32-bit BAR is marked as prefetch, but the prefetch area is not within the first 4GiB of the address space, then downgrade the BAR and place it in the non-prefetch MMIO window. For prefetch BARs there's no downside on being placed in non prefetch MMIO areas, besides the possible slower performance when a driver tries to map it Write-Combine. TEST: Fixes pci_auto on QEMU sbsa-ref fails to autoconfigure BAR0. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
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