summaryrefslogtreecommitdiff
path: root/drivers
AgeCommit message (Collapse)Author
2021-04-29phy: marvell: save comphy_map_data priv structureIgal Liberman
This allows the lower level driver access to comphy map data (required for RX training support, which is introduced in the following patches). Change-Id: Ib7ffdc4b32076c01c3a5d33f59552c9dfc6b12fa Signed-off-by: Igal Liberman <igall@marvell.com>
2021-04-29phy: marvell: fix several minor bugs in comphy_probeIgal Liberman
If fdtdec_get_int can't find speed, set COMPHY_SPEED_INVALID If fdtdec_get_int can't find type, set COMPHY_TYPE_INVALID Move the error print if phy-type is invalid Add continue to the probe loop (in a case of invalid phy) Cosmetic changes Change-Id: I0c61b40bfe685437426fe907942ed338b7845378 Signed-off-by: Igal Liberman <igall@marvell.com>
2021-04-29phy: marvell: cp110: utmi: update analog parameters according to latest ETPIgal Liberman
Add UTMI analog parameters initialization values according to latest ETP. Change-Id: I5bcca205a3995202a18ff126f371a81f69e205c8 Signed-off-by: Igal Liberman <igall@marvell.com>
2021-04-29phy: marvell: cp110: initialize only enabled UTMI unitsOmri Itach
UTMI should be initialized only for enabled device tree nodes. This fix overrides current internal configuration array entry with the next DT entry data if error is detected during the current DT entry parsing or the current port is disabled. This way the internal configuration structure will only contain valid ports information obtained from the DT. Change-Id: I9c43c6a5d234e15ae9005d1c9bc983fc1f3544b8 Signed-off-by: Omri Itach <omrii@marvell.com> Signed-off-by: Ken Ma <make@marvell.com>
2021-04-29phy: marvell: add missing speed during info printsIgal Liberman
In get_speed_string() we have an array (speed_strings[]) which includes all possible speed strings. This array size and content must be aligned to the speed defines in comphy_data.h. This patch adds missing 5.125G speed, aligns speed_strings[] and fixes incorrect printing when speed > 5.0G. Change-Id: I9900d23595094be321be0c62fcaa88036324568e Signed-off-by: Igal Liberman <igall@marvell.com>
2021-04-29phy: marvell: rename comphy related definitions to COMPHY_XXIgal Liberman
Currently, all comphy definitions are PHY_TYPE_XX and PHY_SPEEED_XX. Those definition might be confused with MDIO PHY definitions. This patch does the following changes: - PHY_TYPE_XX --> COMPHY_TYPE_XX - PHY_SPEED_XX --> COMPHY_SPEED_XX This improves readability, no functional change. Change-Id: I2bd1d9289ebbc5c16fa80f9870f797ea1bcaf5fa Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2021-04-29phy: marvell: add comphy type PHY_TYPE_USB3jinghua
- For some Marvell SoCs, like armada-3700, there are both USB host and device controller, but on PHY level the configuration is the same. - The new type supports both USB device and USB host - This patch is cherry-picked from u-boot-2015 as-is. Change-Id: I01262027edd8ec23391cff6fb409b3009aedfbb9 Signed-off-by: jinghua <jinghua@marvell.com> Signed-off-by: Ken Ma <make@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2021-04-29power: regulator: Add support for regulator-force-boot-offKonstantin Porotchkin
Add support for regulator-force-boot-off DT property. This property can be used by the board/device drivers for turning off regulators on early init stages as pre-requisite for the other components initialization. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-04-28Merge https://source.denx.de/u-boot/custodians/u-boot-usbTom Rini
2021-04-28net: designware: fix PHY reset with DM_MDIONeil Armstrong
The dw_eth_pdata is not accessible from the mdio device, it gets the mdio bus plat leading to random sleeps (-10174464 on Odroid-HC4). This moves the dw_mdio_reset function to a common one taking the ethernet device as parameter and use it from the dw_mdio_reset and dm_mdio variant functions. Fixes: 5160b4567c ("net: designware: add DM_MDIO support") Reported-by: Mark Kettenis <mark.kettenis@xs4all.nl> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-04-28usb: ehci-mx6: Limit PHY address parsing to !CONFIG_PHYMarek Vasut
For systems which use generic PHY support and implement USB PHY driver, the parsing of PHY properties is unnecessary, disable it. Signed-off-by: Marek Vasut <marex@denx.de> Tested-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
2021-04-28mtd: cfi: Fix PPB lock status readoutMarek Vasut
According to S26KL512S datasheet [1] and S29GL01GS datasheet [2], the procedure to read out PPB lock bits is to send the PPB Entry, PPB Read, Reset/ASO Exit. Currently, the code does send incorrect PPB Entry, PPB Read and Reset/ASO Exit is completely missing. The PPB Entry sent is implemented by sending flash_unlock_seq() and flash_write_cmd(..., FLASH_CMD_READ_ID). This translates to sequence 0x555:0xaa, 0x2aa:0x55, 0x555:0x90=FLASH_CMD_READ_ID. However, both [1] and [2] specify the last byte of PPB Entry as 0xc0=AMD_CMD_SET_PPB_ENTRY instead of 0x90=FLASH_CMD_READ_ID, that is 0x555:0xaa, 0x2aa:0x55, 0x555:0xc0=AMD_CMD_SET_PPB_ENTRY. Since this does make sense, this patch fixes it and thus also aligns the code in flash_get_size() with flash_real_protect(). The PPB Read returns 00h in case of Protected state and 01h in case of Unprotected state, according to [1] Note 83 and [2] Note 17, so invert the result. Moreover, align the arguments with similar code in flash_real_protect(). Finally, Reset/ASO Exit command should be executed to exit the PPB mode, so add the missing reset. [1] https://www.cypress.com/file/213346/download Document Number: 001-99198 Rev. *M Table 40. Command Definitions, Nonvolatile Sector Protection Command Set Definitions [2] https://www.cypress.com/file/177976/download Document Number: 001-98285 Rev. *R Table 7.1 Command Definitions, Nonvolatile Sector Protection Command Set Definitions Fixes: 03deff433e ("cfi_flash: Read PPB sector protection from device for AMD/Spansion chips") Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Stefan Roese <sr@denx.de> Reviewed-by: Stefan Roese <sr@denx.de>
2021-04-28reset: fix reset_get_by_index_nodev index handlingNeil Armstrong
This fixes an issue getting resets index 1 and 3+, the spurius "> 0" made it return the index 0 or 1, whatever index was passed. The dm_test_reset_base() did not catch it, but the dm_test_reset_base() extension catches it and this fixes the regression. This also fixes a reggression on Amlogic G12A/G12B SoCs, where HDMI output was disable even when Linux was booting. Fixes: ea9dc35aab ("reset: Get the RESET by index without device") Reported-by: B1oHazard <ty3uk@mail.ua> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-04-28pinctrl: single: fix a never true comparisonDario Binacchi
As reported by Coverity Scan for Das U-Boot, the 'less-than-zero' comparison of an unsigned value is never true. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
2021-04-28pinctrl: single: check function mask to be non-zeroDario Binacchi
Otherwise it can generate a division by zero, which has an undefined behavior. Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-04-28allow opting out of WATCHDOG_RESET() from timer interruptRasmus Villemoes
Having WATCHDOG_RESET() called automatically from the timer interrupt runs counter to the idea of a watchdog device - if the board runs into an infinite loops with interrupts still enabled, the watchdog will never fire. When using CONFIG_(SPL_)WDT, the watchdog_reset function is a lot more complicated than just poking a few SOC-specific registers - it involves accessing all kinds of global data, and if the interrupt happens at the wrong time (say, in the middle of an WATCHDOG_RESET() call from ordinary code), that can end up corrupting said global data. Allow the board to opt out of calling WATCHDOG_RESET() from the timer interrupt handler by setting CONFIG_SYS_WATCHDOG_FREQ to 0 - as that setting is currently nonsensical (it would be compile-time divide-by-zero), it cannot affect any existing boards. Add documentation for both the existing and extended meaning of CONFIG_SYS_WATCHDOG_FREQ. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2021-04-28timer: mpc83xx_timer: fix build with CONFIG_{HW_, }WATCHDOGRasmus Villemoes
The code, which is likely copied from arch/powerpc/lib/interrupts.c, lacks a fallback definition of CONFIG_SYS_WATCHDOG_FREQ and refers to a non-existing timestamp variable - obviously priv->timestamp is meant. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2021-04-28watchdog: use time_after_eq() in watchdog_reset()Rasmus Villemoes
Some boards don't work with the rate-limiting done in the generic watchdog_reset() provided by wdt-uclass. For example, on powerpc, get_timer() ceases working during bootm since interrupts are disabled before the kernel image gets decompressed, and when the decompression takes longer than the watchdog device allows (or enough of the budget that the kernel doesn't get far enough to assume responsibility for petting the watchdog), the result is a non-booting board. As a somewhat hacky workaround (because DT is supposed to describe hardware), allow specifying hw_margin_ms=0 in device tree to effectively disable the ratelimiting and actually ping the watchdog every time watchdog_reset() is called. For that to work, the "has enough time passed" check just needs to be tweaked a little to allow the now==next_reset case as well. Suggested-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Stefan Roese <sr@denx.de>
2021-04-28clk: renesas: Synchronize Gen2 MSTP teardown tablesMarek Vasut
Synchronize Gen2 MSTP teardown tables with datasheet Rev.2.00 Feb 01, 2016. This corrects the following bits: - added H2 MSTP3[10] SCIF2 - added H2/M2/E2 MSTP7[29] TCON - removed E2 MSTP5[22] Thermal Sensor - removed E2 MSTP10[31,24:22] SRC0, SRC7:9 Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2021-04-28clk: renesas: Only ever access documented bits in clock driver teardownMarek Vasut
The clock driver used a heavy-handed approach where it turned off all available clocks, while also possibly setting bits which are not documented in the R-Car datasheet. Update the tables so that only the bits which are documented are set or cleared when tearing down the clock driver. Note that the only clock left running before booting Linux are now MFIC, INTC-AP, INTC-EX and SCIF2 / SCIF0 on V3x. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
2021-04-28net: sun8i-emac: Fix pinmux setup for Allwinner H5Andre Przywara
Commit eb5a2b671075 ("net: sun8i-emac: Determine pinmux based on SoC, not EMAC type") switched the pinmux setup over to look at CONFIG_MACH_SUN* symbols, to find the appropriate mux value. Unfortunately this patch missed to check for the H5, which is pin-compatible to the H3, but uses a different Kconfig symbol (because it has ARMv8 vs. ARMv7 cores). Replace the pure SUN8I_H3 symbol with the joint SUNXI_H3_H5 one, which is there to cover the peripherals common to both SoCs. Also explicitly list each supported SoC, and have an error message in the fallback case, to avoid those problems in the future. This fixes Ethernet support on all H5 boards. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Samuel Holland <samuel@sholland.org> # Orange Pi PC2 Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-04-28scsi: Add ata_swap_buf_le16() to support big-endian platformsStefan Roese
Otherwise the output will look like this on MIPS Octeon NIC23: Device 0: (0:0) Vendor: ATA Prod.: aSDnsi klUrt aII Rev: 4X11 Type: Hard Disk Capacity: 457862.8 MB = 447.1 GB (937703088 x 512) instead of this version: Device 0: (0:0) Vendor: TA Prod.: SanDisk Ultra II Rev: X411 Type: Hard Disk Capacity: 457862.8 MB = 447.1 GB (937703088 x 512) Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-28ata: ahci: Fix usage on big-endian platformsStefan Roese
This patch adds a few missing virt_to_phys() to use the correct physical address for DMA operations in the common AHCI code. This is done to support the big-endian MIPS Octeon platform. Additionally the code a cleaned up a bit (remove some empty lines) and made a bit better readable. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-28sata: ahci_mvebu.c: Enable AHCI/SATA driver for MIPS OcteonStefan Roese
This patch enables the usage of the MVEBU AHCI/SATA driver. The only changes necessary to support MIPS Octeon via DT based probing are, to add the compatible DT property and the use of dev_remap_addr() so that the correct mapped address is used in the Octeon case (phys != virt). Please note that this driver supports the usage of the "scsi" command and not the "sata" command, since it does not provide an own "scan" function, which is needed for the "sata" cmd support. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-28serial: serial_octeon_bootcmd.c: Add PCI remote console supportStefan Roese
This patch adds the PCI bootcmd feature for MIPS Octeon, which will be used by the upcoming Octeon III NIC23 board support. It enables the use of the "oct-remote-load" and "oct-remote-bootcmd" on host PC's to communicate with the PCIe target and load images into the onboard memory and issue commands. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-28serial: serial_octeon_pcie_console.c: Add PCI remote console supportStefan Roese
This patch adds the PCI remote console feature for MIPS Octeon, which will be used by the upcoming Octeon III NIC23 board support. It enables the use of the "oct-remote-console" tool on host PC's to communicate with the PCIe target. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-28mips: octeon: Add Octeon PCIe host controller driverStefan Roese
This patch adds the PCIe host controller driver for MIPS Octeon II/III. The driver mainly consist of the PCI config functions, as all of the complex serdes related port / lane setup, is done in the serdes / pcie code available in the "arch/mips/mach-octeon" directory. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-28mips: octeon: Misc changes required because of the newly added headersStefan Roese
With the newly added headers and their restructuring (which macro is defined where), some changes in the already existing Octeon files are necessary. This patch makes the necessary changes. Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-27Merge branch '2021-04-27-assorted-fixes'Tom Rini
- An assortment of bug fixes
2021-04-27reset: fix reset_get_by_index_nodev index handlingNeil Armstrong
This fixes an issue getting resets index 1 and 3+, the spurius "> 0" made it return the index 0 or 1, whatever index was passed. The dm_test_reset_base() did not catch it, but the dm_test_reset_base() extension catches it and this fixes the regression. This also fixes a reggression on Amlogic G12A/G12B SoCs, where HDMI output was disable even when Linux was booting. Fixes: ea9dc35aab ("reset: Get the RESET by index without device") Reported-by: B1oHazard <ty3uk@mail.ua> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-04-27pinctrl: single: fix a never true comparisonDario Binacchi
As reported by Coverity Scan for Das U-Boot, the 'less-than-zero' comparison of an unsigned value is never true. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
2021-04-27pinctrl: single: check function mask to be non-zeroDario Binacchi
Otherwise it can generate a division by zero, which has an undefined behavior. Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-04-27allow opting out of WATCHDOG_RESET() from timer interruptRasmus Villemoes
Having WATCHDOG_RESET() called automatically from the timer interrupt runs counter to the idea of a watchdog device - if the board runs into an infinite loops with interrupts still enabled, the watchdog will never fire. When using CONFIG_(SPL_)WDT, the watchdog_reset function is a lot more complicated than just poking a few SOC-specific registers - it involves accessing all kinds of global data, and if the interrupt happens at the wrong time (say, in the middle of an WATCHDOG_RESET() call from ordinary code), that can end up corrupting said global data. Allow the board to opt out of calling WATCHDOG_RESET() from the timer interrupt handler by setting CONFIG_SYS_WATCHDOG_FREQ to 0 - as that setting is currently nonsensical (it would be compile-time divide-by-zero), it cannot affect any existing boards. Add documentation for both the existing and extended meaning of CONFIG_SYS_WATCHDOG_FREQ. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2021-04-27timer: mpc83xx_timer: fix build with CONFIG_{HW_, }WATCHDOGRasmus Villemoes
The code, which is likely copied from arch/powerpc/lib/interrupts.c, lacks a fallback definition of CONFIG_SYS_WATCHDOG_FREQ and refers to a non-existing timestamp variable - obviously priv->timestamp is meant. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2021-04-27watchdog: use time_after_eq() in watchdog_reset()Rasmus Villemoes
Some boards don't work with the rate-limiting done in the generic watchdog_reset() provided by wdt-uclass. For example, on powerpc, get_timer() ceases working during bootm since interrupts are disabled before the kernel image gets decompressed, and when the decompression takes longer than the watchdog device allows (or enough of the budget that the kernel doesn't get far enough to assume responsibility for petting the watchdog), the result is a non-booting board. As a somewhat hacky workaround (because DT is supposed to describe hardware), allow specifying hw_margin_ms=0 in device tree to effectively disable the ratelimiting and actually ping the watchdog every time watchdog_reset() is called. For that to work, the "has enough time passed" check just needs to be tweaked a little to allow the now==next_reset case as well. Suggested-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Stefan Roese <sr@denx.de>
2021-04-26Merge https://source.denx.de/u-boot/custodians/u-boot-shTom Rini
- RCar3 improvements
2021-04-26net: sun8i-emac: Fix pinmux setup for Allwinner H5Andre Przywara
Commit eb5a2b671075 ("net: sun8i-emac: Determine pinmux based on SoC, not EMAC type") switched the pinmux setup over to look at CONFIG_MACH_SUN* symbols, to find the appropriate mux value. Unfortunately this patch missed to check for the H5, which is pin-compatible to the H3, but uses a different Kconfig symbol (because it has ARMv8 vs. ARMv7 cores). Replace the pure SUN8I_H3 symbol with the joint SUNXI_H3_H5 one, which is there to cover the peripherals common to both SoCs. Also explicitly list each supported SoC, and have an error message in the fallback case, to avoid those problems in the future. This fixes Ethernet support on all H5 boards. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Samuel Holland <samuel@sholland.org> # Orange Pi PC2 Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-04-25clk: renesas: Synchronize Gen2 MSTP teardown tablesMarek Vasut
Synchronize Gen2 MSTP teardown tables with datasheet Rev.2.00 Feb 01, 2016. This corrects the following bits: - added H2 MSTP3[10] SCIF2 - added H2/M2/E2 MSTP7[29] TCON - removed E2 MSTP5[22] Thermal Sensor - removed E2 MSTP10[31,24:22] SRC0, SRC7:9 Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2021-04-25clk: renesas: Only ever access documented bits in clock driver teardownMarek Vasut
The clock driver used a heavy-handed approach where it turned off all available clocks, while also possibly setting bits which are not documented in the R-Car datasheet. Update the tables so that only the bits which are documented are set or cleared when tearing down the clock driver. Note that the only clock left running before booting Linux are now MFIC, INTC-AP, INTC-EX and SCIF2 / SCIF0 on V3x. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
2021-04-24Merge tag 'mips-pull-2021-04-24' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-mips - MIPS: octeon: fix minor bugs of initial merge - MIPS: octeon: add support for QLM and PCI-E controller - MIPS: octeon: add support for AHCI and SATA - MIPS: octeon: add E1000 ethernet support - MIPS: octeon: add Octeon III NIC23 board - ata/scsi: add support for Big Endian platforms
2021-04-24video: sunxi: de2: switch to public uclass functionsJernej Skrabec
Currently DE2 driver uses functions which are defined in internal headers. They are not meant to be used outside of uclass framework. Switch DE2 driver to public ones. This has additional benefit that device_probe doesn't need to be called manually. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-04-24video: sunxi: dw-hdmi: read source_id laterJernej Skrabec
There is no real need to read source_id at probe time. It also doesn't make sense to store it in driver private data since it's already stored in class platform data. While this looks like cleanup (and it is), it's also important for DE2 driver rework because this info will be filled later (after probe is already executed). Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-04-24video: sunxi: Remove TV probe from DE2Jernej Skrabec
TV driver was never fully implemented. Remove search for it from DE2 driver. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-04-24video: sunxi: Remove check for ddc-i2c-bus propertyJernej Skrabec
No Allwinner board with DW-HDMI controller use separate I2C bus for EDID read. Remove that check. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-04-24video: sunxi: Use DW-HDMI hpd functionJernej Skrabec
It turns out that there are two ways how hot plug detection can be done. One is standard way for DW HDMI controller - checking bit 2 in 0x3004 register. Another way is applicable only to Allwinner custom PHY - by checking bit 19 in register 0x10038. Both methods are equally good as far as we know. Use standard method in order to reduce amount of custom code. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-04-24video: sunxi: Add mode_valid callback to sunxi_dw_hdmiJernej Skrabec
Currently driver accepts all resolution which won't work on 4k screens. Add validation callback which limits acceptable resolutions to 297 MHz. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-04-23scsi: Add ata_swap_buf_le16() to support big-endian platformsStefan Roese
Otherwise the output will look like this on MIPS Octeon NIC23: Device 0: (0:0) Vendor: ATA Prod.: aSDnsi klUrt aII Rev: 4X11 Type: Hard Disk Capacity: 457862.8 MB = 447.1 GB (937703088 x 512) instead of this version: Device 0: (0:0) Vendor: TA Prod.: SanDisk Ultra II Rev: X411 Type: Hard Disk Capacity: 457862.8 MB = 447.1 GB (937703088 x 512) Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-23ata: ahci: Fix usage on big-endian platformsStefan Roese
This patch adds a few missing virt_to_phys() to use the correct physical address for DMA operations in the common AHCI code. This is done to support the big-endian MIPS Octeon platform. Additionally the code a cleaned up a bit (remove some empty lines) and made a bit better readable. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-23sata: ahci_mvebu.c: Enable AHCI/SATA driver for MIPS OcteonStefan Roese
This patch enables the usage of the MVEBU AHCI/SATA driver. The only changes necessary to support MIPS Octeon via DT based probing are, to add the compatible DT property and the use of dev_remap_addr() so that the correct mapped address is used in the Octeon case (phys != virt). Please note that this driver supports the usage of the "scsi" command and not the "sata" command, since it does not provide an own "scan" function, which is needed for the "sata" cmd support. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-23serial: serial_octeon_bootcmd.c: Add PCI remote console supportStefan Roese
This patch adds the PCI bootcmd feature for MIPS Octeon, which will be used by the upcoming Octeon III NIC23 board support. It enables the use of the "oct-remote-load" and "oct-remote-bootcmd" on host PC's to communicate with the PCIe target and load images into the onboard memory and issue commands. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
generated by cgit v1.2.3 (git 2.0.4) at 2025-07-24 20:37:31 +0000