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2023-03-02usb: xhci-mtk: modify the SOF/ITP interval for mt8195Chunfeng Yun
There are 4 USB controllers on MT8195, the controllers (IP1~IP3, exclude IP0) have a wrong default SOF/ITP interval which is calculated from the frame counter clock 24Mhz by default, but in fact, the frame counter clock is 48Mhz, so we shall set the accurate interval according to 48Mhz for those controllers. Note: The first controller no need set it, but if set it, shall change tphy's pll at the same time. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Marek Vasut <marex@denx.de>
2023-03-02phy: phy-mtk-tphy: add support mt8195Chunfeng Yun
The T-PHY controller is designed to use use PLL integer mode, but in fact use fractional mode for some ones on mt8195 by mistake, this causes signal degradation (e.g. eye diagram test fail), fix it by switching PLL to 26Mhz from default 48Mhz to improve signal quality. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
2023-03-02phy: phy-mtk-tphy: remove macros to prepare bitfield valueChunfeng Yun
Prefer to make use of FIELD_PREP() macro to prepare bitfield value, then no need local macros anymore. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
2023-03-02usb: dwc3-meson-g12a: Select PHY instead of imply PHYMarek Vasut
Imply means you can turn off the option and expect things to work - "it's a good idea to have X enabled" is when to use imply - "you must have X for Y to work" is when to use select Use "select" here. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2023-03-01arm: mvebu: Add support for generating NAND kwbimagePali Rohár
Add a new Kconfig option CONFIG_MVEBU_SPL_BOOT_DEVICE_NAND which instruct make to generate kwbimage with NAND header. This image is used for booting from NAND flash (either SPI or parallel). Support is very simple, SPL after finishes DDR training returns back to the BootROM (via CONFIG_SPL_BOOTROM_SUPPORT option) and BootROM then loads and executes U-Boot proper. To generate correct kwbimage NAND header, it is required to set following Kconfig options: CONFIG_SYS_NAND_PAGE_SIZE CONFIG_SYS_NAND_BLOCK_SIZE CONFIG_MVEBU_SPL_NAND_BADBLK_LOCATION They are used only by make / mkimage when generating final kwbimage. CONFIG_MVEBU_SPL_NAND_BADBLK_LOCATION is a new mvebu specific Kconfig option which is set into kwbimage NAND_BADBLK_LOCATION header field. Signed-off-by: Pali Rohár <pali@kernel.org>
2023-02-28Merge tag 'tpm-next-28022023' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-tpm into next TPM auto startup and testing: Due to U-Boot's lazy binding we always relied on command line tools to initialize the TPM subsystem and devices. One exception is the EFI subsystem. When compiled with TCG2 measured boot support the TPM was automatically initialized. However that init was not complete. The TCG specs [0] (and specifically §12.3 Self-test modes) describe how self-tests on the device should be performed. This PR is adding an extra API function, that can be used to initialize the TPM2.0 properly. Simon added the equivalent for TPM1.2 and refactored the DM tests to include the new funtion. [0] https://trustedcomputinggroup.org/wp-content/uploads/TPM-Rev-2.0-Part-1-Architecture-01.07-2014-03-13.pdf
2023-02-28Merge tag 'u-boot-nand-20230227' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-nand-flash into next Pull request for u-boot-nand-20230227 - mark reserved blocks from Ashok Reddy Soma - backport BRCMNAND changes from Linux from Linus Walleij - fix display of unknown raw ID from Patrice Chotard - show reserved block in chip.erase from Michael Trimarchi
2023-02-28tpm: sandbox: Change the return code when device is already openIlias Apalodimas
All the TPM drivers as well as out TCG TIS API for a TPM2.0 device return -EBUSY if the device has already been opened. Adjust the sandbox TPM do return the same error code. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-02-27Merge tag 'v2023.04-rc3' into nextTom Rini
Prepare v2023.04-rc3
2023-02-27mtd: nand: Show reserved block in chip.eraseMichael Trimarchi
The "nand chip.erase" command always printed as bad blocks even in the case of reserved blocks. Reserved blocks are used for storing bad block tables. The patch displays "bbt reserved" when printing reserved blocks in "nand chip.erase" command. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: spinand: Fix display of unknown raw IDPatrice Chotard
In case ID is not found in manufacturer table, the raw ID is printed using %*phN format which is not supported by lib/vsprintf.c. The information displayed doesn't reflect the raw ID return by the unknown spi-nand. Use %02x format instead, as done in spi-nor-core.c. For example, before this patch: ERROR: spi-nand: spi_nand flash@0: unknown raw ID f74ec040 after ERROR: spi-nand: spi_nand flash@0: unknown raw ID 00 c2 26 03 Fixes: 0a6d6bae0386 ("mtd: nand: Add core infrastructure to support SPI NANDs") Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Acked-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: rawnand: brcmnand: fix OOB R/W with Hamming ECCÁlvaro Fernández Rojas
Hamming ECC doesn't cover the OOB data, so reading or writing OOB shall always be done without ECC enabled. This is a problem when adding JFFS2 cleanmarkers to erased blocks. If JFFS2 clenmarkers are added to the OOB with ECC enabled, OOB bytes will be changed from ff ff ff to 00 00 00, reporting incorrect ECC errors. Fixes: 27c5b17cd1b1 ("mtd: nand: add NAND driver "library" for Broadcom STB NAND controller") Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210224080210.23686-1-noltari@gmail.com [Ported to U-Boot from the Linux kernel] Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: rawnand: brcmnand: support v2.1-v2.2 controllersÁlvaro Fernández Rojas
v2.1: tested on Netgear DGND3700v1 (BCM6368) v2.2: tested on Netgear DGND3700v2 (BCM6362) Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200522121524.4161539-6-noltari@gmail.com [Ported to U-Boot from the Linux kernel] Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: rawnand: brcmnand: rename page sizesÁlvaro Fernández Rojas
Current pages sizes apply to controllers after v3.4 Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200522121524.4161539-4-noltari@gmail.com [Ported to U-Boot from the Linux kernel] Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: rawnand: brcmnand: fix CS0 layoutÁlvaro Fernández Rojas
Only v3.3-v5.0 have a different CS0 layout. Controllers before v3.3 use the same layout for every CS. Fixes: 27c5b17cd1b1 ("mtd: nand: add NAND driver "library" for Broadcom STB NAND controller") Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200522121524.4161539-3-noltari@gmail.com [Ported to U-Boot from the Linux kernel] Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: rawnand: brcmnand: rename v4 registersÁlvaro Fernández Rojas
These registers are also used on v3.3. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200522121524.4161539-2-noltari@gmail.com [Ported to U-Boot from the Linux kernel] Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: rawnand: brcmnand: correctly verify erased pagesÁlvaro Fernández Rojas
The current code checks that the whole OOB area is erased. This is a problem when JFFS2 cleanmarkers are added to the OOB, since it will fail due to the usable OOB bytes not being 0xff. Correct this by only checking that data and ECC bytes aren't 0xff. Fixes: 02b88eea9f9c ("mtd: brcmnand: Add check for erased page bitflips") Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200512082451.771212-1-noltari@gmail.com [Ported to U-Boot from the Linux kernel] Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: nand: brcmnand: Add support for flash-dma v0Kamal Dasu
This change adds support for flash dma v0.0. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> [Ported to U-Boot from the Linux kernel] Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: rawnand: brcmnand: Fix ecc chunk calculation for erased page bitfipsClaire Lin
In brcmstb_nand_verify_erased_page(), the ECC chunk pointer calculation while correcting erased page bitflips is wrong, fix it. Fixes: 02b88eea9f9c ("mtd: brcmnand: Add check for erased page bitflips") Signed-off-by: Claire Lin <claire.lin@broadcom.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> [Ported to U-Boot from the Linux kernel] Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: rawnand: brcmnand: Add support for v7.3 controllerKamal Dasu
This change adds support for brcm NAND v7.3 controller. This controller uses a newer version of flash_dma engine and change mostly implements these differences. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> [Ported to U-Boot from the Linux kernel] Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: rawnand: brcmnand: Refactored code to introduce helper functionsKamal Dasu
Refactored NAND ECC and CMD address configuration code to use helper functions. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> [Ported to U-Boot from the Linux kernel] Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27mtd: nand: Mark reserved blocksAshok Reddy Soma
Reserved blocks are used for storing bad block tables. With "nand bad" command, these reserved blocks are shown as bad blocks. This is leading to confusion when compared with Linux bad blocks. Hence, display "bbt reserved" when printing reserved blocks with "nand bad" command. To acheive this, return 2 which represents reserved from nand_isbad_bbt() instead of 1 in case of reserved blocks and catch it in cmd/nand.c. "nand bad" command display's hexadecimal numbers, so add "0x" prefix. Example log will show up as below. ZynqMP> nand bad Device 0 bad blocks: 0x00400000 0x16800000 0x16c00000 0x17000000 0x3d800000 0x3e400000 0xe8400000 0xff000000 (bbt reserved) 0xff400000 (bbt reserved) 0xff800000 (bbt reserved) 0xffc00000 (bbt reserved) 0x116800000 0x116c00000 0x1ff000000 (bbt reserved) 0x1ff400000 (bbt reserved) 0x1ff800000 (bbt reserved) 0x1ffc00000 (bbt reserved) Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Acked-By: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-23ARM: tegra: provide default USB gadget setupMaxim Schwalm
All Nvidia boards use the same manufacturer, vendor ID and product ID for the gadgets. Make them the defaults to remove some boilerplate from the defconfigs. Inspired by commit e02687bda96c ("sunxi: provide default USB gadget setup") which did the same for Allwinner boards. Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124 Signed-off-by: Maxim Schwalm <maxim.schwalm@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23spi: tegra20_slink: accept any word lengthSvyatoslav Ryhel
Original t20 slink could work with commands only fully divisible by 8. This patch removes such restriction, so commands of any bitlength now can be passed and processed. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: tegra: Fix Tegra PWM parent clockSvyatoslav Ryhel
Default parent clock for the PWM on Tegra is a 32kHz clock and is unable to support the requested PWM period. Fix PWM support on Tegra20, Tegra30, Tegra114, Tegra124 and Tegra210 by updating the parent clock for the PWM to be the PLL_P. This commit is equivalent to Linux kernel commit: https://lore.kernel.org/all/20221010100046.6477-1-jonathanh@nvidia.com/ Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # ASUS TF201 T30 Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23usb: dwc3-uniphier: Select PHYMarek Vasut
Make sure the PHY subsystem is activated for the uniphier DWC3 glue logic, as it depends on PHY implementation there. Signed-off-by: Marek Vasut <marex@denx.de>
2023-02-22usb: dwc3-uniphier: Use dwc3-generic instead of xhci-dwc3Kunihiko Hayashi
dwc3-uniphier depends on xhci-dwc3 framework, however, it is preferable to use dwc3-generic. This driver calls the exported dwc3-generic functions and redefine the SoC-dependent operations to fit dwc3-generic. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22phy: socionext: Add UniPhier USB3 PHY driverKunihiko Hayashi
Add USB3 PHY driver support to control clocks and resets needed to enable PHY. The phy_ops->init() and exit() control PHY clocks and resets only, and clocks and resets for the controller and the parent logic are enabled in advance. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22clk: uniphier: Add missing USB SS-PHY clocksKunihiko Hayashi
The USB SS-PHY needs its own clock, however, some clocks don't have clock gates. Define missing clock entries for the PHY as reference clock. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22reset: uniphier: Add USB glue reset supportKunihiko Hayashi
Add reset control support in USB glue logic. This needs to control the external clocks and resets for the logic before accessing the glue logic. The USB dm tree when using dwc3-generic is the following: USB glue +-- controller (need controller-reset) +-- controller-reset (need syscon-reset) +-- phy The controller needs to deassert "controller-reset" in USB glue before the controller registers are accessed. The glue needs to deassert "syscon-reset" before the glue registers are accessed. The glue itself doesn't have "syscon-reset", so the controller-reset controls "syscon-reset" instead. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22usb: dwc3-generic: Add the size of regs property to glue structureKunihiko Hayashi
Add the size of regs property to the glue structure to correctly specify the register region to map. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22usb: dwc3-generic: Export glue structures and functionsKunihiko Hayashi
In order to allow external SoC-dependent glue drivers to use dwc3-generic functions, push the glue structures and export the functions to a header file. The exported structures and functions are: - struct dwc3_glue_data - struct dwc3_glue_ops - dwc3_glue_bind() - dwc3_glue_probe() - dwc3_glue_remove() The SoC-dependent glue drivers can only define their own wrapper driver and specify these functions. The drivers can also add their own compatible strings and configure functions. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22usb: dwc3-generic: Add clock initialization in child DT nodeKunihiko Hayashi
Same as the reset cotnrol, should add a clock initialization in child DT node, if the glue node doesn't have any clocks. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22usb: dwc3-generic: Allow different controller DT node patternKunihiko Hayashi
The most of devicetree has the following USB node structure. The controller node is placed as a child node of the glue node. Current dwc3-generic driver works on this premise. glue { /* glue node */ usb { /* controller node */ }; }; However, UniPhier original devicetree has the following USB node structure. The controller node is separately placed from the glue node. usb { /* controller node */ }; glue { /* glue node */ }; In dwc_glue_bind(), this patch provides .glue_get_ctrl_dev() callback to get such a controller node and binds the driver related to the node. If this callback isn't defined, dwc_glue_bind() looks for the controller nodes from the child nodes, as before. Suggested-by: Marek Vasut <marex@denx.de> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22usb: dwc3: Look up reference clock DT phandle in both controller DT nodesMarek Vasut
There are currently four disparate placement possibilities of DWC3 reference clock phandle in SoC DTs: - in top level glue node, with generic subnode without clock (ZynqMP) - in top level generic node, with no subnode (i.MX8MQ) - in generic subnode, with other clock in top level node (i.MX8MP) - in both top level node and generic subnode (Rockchip) Cover all the possibilities here by looking into both nodes, start with the top level node as that seems to be used in majority of DTs to reference the clock. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
2023-02-22usb: dwc3: Use the devm_gpiod_get_optional() API for reset gpioVenkatesh Yadav Abbarapu
As the "reset-gpios" property is optional, don't return the error and just skip the gpio reset sequence. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
2023-02-17cpsw_mdio.c: Use correct reg in cpsw_mdio_get_aliveUlf Samuelsson
cpsw_mdio_get_alive reads the wrong register. See page 2316 in SPRUH73Q AM335x TRM Signed-off-by: Ulf Samuelsson <ulf@emagii.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2023-02-17driver: cache-v5l2: Fix type casting warning on RV32Yu Chien Peter Lin
This patch fixes following warning for the riscv32 toolchain. drivers/cache/cache-v5l2.c:122:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 122 | regs = (struct l2cache *)dev_read_addr(dev); | ^ Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-02-17riscv: ae350: dts: Update L2 cache compatible stringYu Chien Peter Lin
Update the compatible string of L2 cache. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17driver: cache: cache-v5l2: Update memory-mapped scheme to support Gen2 platformYu Chien Peter Lin
The L2C configuration register has MAP field to indicate its version is v0 (Gen1) or v1 (Gen2) L2-cache. This patch makes the driver compatible with both memory-mapped scheme. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"Leo Yu-Chi Liang
There is no need for RISCV_NDS_CACHE config to control cache switches. Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-14dm: treewide: Complete migration to new driver model schemaSimon Glass
Update various build and test components to use the new schema. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-14dm: Add support for handling old u-boot,dm- tagsSimon Glass
Add a CONFIG option to deal with this automatically, printing a warning when U-Boot starts up. This can be useful if the device tree comes from another project. We will maintain this through the 2023.07 release, providing 6 months for people to notice. Signed-off-by: Simon Glass <sjg@chromium.org> Version 4: Acked-by: Michal Simek <michal.simek@amd.com>
2023-02-13i2c: i2c-cdns.c: Update driver to read fifo-depth from device treePei Yue Ho
Enable driver to fetch the optional parameter (fifo-depth) from device tree. If the parameter is not found in the device tree, it will use the default value declared in the driver. Signed-off-by: Pei Yue Ho <peiyue.ho@starfivetech.com> Reviewed-by: Wei Liang Lim <weiliang.lim@starfivetech.com> Reviewed-by: Eng Lee Teh <englee.teh@starfivetech.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2023-02-13i2c:aspeed:support ast2600 i2c new register mode driverRyan Chen
Add i2c new register mode driver to support AST2600 i2c new register mode. AST2600 i2c controller have legacy and new register mode. The new register mode have global register support 4 base clock for scl clock selection, and new clock divider mode. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2023-02-13i2c: mxc_i2c: Use hex notation for the base addressFabio Estevam
Printing the I2C controller base address in decimal notation is not helpful. Change it to hex notation, which is the standard format found in the Reference Manual and devicetree. Signed-off-by: Fabio Estevam <festevam@denx.de> Acked-by: Dhruva Gole <d-gole@ti.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2023-02-12Merge tag 'clk-2023.04-rc1' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-clk Clock changes for 2023.04-rc1 This contains various fixes and small features. I've included a reset patch as well since it was in the same series as a clock patch.
2023-02-12Merge branch 'for-2023.04' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-mpc8xx - A fix for a long standing bug that has been exposed by commit 50128aeb0f8 ("cyclic: get rid of cyclic_init()") preventing 8xx boards from booting since u-boot 2023.01 - A GPIO driver for powerpc 8xx chip - Fixup for powerpc 8xx SPI driver - A new powerpc 8xx board - The two devices having that board.
2023-02-12reset: Allow reset_get_by_name() with NULL nameSamuel Holland
This allows devm_reset_control_get(dev, NULL) to work and get the first reset control, which is common in code ported from Linux. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20230122000252.53642-2-samuel@sholland.org
2023-02-12clk: Allow clk_get_by_name() with NULL nameSamuel Holland
This allows devm_clock_get(dev, NULL) to work and get the first clock, which is common in code ported from Linux. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20230122000252.53642-1-samuel@sholland.org
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