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2020-10-21arm: stm32: cleanup arch gpio.hPatrick Delaunay
Cosmetic update of gpio.h: - remove enumerate: stm32_gpio_port, stm32_gpio_pin because STM32_GPIO_XXX values are unused - move STM32_GPIOS_PER_BANK in stm32_gpio.c as its value is IP dependent and not arch dependent No functional change as number of banks and number of gpio by banks is managed by device tree since since DM migration and commit 8f651ca60ba1 ("pinctrl: stm32: Add get_pins_count() ops"). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-21mmc: stm32_sdmmc2: Use mmc_of_parse() to read host capabilitiesAlexandru Gagniuc
mmc_of_parse() can populate the 'f_max' and 'host_caps' fields of struct mmc_config from devicetree. The same logic is duplicated in stm32_sdmmc2_probe(). Use mmc_of_parse(), which is more generic. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-10-21mmc: mmc_of_parse: Enable 52 MHz support with "cap-mmc-highspeed"Alexandru Gagniuc
"cap-mmc-highspeed" enables support for 26 MHz MMC, but there is no additional flag to enable 52 MHz MMC. In Linux. "cap-mmc-highspeed" is used for MMC HS at both 26MHz and 52MHz. Use the same approach and enable MMC_CAP(MMC_HS_52) host capability when "cap-mmc-highspeed" is found in the devicetree. In the event an MMC card doesn't support 52 MHz, it will be clocked at a speed based on its EXT CSD, even on 52 MHz host controllers Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-19Merge tag 'u-boot-atmel-2021.01-b' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-atmel Second set of u-boot-atmel features for 2021.01 cycle: This feature set brings the rework of the clock tree for sam9x60 SoC. This makes the clock tree fully compatible with Common Clock Framework and allows full clock configuration in U-Boot. This means that the sam9x60 boards can boot now using U-Boot. This also includes the definitions for sam9x60 SiPs and a divisor fix for the clock on sama7g5 SoC.
2020-10-19clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristicsEugen Hristev
This SoC has the 5th divisor for the mck0 master clock. Adapt the characteristics accordingly. Reported-by: Mihai Sain <mihai.sain@microchip.com> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19clk: at91: clk-master: add 5th divisor for mck masterEugen Hristev
clk-master can have 5 divisors with a field width of 3 bits on some products. Change the mask and number of divisors accordingly. Reported-by: Mihai Sain <mihai.sain@microchip.com> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19clk: at91: sam9x60: add support compatible with CCFClaudiu Beznea
Add SAM9X60 clock support compatible with CCF. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-18configs: migrate CONFIG_BMP_16/24/32BPP to defconfigsPatrick Delaunay
Done with: ./tools/moveconfig.py BMP_16BPP BMP_24BPP BMP_32BPP Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-18configs: migrate CONFIG_VIDEO_BMP_RLE8 to defconfigsPatrick Delaunay
Done with: ./tools/moveconfig.py VIDEO_BMP_RLE8 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-18configs: migrate CONFIG_VIDEO_BMP_GZIP to defconfigsPatrick Delaunay
Done with: ./tools/moveconfig.py VIDEO_BMP_GZIP The 3 suspicious migration because CMD_BMP and SPLASH_SCREEN are not activated in these defconfigs: - trats_defconfig - s5pc210_universal_defconfig - trats2_defconfig Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-18video: backlight: fix pwm's duty cycle calculationDario Binacchi
For levels equal to the maximum value, the duty cycle must be equal to the period. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-18video: backlight: fix pwm data structure descriptionDario Binacchi
The description of the 'max_level' field was incorrectly assigned to the 'min_level' field. Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-10-18video: dw-mipi-dsi: permit configuring the escape clock rateNeil Armstrong
The Amlogic D-PHY in the Amlogic AXG SoC Family does support a frequency higher than 10MHz for the TX Escape Clock, thus make the target rate configurable. This is based on the Linux commit [1] and adapted to the U-Boot driver. [1] a328ca7e4af3 ("drm/bridge: dw-mipi-dsi: permit configuring the escape clock rate") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-18video: dw-mipi-dsi: driver-specific configuration of phy timingsNeil Armstrong
The timing values for dw-dsi are often dependent on the used display and according to Philippe Cornu will most likely also depend on the used phy technology in the soc-specific implementation. To solve this and allow specific implementations to define them as needed add a new get_timing callback to phy_ops and call this from the dphy_timing function to retrieve the necessary values for the specific mode. This is based on the Linux commit [1] and adapted to the U-Boot driver. [1] 25ed8aeb9c39 ("drm/bridge/synopsys: dsi: driver-specific configuration of phy timings") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-16Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini
- Fix Octeon SPI driver for Octeon TX2 - Fix and enhance Octeon watchdog driver - Misc minor enhancements to Octeon TX/TX2
2020-10-16usb: dwc3: Include device_compat.h in dwc3-octeon-glue.cTom Rini
Necessary for dev_xxx. Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-16clk: at91: Include device_compat.h in compat.cTom Rini
Necessary for dev_xxx. Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-16usb: musb-new: mt85xx: Fix not calling dev_err with a deviceSean Anderson
This driver doesn't use DM (in the correct places), so we use a device and not a udevice. We also need to include device_compat.h Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-16usb: musb-new: Include device_compat.hSean Anderson
This was included, but was ifdef'd out. We also need dm.h for struct udevice. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-16usb: xhci: Include device_compat.hSean Anderson
This header is necessary for the dev_xxx macros. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-16timer: Include device_compat.hSean Anderson
Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-16tee: optee: Include device_compat.hSean Anderson
Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-16spi: fsl_qspi: Include device_compat.hSean Anderson
Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-16spi: nxp_fspi: Include device_compat.hSean Anderson
Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-16watchdog: octeontx_wdt: Add support for start and stopSuneel Garapati
This patch enhances the Octeon TX/TX2 watchdog driver to fully enable the WDT. With this changes, the "wdt" command is now also supported on these platforms. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Suneel Garapati <sgarapati@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
2020-10-16mmc: octeontx_hsmmc.c: Remove test debug messageStefan Roese
Remove a left-over debug test message from the Octeon TX / TX2 MMC driver. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Suneel Garapati <sgarapati@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
2020-10-16spi: octeon_spi: Use a fixed 100MHz input clock on Octeon TX2Stefan Roese
Octeon TX2 sets the TB100_EN bit in the config register. We need to use a fixed 100MHz clock for this as well to work properly. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Suneel Garapati <sgarapati@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Jagan Teki <jagan@amarulasolutions.com>
2020-10-15ram: imxrt: Include device_compat.hSean Anderson
Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-15phy: Include device_compat.hSean Anderson
Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-15net: ldpaa_eth: Include device_compat.hSean Anderson
Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-15mtd: mxs_nand: Fix not calling dev_xxx with a deviceSean Anderson
This includes device_compat.h, and fixes several calls to dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-15firmware: scmi: Include device_compat.hSean Anderson
This header is necessary for the dev_xxx macros. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-15dm: syscon: Set LOG_CATEGORYSean Anderson
We call log_debug, but do not have a category set. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-15clk: sifive: Include device_compat.hSean Anderson
Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-15Merge tag 'mmc-2020-10-14' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-mmc - fsl_esdhc_imx cleanup - not send cm13 if send_status is 0. - Add reinit API - Add mmc HS400 for fsl_esdhc - Several cleanup for fsl_esdhc - Add ADMA2 for sdhci
2020-10-14Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini
- Octeon TX: Add NAND driver (Suneel) - Octeon TX: Add NIC driver driver (Suneel) - Octeon TX2: Add NIC driver driver (Suneel) - Armada 8040: Add iEi Puzzle-M80 board support (Luka) - Armada A37xx SPI: Add support for CS-GPIO (George) - Espressobin: Use Linux model/compatible strings (Andre) - Espressobin: Add armada-3720-espressobin-emmc.dts from Linux (Andre) - Armada A37xx: Small cleanup of config header (Pali)
2020-10-14net: e1000: add defaults for i210 TX/RX PBSIZEChristian Gmeiner
Set the defaults on probe for the packet buffer size registers for the i210. The TX/RX PBSIZE register of the i210 resets to its default value only at power-on - see Intel Ethernet Controller I210 Datasheet rev 3.5 chapter 8.3 'Internal Packet Buffer Size Registers'. If something (another driver, another OS, etc.) modifies this register from its default value, the e1000 driver doesn't function correctly. It detects a hang of the transmitter and continuously resets the adapter. Here we set this value to its default when resetting the i210 to resolve this issue. Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2020-10-14treewide: Fix wrong CONFIG_IS_ENABLED() handlingAlper Nebi Yasak
CONFIG_IS_ENABLED() takes the kconfig name without the CONFIG_ prefix, e.g. CONFIG_IS_ENABLED(CLK) for CONFIG_CLK. Some of these were being fixed every now and then, see: commit 71ba2cb0d678 ("board: stm32mp1: correct CONFIG_IS_ENABLED usage for LED") commit a5ada25e4213 ("rockchip: clk: fix wrong CONFIG_IS_ENABLED handling") commit 5daf6e56d36c ("common: console: Fix duplicated CONFIG in silent env callback") commit 48bfc31b6484 ("MIPS: bootm: Fix broken boot_env_legacy codepath") Fix all files found by `git grep "CONFIG_IS_ENABLED(CONFIG"` by running ':%s/CONFIG_IS_ENABLED(CONFIG_\(\w+\))/CONFIG_IS_ENABLED(\1)/g' in vim. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-14mmc: remove duplicate mmc_get_env_dev() implementationsDavid Woodhouse
Since it's so trivial I could just about tolerate this when there were only two copies of it. But now there are about to be three. Signed-off-by: David Woodhouse <dwmw2@infradead.org>
2020-10-14drivers: gpio: keep output value for input on sandboxHeinrich Schuchardt
For testing purposes keep the output value when switching to input. This allows us to manipulate the input value via the gpio command. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
2020-10-14mmc: fsl_esdhc: add ADMA2 supportMichael Walle
Newer eSDHC controllers support ADMA2 descriptor tables which support 64bit DMA addresses. One notable user of addresses in the upper memory segment is the EFI loader. If support is enabled, but the controller doesn't support ADMA2, we will fall back to SDMA (and thus 32 bit DMA addresses only). Signed-off-by: Michael Walle <michael@walle.cc>
2020-10-14mmc: fsl_esdhc: replace most #ifdefs by IS_ENABLED()Michael Walle
Make the code cleaner and drop the old-style #ifdef constructs where it is possible. Signed-off-by: Michael Walle <michael@walle.cc>
2020-10-14spi: mvebu_a3700_spi: add support for cs-gpiosGeorge Hilliard
The device tree has a way to specify GPIO lines as chip selects. From the binding docs: So if for example the controller has 2 CS lines, and the cs-gpios property looks like this: cs-gpios = <&gpio1 0 0> <0> <&gpio1 1 0> <&gpio1 2 0>; Then it should be configured so that num_chipselect = 4 with the following mapping: cs0 : &gpio1 0 0 cs1 : native cs2 : &gpio1 1 0 cs3 : &gpio1 2 0 Add support for this, while retaining backward-compatibility with existing device trees; the driver will preserve existing behavior if a cs-gpios list is not given, or if a particular line is specified as <0> (native). This implementation is inspired by similar implementations in neighboring drivers for other platforms: atmega, mxc, etc. Signed-off-by: George Hilliard <ghilliar@amazon.com> Reviewed-by: Stefan Roese <sr@denx.de>
2020-10-14net: Add NIC controller driver for OcteonTX2Suneel Garapati
Adds support for Network Interface controllers found on OcteonTX2 SoC platforms. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com>
2020-10-14net: Add NIC controller driver for OcteonTXSuneel Garapati
Adds support for Network Interface controllers found on OcteonTX SoC platforms. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com>
2020-10-14mtd: nand: Add NAND controller driver for OcteonTXSuneel Garapati
Adds support for NAND controllers found on OcteonTX or OcteonTX2 SoC platforms. Also includes driver to support Hardware ECC using BCH HW engine found on these platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-12Merge branch 'for-next' of https://github.com/lftan/u-bootTom Rini
2020-10-12Merge tag 'ti-v2021.01-rc1' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-ti - Minor cleanup on K3 env variables - Fix OSPI compatible for J721e - Drop unused property in omap-usb2-phy - Update Maintainer for am335x-guardian board.
2020-10-12mmc: fsl_esdhc_imx: replace all readl/writel to esdhc_read32/esdhc_write32Haibo Chen
Currently, readl/writel and esdhc_read32/esdhc_write32 are used. To align the usage, change to only use esdhc_read32/esdhc_write32. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
2020-10-12mmc: do not check argument of free() beforehandHeinrich Schuchardt
free() checks if its argument in NULL. No need to check it twice. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
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