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2021-12-23dm: core: Allow getting some basic statsSimon Glass
Add a function that returns some basic stats about driver model. For now we only have two. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-21pci: pci_mvebu: Remove unused DECLARE_GLOBAL_DATA_PTRPali Rohár
The global data pointer is not used in this driver, remove it's declaration. Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-12-21pci: pci_mvebu: Replace MBUS_PCI_*_SIZE by resource_size()Pali Rohár
Use more appropriate resource_size() function when working with data in struct resource. Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-12-21pci: pci_mvebu: Move setup for BAR[0] where other BARs are setupPali Rohár
Function mvebu_pcie_setup_wins() sets up all other BARs, so move setup of BAR[0] to this function to have common code at one place. In the past, commit 193a1e9f196b ("pci: pci_mvebu: set BAR0 after memory space is set") moved setup of BAR[0] to another location, due to ath10k not working in kernel, but the reason why was unknown, but it seems to work now, and we think the issue then was cause by the PCIe Root Port presenting itself as a Memory Controller and therefore U-Boot's code have overwritten the BAR. Since the driver now ignores any write operations to PCIe Root Port BARs, this should not be an issue anymore. Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-12-20Merge tag 'v2022.01-rc4' into nextTom Rini
Prepare v2022.01-rc4
2021-12-20i2c: mvtwsi: Swab the register address if its size is > 1Stefan Roese
Testing on Armada XP with an EEPROM using register address with size of 2 has shown, that the register address bytes are sent to the I2C EEPROM in the incorrect order. This patch swabs the address bytes so that the correct address is transferred to the I2C device. BTW: This worked without any issues before migrating Armada XP to DM I2C. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Samuel Holland <samuel@sholland.org> Cc: Baruch Siach <baruch@tkos.co.il> Cc: Pali Rohár <pali@kernel.org> Cc: Marek Behún <marek.behun@nic.cz> Tested-by: Marek Behún <marek.behun@nic.cz>
2021-12-19arm: mvebu: serial: Add me as co-maintainer and author of Marvell serial driversPali Rohár
There is no maintainer entry for serial_mvebu_a3700.c. Add entry with Pali and Stefan as maintainers. Signed-off-by: Pali Rohár <pali@kernel.org> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Stefan Roese <sr@denx.de>
2021-12-19arm: mvebu: pci: Add me as co-maintainer and author of Marvell PCIe driversPali Rohár
There is no maintainer entry for pci-aardvark.c. Add entry for pci-aardvark.c and pci_mvebu.c with Pali and Stefan as maintainers. Signed-off-by: Pali Rohár <pali@kernel.org> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Stefan Roese <sr@denx.de>
2021-12-19phy: marvell: a3700: Convert to official DT bindings in COMPHY driverPali Rohár
Convert A3720 common PHY driver to official DT bindings. This puts us closer to be able to synchronize A3720 device-trees with those from Linux. Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Konstantin Porotchkin <kostap@marvell.com> Cc: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Marcin Wojtas <mw@semihalf.com> Cc: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Stefan Roese <sr@denx.de>
2021-12-19fdt_support: Remove FDT_STATUS_FAIL_ERROR_CODEMarek Behún
Since no one uses this feature and I am not aware of any parsers of this in Linux, remove it. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Pratyush Yadav <p.yadav@ti.com> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Michael Walle <michael@walle.cc> Cc: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-12-19treewide: Use fdt_create_phandle() where appropriateMarek Behún
Replace fdt_alloc_phandle() with subsequent fdt_set_phandle() by fdt_create_phandle(). Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Vladimir Oltean <vladimir.oltean@nxp.com>
2021-12-19arm: mvebu: axp: ddr: Switch to using DM I2C APIStefan Roese
No functional change intended. This patch switches from the legacy I2C API to the DM I2C API, so that this code can be used with DM I2C enabled. Signed-off-by: Stefan Roese <sr@denx.de>
2021-12-19arm: mvebu: axp: Remove unreferenced ddr3_get_eprom_fabric() functionStefan Roese
This function is not referenced in mainline U-Boot. Let's remove now. Signed-off-by: Stefan Roese <sr@denx.de>
2021-12-18blk: add a helper function, blk_probe_or_unbind()AKASHI Takahiro
This function will be commonly used in block device drivers in the succeeding patches. Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2021-12-17Merge tag 'u-boot-at91-2022.04-a' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-at91 into next First set of u-boot-at91 features for the 2022.04 cycle: This feature set includes : support for the new QSPI hardware on sama7g5, small fixes on sam9x60 and sama7g5, some additions of commands and PIO controller on sam9x60/sam9x60ek.
2021-12-17arm: socfpga: arria10: Enable double peripheral RBF configurationTien Fong Chee
Double peripheral RBF configuration are needed on some devices or boards to stabilize the IO configuration system. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-12-15Merge tag 'clk-2022.01-rc3' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-clk Clock patches for v2022.01-rc3 This adds better logging support for many CCF drivers, and clarifies some documentation regarding clk_get_rate.
2021-12-15clk: define LOG_CATEGORY for generic and ccf clocksPatrick Delaunay
Define LOG_CATEGORY to allow filtering with log command for generic clock and CCF clocks. This patch also change existing printf, debug and pr_ macro to log_ or dev_ macro. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2021-12-15clk: cosmetic: reorder include filesPatrick Delaunay
Reorder include files in the U-Boot expected order: the common.h header should always be first, followed by other headers in order, then headers with directories, then local files. It is a preliminary step for next patch. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2021-12-15arm: a37xx: pci: Do not allow setting ROM BAR on PCI BridgePali Rohár
PCI Bridge which represents aardvark PCIe Root Port has Expansion ROM Base Address register at offset 0x30 but its meaning is different than PCI's Expansion ROM BAR register. Only address format of register is same. In reality, this device does not have any configurable PCI BARs. So ensure that write operation into BARs (including Expansion ROM BAR) is noop and registers always contain zero address which indicates that bars are unsupported. Fixes: cb056005dc67 ("arm: a37xx: pci: Add support for accessing PCI Bridge on root bus") Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-12-15pci: pci_mvebu: Do not allow setting ROM BAR on PCI BridgePali Rohár
The PCI Bridge which represents mvebu PCIe Root Port has Expansion ROM Base Address register at offset 0x30 but its meaning is different that of PCI's Expansion ROM BAR register, although the address format of the register is the same. In reality, this device does not have any configurable PCI BARs. So ensure that write operation into BARs (including Expansion ROM BAR) is a noop and registers always contain zero address which indicates that BARs are unsupported. Fixes: a7b61ab58d5d ("pci: pci_mvebu: Properly configure and use PCI Bridge (PCIe Root Port)") Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-12-15pci: pci_mvebu, pci_aardvark: Fix size of configuration cacheMarek Behún
Since u32 takes up 4 bytes, we need to divide the number of u32s by 4 for cfgcache. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-12-13net: ravb: Support multiple clocksAdam Ford
The RZ/G2 series uses an external clock as a reference to the AVB. If this clock is controlled by an external programmable clock, it must be requested by the consumer or it will not turn on. In order to do this, update the driver to use bulk enable and disable functions to enable clocks for boards with multiple clocks. Signed-off-by: Adam Ford <aford173@gmail.com>
2021-12-09efi: Add a media/block driver for EFI block devicesSimon Glass
Add a block driver which handles read/write for EFI block devices. This driver actually already exists ('efi_block') but is not really suitable for use as a real U-Boot driver: - The operations do not provide a udevice - The code is designed for running as part of EFI loader, so uses EFI_PRINT() and EFI_CALL(). - The bind method probes the device, which is not permitted - It uses 'EFI' as its parent device The new driver is more 'normal', just requiring its platform data be set up in advance. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2021-12-09efi: Add uclass for devices provided by UEFI firmwareSimon Glass
UCLASS_EFI_LOADER is used for devices created by applications and drivers loaded by U-Boots UEFI implementation. This patch provides a new uclass (UCLASS_EFI_MEDIA) to be used for devices that provided by a UEFI firmware calling U-Boot as an EFI application. If the two uclasses can be unified, is left to future redesign. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2021-12-09efi: Rename UCLASS_EFI and IF_TYPE_EFISimon Glass
These names are better used for access to devices provided by an EFI layer. Use EFI_LOADER instead here, since these are only available in U-Boot's EFI_LOADER layer. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2021-12-07spi: atmel-quadspi: Add support for SAMA7G5 QSPITudor Ambarus
sama7g5 QSPI has: 1/ One Octal Serial Peripheral Interfaces (QSPI0) Supporting Up to 200 MHz DDR. Octal, TwinQuad, Hyperflash and OctaFlash Protocols Supported 2/ One Quad Serial Peripheral Interfaces (QSPI1) Supporting Up to 90 MHz DDR/133 MHz SDR The QSPI controller of SAMA7G5 uses different clock domains, hence extra synchronization operations must be performed before accessing some registers. Differentiate between the versions of the IP using has_gclk. Differentiate between QSPI0 and QSPI1 with has_octal. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-12-05ide: Drop ATA_PORT_ADDRSimon Glass
This is not needed anymore. Drop it to simplify the code. Signed-off-by: Simon Glass <sjg@chromium.org> Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-12-05ide: Drop unused CONFIG optionsSimon Glass
CONFIG_SYS_ATA_PORT_ADDR is not used in the code anymore. Drop it and use ATA_PORT_ADDR() locally instead. Drop CONFIG_IDE_RESET_ROUTINE and CONFIG_IDE_SWAP_IO which are also unused. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-05Convert CONFIG_KEYBOARD to KconfigSimon Glass
This converts the following to Kconfig: CONFIG_KEYBOARD Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-05sandbox: Drop CONFIG_HOST_MAX_DEVICESSimon Glass
This can go in the related header file. Drop the CONFIG option. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-12-03Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini
2021-12-02drivers: core: lists: fix for loop index typeAlexander Preißner
* fixes the bug in function bind_drivers_pass that for CONFIG_CC_OPTIMIZE_FOR_SIZE=n and no entries in the driver_info list, i.e. n_ents == 0, the processor steps into the first loop iteration despite the loop condition being false. * the Xilinx Zynq-7000 device would eventually hang due to an attempted access to an invalid memory address * the bug is fixed by changing the type of idx from uint to int Board: zynq-zybo Target: ARM Compiler: arm-none-eabi-gcc 9.2.1 Signed-off-by: Alexander Preissner <fpga-garage@preissner-muc.de> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2021-12-02Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-net ↵Tom Rini
into next - New Broadcom NetXtreme driver - Support for socat for netconsole - Felix switch soft reset fix
2021-12-02i2c: Add Microchip PolarFire SoC I2C driverPadmarao Begari
Add I2C driver code for the Microchip PolarFire SoC. This driver supports I2C data transfer and probe for I2C slave addresses. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-12-02net: macb: Remove Microchip compatible stringPadmarao Begari
Remove the microchip compatible string and default compatible "cdns,macb" support both 32-bit and 64-bit DMA access. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-12-02net: dwc_eth_qos: Enable clock in probeMarek Vasut
Enable DWC IP clock in driver probe, so the MII access is possible even outside of active network transfers. This is particularly useful when using 'mii' or 'mdio' commands to explore PHY state, neither of which works with DWMAC currently due to the disabled clock. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Stephen Warren <swarren@nvidia.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-12-02net: eth-phy: Handle gpio_request_by_name() return valueMarek Vasut
The gpio_request_by_name() returns zero in case of success, however the conditional return value check in gpio_request_by_name() checks only for (ret != -ENOENT) and if the condition is true, returns ret outright. This leads to a situation where successful gpio_request_by_name() return leads to immediate successful eth_phy_of_to_plat() return as well, and to skipped parsing of "reset-assert-us" and "reset-deassert-us", so the PHY driver operates with valid reset GPIO, but with assert/deassert times set to default, which is 0, instead of the values from DT. This breaks PHY reset. Fix this by checking if return value is non-zero and then for this one single allowed non-zero return value, -ENOENT. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-12-02net: brcm: netXtreme driverBharat Gooty
Broadcom bnxt L2 driver support. Used by the Broadcom iproc platforms. Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Roman Bacik <roman.bacik@broadcom.com>
2021-12-02driver: net: Makefile: order file alphabeticallyRamon Fried
Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
2021-12-02drivers: net: Soft reset felix switch coreRadu Bulie
It turns out that in custom designs if the system is reset multiple times in conjunction with a slight increase in external temperature, the felix switch starts to behave in a strange way: packets are no longer received on the ENECT interface connected to the L2switch internal port (the TX side of internal port stops working or the packets do not reach there. It is not very clear where the packets remain blocked. None of the counters points to a disruption in the L2switch) The issue is not reproducible on NXP reference designs. It was observed that by adding the switch core reset, the problem goes aways, even if intensive testing in temperature chambers is applied. The current patch performs soft reset on the switch core to ensure proper operation of the L2switch. Signed-off-by: Radu Bulie <radu-andrei.bulie@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-12-01dm: add debug message when failed to select the default pinctrlPatrick Delaunay
Add a message on probe in driver model core when the default pinctrl selection failed. This message is displayed only when the pinctrl API is implemented, i.e. when result is not ENOSYS. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-12-01Convert CONFIG_SYS_BR0_PRELIM et al to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SYS_BR0_PRELIM CONFIG_SYS_OR1_PRELIM CONFIG_SYS_BR1_PRELIM CONFIG_SYS_OR2_PRELIM CONFIG_SYS_BR2_PRELIM CONFIG_SYS_OR2_PRELIM CONFIG_SYS_BR3_PRELIM CONFIG_SYS_OR3_PRELIM CONFIG_SYS_BR4_PRELIM CONFIG_SYS_OR4_PRELIM CONFIG_SYS_BR5_PRELIM CONFIG_SYS_OR5_PRELIM CONFIG_SYS_BR6_PRELIM CONFIG_SYS_OR6_PRELIM CONFIG_SYS_BR7_PRELIM CONFIG_SYS_OR7_PRELIM This also introduces CONFIG_SYS_BR0_PRELIM_BOOL as not all platforms that can set these values do so. Add the relevant SYS_BRx_PRELIM_BOOL to platforms that had not been previously migrated. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-30ram: stm32mp1: remove __maybe_unused on stm32mp1_ddr_setupPatrick Delaunay
Since the commit f42045b2e750 ("stm32mp15: replace CONFIG_TFABOOT when it is possible") the function stm32mp1_ddr_setup is always called so the __maybe_unused can be removed. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-11-30ram: stm32mp1: compute DDR size from DDRCTL registersPatrick Delaunay
Compute the DDR size from DDR controller register (mstr and addrmap) in U-Boot proper as the DDR information are useful only for SPL but not for U-Boot proper, for example with TFABOOT. This patch simplify U-Boot DT when several DDR size are supported and support of next SOC in STM32MP family. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-30video: stm32: stm32_ltdc: align framebuffer on 2MBPatrick Delaunay
Align the framebuffer size on MMU_SECTION_SIZE in kernel, = max 2MB for LPAE for armV7, to avoid issue with the simple frame buffer activation, when U-Boot add a reserved memory in the kernel device tree to preserve the splash screen until Linux driver initialization. See Linux documentation for details: Documentation/devicetree/bindings/display/simple-framebuffer.yaml Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-11-30video: Add video_is_active functionPatrick Delaunay
Add the helper function video_is_active() to test if one video device is active. This function can be used in board code to execute operation only when the display is probed / really used. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-11-30stm32mp1: ram: remove tuning supportPatrick Delaunay
Remove the DDR interactive command tuning, as the support of a predefined DDR PHY tuning is removed for STM32MP1 driver in SPL and in TF-A and the result of this tuning will be never used. Moreover this SW tuning procedure can failed on some hardware configuration (to many BIST errors and no convergence); it will be no more supported in the next delivery of the DDR utilities included in the CubeMX tool of STMicroelectronics. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-11-30stm32mp1: ram: remove the support of calibration resultPatrick Delaunay
The support of a predefined DDR PHY tuning result is removed for STM32MP1 driver because it is not needed at the supported frequency when built-in calibration is executed. The calibration parameters were provided in the device tree by the optional node "st,phy-cal", activated in ddr helper file by the compilation flag DDR_PHY_CAL_SKIP and filled with values generated by the CubeMX DDR utilities. This patch - updates the binding file to remove "st,phy-cal" support - updates the device trees and remove the associated defines - simplifies the STM32MP1 DDR driver and remove the support of the optional parameter "st,phy-cal" After this patch, the built-in calibration is always executed and the calibration registers are moved in the phy dynamic part; that allows manual tests. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-11-30stm32mp1: ram: add read valid training supportPatrick Delaunay
Add the read data eye training = training for optimal read valid placement (RVTRN) when the built-in calibration is executed for LPDDR2 and LPDDR3. This training is supported on the PUBL integrated in the STM32MP15x DDR subsystem and it is not required for DDR3. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-06 19:29:12 +0000