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Svyatoslav Ryhel <clamor95@gmail.com> says:
Add uclass for HW AES cryptographic devices found on some devices, like
Tegra20/Tegra30 SoC AES engine.
Link: https://lore.kernel.org/r/20250629105711.24687-1-clamor95@gmail.com
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This adds AES crypto engine using the AES Uclass implemented in software,
serves as example implementation and for uclass tests.
Those implementing HW AES crypto engine drivers can use this as basis and
replace software parts with the HW specifics of their device.
Signed-off-by: Ion Agorria <ion@agorria.com>
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Create a basic framework for a group of devices that perform AES
cryptographic operations.
Signed-off-by: Ion Agorria <ion@agorria.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27010
- Fix the i.MX8M Nano GPU path.
- Enable RNG support for KASLR on Toradex i.MX8 boards.
- Enable watchdog and clock driver for imx6ulz_smm_m2b.
- Tighten dependencies on CMD_BLOB.
- Remove the rest of i.MX31 support.
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- SH Ether clean ups, RZ/A1 clean ups, RZ/A1 Genmai support
- Gen3 EEPROM DT node clean up
- V4H SA0 BootROM compatible binman etype, SCIF compatible SREC
generation for Gen4
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Drop CFG_SH_ETHER_PHY_ADDR from README and configuration files, this
value is never used, PHY address is extracted from control DT instead.
No functional change intended.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
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Drop unused struct sh_eth_info *port_info .phy_addr member assignment.
PHY address is extracted from control DT. No functional change intended.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
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Turn the current cache operation macros into static functions to improve
compiler coverage checking. This does change the driver behavior slightly,
the driver now expects those cache operation functions to be available on
all architectures on which it is used. This should pose no problem, as the
driver is only used on 32bit and 64bit ARM, which both have those operations.
The CFG_SH_ETHER_ALIGNE_SIZE is converted to SH_ETHER_ALIGN_SIZE and defined
as either 64 on ARM or 16 on SH.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
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The CFG_SH_ETHER_USE_PORT configuration option is a remnant from
before U-Boot DM existed and SH Ethernet made full use of it, and
is no longer used, remove it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
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The struct sh_eth_dev .port member is always set to 0, therefore only
single-ported SH Ethernet is ever used. Support for multiple SH Ethernet
ports implemented on driver level is a remnant from before U-Boot DM
existed.
Pass struct sh_eth_info port_info around directly and remove the
struct sh_eth_dev entirely. Handling of multiple ports should be done
by U-Boot DM and multiple per-driver-instance private data.
No functional change intended.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
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The use of log_msg_ret to log a message and return an error meant that
memory allocated earlier in the function was not freed on this error
path. Instead log the message in the same way that log_msg_ret would do
and then goto the cleanup code to free the memory.
This issue found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
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Update the ICSSG PRU Ethernet driver to read PRU/RTU/TXPRU firmware names
from the Device Tree using the "firmware-name" property, instead of relying
on the hard-coded firmware names. The firmware names are parsed during
prueth_probe() and stored in the prueth->firmwares for each slice. The
driver now uses these dynamically loaded names when starting the PRU cores.
This change improves flexibility and allows firmware selection to be
controlled via the device tree, making the driver more adaptable to
different platforms and firmware configurations.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
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A few adc drivers cannot build without access to some platform specific
header files. Express those requirements in Kconfig as well.
Signed-off-by: Tom Rini <trini@konsulko.com>
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First, the SATA_MV driver can only build on kirkwood or mvebu platforms
due to header requirements, so add that as a dependency here. Second,
SYS_SATA_MAX_DEVICE is also used by the API code so allow it to be
configured in that case.
Reviewed-by: Tony Dinh <mibodhi@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
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Some of the aspeed platform drivers cannot build without platform
specific headers being available. Express those requirements in Kconfig as
well.
Signed-off-by: Tom Rini <trini@konsulko.com>
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These drivers require various headers which only exist on the ARM /
PowerPC platforms which implement the hardware. Express that requirement
in Kconfig as well.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
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The nuvoton AES driver cannot build without platform specific headers
being available. Express that requirement in Kconfig as well.
Signed-off-by: Tom Rini <trini@konsulko.com>
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The TI EDMA3 driver cannot build without platform specific headers being
available. Express that requirement in Kconfig as well.
Signed-off-by: Tom Rini <trini@konsulko.com>
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A large number of gpio drivers cannot build without access to some platform
specific header files. Express those requirements in Kconfig as well.
Signed-off-by: Tom Rini <trini@konsulko.com>
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If phy node isn't found in ethernet-phy subnode, try to get it from
phy-handle. And when this fails, only then use Ethernet node. This
fix results in getting correct phy handle properties for the
phy node if defined.
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
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With the removal of the last i.MX31 platform we can remove the rest of
the underlying architecture code as well.
Fixes: f247354708ec ("arm: Remove mx31pdk board")
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
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This driver has no users after we removed the last supported platform in
2024.
Fixes: 26ed58b40f58 ("arm: Remove devkit3250 board")
Signed-off-by: Tom Rini <trini@konsulko.com>
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This driver has no users after we removed the last supported platform in
2023.
Fixes: 7a3ee61f5551 ("arm: Remove omap5_uevm board")
Signed-off-by: Tom Rini <trini@konsulko.com>
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Green Eco"
Romain Gantois <romain.gantois@bootlin.com> says:
This is version one of my series which enables Ethernet support on the BBGE
board. This requires three main changes:
- Describing the MAC<->PHY link and DP83867 PHY accurately in the device
tree
- Enabling the RGMII1 pinmux configuration
- Enabling the DP83867 driver
These changes are all applied in patch 2.
Patch 1 enables excluding the DP83867 driver from SPL. This is done to
avoid size issues when adding the DP83867 driver to the am335x-evm
defconfig.
Link: https://lore.kernel.org/r/20250626-bbge-ethernet-v1-0-5b544fb1898f@bootlin.com
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The DP83867 PHY driver is used by the BeagleBoneGreen Eco board, but adding
it to the am335x-evm defconfig causes SPL to overflow its size limits.
Add a separate option to enable this driver in SPL, so that it can be
enabled in U-Boot without adding unnecessary volume to SPL.
Signed-off-by: Romain Gantois <romain.gantois@bootlin.com>
Tested-by: Judith Mendez <jm@ti.com>
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The commit under fixes tag includes "pcie-cadence.h" using angle
brackets. Since the header file is not in standard include path change
it to double quotes to ensure proper inclusion and avoid build issues,
especially on older compilers.
Fixes: a4a0edc6046 ("pci_endpoint: Add TI K3 Cadence PCIe Endpoint Controller driver")
Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
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In DDR mode, even bytes are read using DMA, while the remaining odd
bytes are read using STIG mode. However, the data is not correctly
transferred into the flash read data lower register because the
supplementary byte of the STIG opcode is not being written to the
opcode extension register, resulting in incorrect data being read.
To resolve this issue, when using STIG transactions, the corresponding
supplementary byte of any STIG opcode must be defined in the Opcode
Extension Register (Lower). Issue has been observed on the Macronix
MX66UM2G45G flashes.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20250702053953.640046-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
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tshsl_ns is the clock delay for chip select deassert. This is the delay in
master reference clocks for the length that the master mode chip select
outputs are de-asserted between transactions.
The minimum delay is always SCLK period to ensure the chip select is never
re-asserted within one SCLK period.
That is why tshsl_ns delay should be at least one sclk_ns value. If it is
less than sclk_ns, set it equal to sclk_ns.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20250702065717.3871435-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
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Starting from 'commit <8077d296adff> ("spi: cadence-quadspi: Use STIG
mode for all ops with small payload") the utilization of STIG mode
has been implemented for read and write operations involving less
than 8 bytes of data.
However, following this commit, encountering timeout issues occurs when
writing odd bytes of data in DDR mode, as indicated below:
"jedec_spi_nor flash@0: flash operation timed out
SF: 3 bytes @ 0x0 Written: ERROR -110"
To resolve this issue, the number of bytes to write has been updated
specifically for DDR mode.
Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20250704040444.671604-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
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While sending bitstream via SIP SMC, busy status received does not
correspond to error, instead it means transfer is accepted but SDM
doesn't have any more free buffer space. Hence, data transmission
is continued when busy status is received.
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Link: https://lore.kernel.org/r/20250701044311.3670-1-nareshkumar.ravulapalli@altera.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
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Reset the host controller at the early stage of probe so that the
configuration will be done properly for reboot cases.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20250626062440.295301-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
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Separate code to own function to be able to add new enhancement format.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/cf99fe1af82bc004de3e313d4018464f4504f380.1750858165.git.michal.simek@amd.com
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The ZYNQMP_FIRMWARE code cannot build without platform specific headers
being available. Express that requirement in Kconfig as well.
Signed-off-by: Tom Rini <trini@konsulko.com>
Link: https://lore.kernel.org/r/20250702010410.18828-1-trini@konsulko.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
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The clock driver fails to correctly calculate the PLL clock
rate for peripherals when using the DPLL as the clock source.
The DPLL operates within the full power domain, while peripheral
clocks reside in the low power domain. To ensure accurate PLL
clock rate computation when the peripheral clock source is set
to DPLL, the DPLL-to-LPD cross divisor is used.
Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Link: https://lore.kernel.org/r/20250618094329.296731-1-padmarao.begari@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
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Driver fully depends on firmware driver to be present that's why change
imply to depends on to cover it.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/bd18a4ce3e65411bb956636d4a2ef4b5fbe8b9e1.1749104235.git.michal.simek@amd.com
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The cache driver here can only build on RISCV due to header
dependencies. Express that requirement in Kconfig as well.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
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The SoC pads of TH1520 are separated into three groups (AP 1, AP 2 and
AON) controlled by independent pin controllers. This patch ports their
driver from Linux kernel with most code for setting pinconf and pinmux
kept as is.
The dt-binding of TH1520 pin controller uses a schema where pins to
configure are specfied as strings and looked up at runtime, which the
generic pinctrl helpers of U-Boot cannot parse, thus a customized
set_state() callback is implemented to parse pinconfig nodes and setup
the configuration.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
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Update the MMC driver to retrieve the clock manager base address via
probing the clock manager node in the device tree.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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This reverts commit ae93d8106bdb5926efef9222d553adb295ebce96.
It is no longer needed since 24b1e0c7e2e3.
Since the obsolete include pulled in byteorder.h which is needed by now,
include this one directly.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Adding support for:
GD5F1GQ4RExxG
GD5F2GQ4UExxG
GD5F2GQ4RExxG
GD5F1GQ5RExxG
GD5F2GQ5UExxG
GD5F2GQ5RExxG
GD5F4GQ6UExxG
GD5F4GQ6RExxG
GD5F1GM7UExxG
GD5F1GM7RExxG
GD5F2GM7UExxG
GD5F2GM7RExxG
GD5F4GM8UExxG
GD5F4GM8RExxG
GD5F2GQ5xExxH
GD5F1GQ5RExxH
GD5F1GQ4RExxH
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
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The commit e8a9521e649f
("vf500/vf610: synchronise device trees with linux")
has synchronized U-Boot's DTS with v5.19 Linux kernel.
It turned out that in Linux's upstream iomuxc node description the
'fsl,mux_mask' was missing, so the U-Boot's pinctrl driver for NXP's
Vybrid SoC was not working properly.
As by default the mux mask was set to 0, for example the vf610 based
boards (like BK4) were bricked, due to misconfiguration of gpio at
early boot stage.
The fix for all NXP eligible boards is to define .mux_mask field for
soc specific *pinctrl_soc_info structure and use it directly in pinctrl
MMIO driver, without the need to read the "fsl,mux_mask" property from
device tree.
This change brings the NXP's pinctrl driver in U-Boot closer to Linux
upstream one.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com> #for i.MX8ULP
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Ilias Apalodimas <ilias.apalodimas@linaro.org> says:
Instructions that lead ito an exception in the hypervisor can't modify two
CPU registers at once for the ARM ISA.
These instructions cannot be emulated by KVM as they do not produce
syndrome information data that KVM can use to infer the destination
register, the faulting address, whether it was a load or store, or
if it's a 32 or 64 bit general-purpose register.
As a result an external abort is injected from QEMU, via ext_dabt_pending.
Link: https://lore.kernel.org/r/20250618065828.1312146-1-ilias.apalodimas@linaro.org
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A following patch is replacing our IO accessors with
do { ... } while(0) ones in order to make them usable with KVM.
That leads to an error eventually looking like this:
arch/arm/include/asm/io.h:62:9: error: expected expression before 'do'
62 | do { \
| ^~
arch/arm/include/asm/io.h:211:41: note: in expansion of macro '__raw_writel'
211 | #define out_arch(type,endian,a,v) __raw_write##type(cpu_to_##endian(v),a)
| ^~~~~~~~~~~
arch/arm/include/asm/io.h:223:25: note: in expansion of macro 'out_arch'
223 | #define out_be32(a,v) out_arch(l,be32,a,v)
| ^~~~~~~~
drivers/spi/fsl_dspi.c:127:17: note: in expansion of macro 'out_be32'
127 | out_be32(addr, val) : out_le32(addr, val);
| ^~~~~~~~
So adjust the current macros and code to be compatible with the upcoming
change.
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
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dw_pcie_link_set_max_link_width()"
This patch set from Marek Vasut <marek.vasut+renesas@mailbox.org>
introduces dw_pcie_link_set_max_link_width() similar to the Linux Kernel
and then migrates the current platform drivers to use it. Next it adds
support for Renesas R-Car Gen4 platforms and enables it on one.
Link: https://lore.kernel.org/r/20250617081641.8385-1-marek.vasut+renesas@mailbox.org
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Add R-Car Gen4 PCIe controller support for host mode.
This controller is based on Synopsys DesignWare PCIe. However, this
particular controller has a number of vendor-specific registers, and as
such, requires initialization code, including PHY firmware loading.
The PHY firmware loading is implemented in an entirely generic manner,
by calling a firmware loading script, which the user can configure in
a way they require. This provides the user with flexibility of loading
the PCIe firmware from whichever storage device they need to load it
from.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
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Use dw_pcie_link_set_max_link_width() instead of local implementation
of the same functionality. This does change the behavior slightly, as
the dw_pcie_link_set_max_link_width() implementation also programs the
LNKCAP register MLW, this should however be correct and is now aligned
with Linux kernel behavior.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
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Use dw_pcie_link_set_max_link_width() instead of local implementation
of the same functionality.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
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Use dw_pcie_link_set_max_link_width() instead of local implementation
of the same functionality. This does change the behavior slightly, as
the dw_pcie_link_set_max_link_width() implementation also programs the
LNKCAP register MLW, this should however be correct and is now aligned
with Linux kernel behavior.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
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Add dw_pcie_link_set_max_link_width() implementation ported from Linux kernel
as of commit 89db0793c9f2 ("PCI: dwc: Add missing PCI_EXP_LNKCAP_MLW handling").
This is common code which is already duplicated in multiple drivers.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
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