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8 daysSubtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstreamTom Rini
[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git Perform a few fixups in our dts* files to match upstream changes. Signed-off-by: Tom Rini <trini@konsulko.com>
8 daysMerge patch series "rockchip: puma-rk3399: anticipate breakage with v6.16 DT"Tom Rini
Quentin Schulz <foss+uboot@0leil.net> says: Due to updates to the Device Tree (migrating to onboard USB hub nodes instead of (badly) hacking things with a gpio regulator that doesn't actually work properly), we now need to enable the onboard USB hub driver in U-Boot. This anticipates upcoming breakage when 6.16 DT will be merged into U-Boot's dts/upstream. The series can be applied as is before v6.16 DT is merged or only the defconfig changes after 6.16 DT has been merged. The last two patches are simply to avoid probing devices that aren't actually routed on RK3399 Puma, which is nice to have but doesn't fix anything. Note that this depends on the following series: https://lore.kernel.org/u-boot/20250722-usb_onboard_hub_cypress_hx3-v4-0-91c3ee958c0e@thaumatec.com/ Link: https://lore.kernel.org/r/20250730-puma-usb-cypress-v1-0-b1c203c733f9@cherry.de
8 daysarm64: dts: rockchip: disable unrouted USB controllers and PHY on RK3399 ↵Quentin Schulz
Puma with Haikou The u2phy0_host port is the part of the USB PHY0 (namely the HOST0_DP/DM lanes) which routes directly to the USB2.0 HOST controller[1]. The other lanes of the PHY are routed to the USB3.0 OTG controller (dwc3), which we do use. The HOST0_DP/DM lanes aren't routed on RK3399 Puma so let's simply disable the USB2.0 controllers. USB3 OTG has been known to be unstable on RK3399 Puma Haikou for a while, one of the recurring issues being that only USB2 is detected and not USB3 in host mode. Reading the justification above and seeing that we are keeping u2phy0_host in the Haikou carrierboard DTS probably may have bothered you since it should be changed to u2phy0_otg. The issue is that if it's switched to that, USB OTG on Haikou is entirely broken. I have checked the routing in the Gerber file, the lanes are going to the expected ball pins (that is, NOT HOST0_DP/DM). u2phy0_host is for sure the wrong part of the PHY to use, but it's the only one that works at the moment for that board so keep it until we figure out what exactly is broken. No intended functional change. [1] https://rockchip.fr/Rockchip%20RK3399%20TRM%20V1.3%20Part2.pdf Chapter 2 USB2.0 PHY Fixes: 2c66fc34e945 ("arm64: dts: rockchip: add RK3399-Q7 (Puma) SoM") Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Signed-off-by: Lukasz Czechowski <lukasz.czechowski@thaumatec.com> Link: https://lore.kernel.org/r/20250425-onboard_usb_dev-v2-5-4a76a474a010@thaumatec.com Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: febd8c6ab52c683b447fe22fc740918c86feae43 ] (cherry picked from commit 0a0ebebfdd4558512675e1aff34bddb770086cb0)
8 daysarm64: dts: rockchip: disable unrouted USB controllers and PHY on RK3399 PumaQuentin Schulz
The u2phy1_host port is the part of the USB PHY1 (namely the HOST1_DP/DM lanes) which routes directly to the USB2.0 HOST controller[1]. The other lanes of the PHY are routed to the USB3.0 OTG controller (dwc3), which we do use. The HOST1_DP/DM lanes aren't routed on RK3399 Puma so let's simply disable the USB2.0 controllers and associated part in USB2.0 PHY. No intended functional change. [1] https://rockchip.fr/Rockchip%20RK3399%20TRM%20V1.3%20Part2.pdf Chapter 2 USB2.0 PHY Fixes: 2c66fc34e945 ("arm64: dts: rockchip: add RK3399-Q7 (Puma) SoM") Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Signed-off-by: Lukasz Czechowski <lukasz.czechowski@thaumatec.com> Link: https://lore.kernel.org/r/20250425-onboard_usb_dev-v2-4-4a76a474a010@thaumatec.com Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: 3373af1d76bacd054b37f3e10266dd335ce425f8 ] (cherry picked from commit 97640da1f41d022484c1a4725bed943a5ae56073)
8 daysarm64: dts: rockchip: fix internal USB hub instability on RK3399 PumaLukasz Czechowski
Currently, the onboard Cypress CYUSB3304 USB hub is not defined in the device tree, and hub reset pin is provided as vcc5v0_host regulator to usb phy. This causes instability issues, as a result of improper reset duration. The fixed regulator device requests the GPIO during probe in its inactive state (except if regulator-boot-on property is set, in which case it is requested in the active state). Considering gpio is GPIO_ACTIVE_LOW for Puma, it means it’s driving it high. Then the regulator gets enabled (because regulator-always-on property), which drives it to its active state, meaning driving it low. The Cypress CYUSB3304 USB hub actually requires the reset to be asserted for at least 5 ms, which we cannot guarantee right now since there's no delay in the current config, meaning the hub may sometimes work or not. We could add delay as offered by fixed-regulator but let's rather fix this by using the proper way to model onboard USB hubs. Define hub_2_0 and hub_3_0 nodes, as the onboard Cypress hub consist of two 'logical' hubs, for USB2.0 and USB3.0. Use the 'reset-gpios' property of hub to assign reset pin instead of using regulator. Rename the vcc5v0_host regulator to cy3304_reset to be more meaningful. Pin is configured to output-high by default, which sets the hub in reset state during pin controller initialization. This allows to avoid double enumeration of devices in case the bootloader has setup the USB hub before the kernel. The vdd-supply and vdd2-supply properties in hub nodes are added to provide correct dt-bindings, although power supplies are always enabled based on HW design. Fixes: 2c66fc34e945 ("arm64: dts: rockchip: add RK3399-Q7 (Puma) SoM") Cc: stable@vger.kernel.org # 6.6 Cc: stable@vger.kernel.org # Backport of the patch in this series fixing product ID in onboard_dev_id_table in drivers/usb/misc/onboard_usb_dev.c driver Signed-off-by: Lukasz Czechowski <lukasz.czechowski@thaumatec.com> Link: https://lore.kernel.org/r/20250425-onboard_usb_dev-v2-3-4a76a474a010@thaumatec.com Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: d7cc532df95f7f159e40595440e4e4b99481457b ] (cherry picked from commit 0fe42d171081426ab119ca5c0eb130e5f3a9a805)
8 daysMerge patch series "rockchip: ringneck-px30: anticipate breakage with ↵Tom Rini
v6.16-rc1 DT" Quentin Schulz <foss+uboot@0leil.net> says: v6.16-rc1 will bring an incompatible change to the Device Tree of PX30 Ringneck which will break Ethernet support. Unfortunately, the designware net driver's logic doesn't seem to allow having the old Device Tree (without MDIO bus and Ethernet PHY nodes) with DM_MDIO and DM_ETH_PHY enabled so there cannot be a smooth transition. Since this is going to bite me in a few months time, let's just break and fix it now in a couple of commits so I don't have to think about it later :) This can be cleanly applied on master or next, I have absolutely zero preference on the branch this should be merged in (my opinion is that it's too late in the 2024.07 cycle to bring this in :) ). Link: https://lore.kernel.org/r/20250611-ringneck-mdio-v1-0-529a40a0f966@cherry.de
8 daysarm64: dts: rockchip: move reset to dedicated eth-phy node on ringneckHeiko Stuebner
Using snps,reset-* properties to handle the ethernet-phy resets is deprecated and instead a real phy node should be used. Move the Ringneck phy-reset properties to such a node Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de> Tested-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250514150745.2437804-3-heiko@sntech.de Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: e463625af7f92c4a9f097f7fb87f6baaad6e762a ] (cherry picked from commit 76d0d8e00c9ac845ca8d6cbe191cf015ca3a8c16) Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
8 daysarm64: dts: rockchip: add basic mdio node to px30Heiko Stuebner
Using snps,reset-* properties for handling the phy-reset is deprecated and instead a real phy node should be defined that then contains the reset-gpios handling. To facilitate this, add the core mdio node under the px30's gmac, similar to how the other Rockchip socs already do this. Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250514150745.2437804-2-heiko@sntech.de Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: ede4837a504ca7e5811217060aa8300b8d0cf7f2 ] (cherry picked from commit cb54a264ecdb9e95b1529e4542e157cb9acded30) Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
11 daysarm64: dts: allwinner: a523: add Avaota-A1 router supportAndre Przywara
The Avaota A1 router board is an Open Source hardware board, designed by YuzukiHD. Pine64 produces some boards and sells them. It uses the Allwinner A527 or T527 SoC, and comes with the following features: - Eight ARM Cortex-A55 cores, Mali-G57 MC1 GPU - 1GiB/2GiB/4GiB LPDDR4 DRAM - AXP717 + AXP323 PMIC - Raspberry-Pi-2 compatible GPIO header - 1 USB 2.0 type A host port, 1 USB 3.0 type A host post - 1 USB 2.0 type C port (OTG + serial debug) - MicroSD slot - eMMC between 16 and 128 GiB - on-board 16MiB bootable SPI NOR flash - two 1Gbps Ethernet ports (via RTL8211F PHYs) - HDMI port - DP port - camera and LCD connectors - 3.5mm headphone jack - (yet) unsupported WiFi/BT chip - 1.3" LC display, connected via SPI - 12 V barrel plug for power supply Add the devicetree file describing the currently supported features. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20250307005712.16828-12-andre.przywara@arm.com [wens@csie.org: Squash in SD card detect pull resistor fix] Link: https://patch.msgid.link/20250425003422.3465-1-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai <wens@csie.org> [ upstream commit: dbe54efa32afe5b82763c015cbe9e64c4d4e117a ] (cherry picked from commit ebcb8469ef4336c05c6b9f409714a23cfc891fff)
11 daysarm64: dts: allwinner: a523: add Radxa A5E supportAndre Przywara
The Radxa A5E is a development board using the Allwinner A527 SoC, which is using the same die as the A523 SoC, just exposing the pins of more peripherals (like HDMI or the 2nd MAC). The board features: - Allwinner A527/T527 SoC: 8 ARM Cortex-A55 cores, Mali-G57 MC1 GPU - 1GiB/2GiB/4GiB LPDDR4 DRAM - AXP717 + AXP323 PMICs - Raspberry-Pi-2 compatible 40pin GPIO header - 1 USB 2.0 type C port (OTG), also power supply - 1 USB 3.0 type A host port (multiplexed with M.2 slot) - 1 M.2 M-key 2230 slot, with 1 PCIe2.1 lane connected (multiplexed with USB 3.0 port) - MicroSD slot - optional eMMC, 8, 16 or 32GB available - optional on-board 16MiB bootable SPI NOR flash - two 1Gbps Ethernet ports (via MAXIO MAE0621A PHYs) - PoE header for optional supply circuit on one Ethernet port - WiFi 802.11 a/b/g/n/ac/ax (LB-Link BL-M8800DS2 module using AIC8800) - HDMI port - camera and LCD connectors - power supply via USB-C connector (but no PD) or GPIO header pins This .dts describes the devices as far as we support them at the moment. The PMIC rails have been assigned as per the schematics. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20250307005712.16828-14-andre.przywara@arm.com [wens@csie.org: Squash in SD card detect pull resistor fix] Link: https://patch.msgid.link/20250425003422.3465-1-andre.przywara@arm.com [wens@csie.org: Rename dts file to sun55i-a527-cubie-a5e.dts] Signed-off-by: Chen-Yu Tsai <wens@csie.org> [ upstream commit: c2520cd032ae8ca3fdaf77b3f3aa687c8cb7843f ] (cherry picked from commit 91ad117321c0901094c1d6467df90f5f6757569a)
11 daysarm64: dts: allwinner: a523: add X96Q-Pro+ supportAndre Przywara
The X96QPro+ is a TV box using the Allwinner H728 SoC. That SoC seems to be a package variant of the A523 family, at least it uses the same SoC ID and is compatible as far as we can assess. It comes with the following specs: - Allwinner H728 SoC: 8 Arm Cortex-A55 cores, Mali-G57 MC1 GPU - 2 or 4GiB DDR3L DRAM - 32, 64, or 128 GiB eMMC flash - AXP717 + AXP323 PMICs - Gigabit Ethernet (using MAXIO PHY) - HDMI port - 2 * USB 2.0 ports - 1 * USB 3.0 port - microSD card slot - TOSLINK digital audio output - 3.5mm A/V port - infrared sensor - 7-segment display - 5V barrel plug power supply - power button The PCB provides holes for soldering a UART header or cable, this is connected to the debug UART0. There is another set of UART pins available. The board also features a FEL button (accessible through the 3.5mm socket) and a reset button (only accessible when case is open). This .dts just describes the basic peripherals as far as we support them at the moment. The PMIC rail assignments are reverse engineered as far as possible, by dumping them from a running Android system, and correlating them to other boards using the same SoC. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20250307005712.16828-13-andre.przywara@arm.com [wens@csie.org: Squash in SD card detect pull resistor fix] Link: https://patch.msgid.link/20250425003422.3465-1-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai <wens@csie.org> [ upstream commit: 4ee87d875071390b4e24ce46dbdd792216d61651 ] (cherry picked from commit 693da0a03149b77a3e2bc11cfd314df8cc2fab40)
11 daysarm64: dts: allwinner: Add Allwinner A523 .dtsi fileAndre Przywara
The Allwinner A523, and its siblings A527 and T527, which share the same die, are a new family of SoCs introduced in 2023. They features eight Arm Cortex-A55 cores, and, among the other usual peripherals, a PCIe and USB 3.0 controller. Add the basic SoC devicetree .dtsi for the chip, describing the fundamental peripherals: the cores, GIC, timer, RTC, CCU and pinctrl. Also some other peripherals are fully compatible with previous IP, so add the USB and MMC nodes as well. The other peripherals will be added in the future, once we understand their compatibility and DT requirements. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20250307005712.16828-9-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai <wens@csie.org> [ upstream commit: 35ac96f796649346c9b0440413dc6c5138249b3e ] (cherry picked from commit 247a3572abcfd7a0d48e12f8f810f1cbae5ce4f4)
2025-06-24arm64: dts: allwinner: h616: add YuzukiHD Chameleon supportAndre Przywara
The Chameleon board is an OpenHardware devboard made by YuzukiTsuru. The form factor resembles the Raspberry Pi Model A boards, though it differs significantly in its features: - Allwinner H618 SoC (4 * Arm Cortex-A53 cores, 1MB L2 cache, 1.4 GHz) - between 512MiB and 2GiB DDR3 DRAM - up to 128 GiB eMMC flash - AXP313a PMIC - 100 Mbit/s Ethernet pins on a header - XR829 WIFI+Bluetooth chip - 4 * USB 2.0 USB-C ports - microSD card slot - 3.5mm A/V port Add the devicetree describing the board's peripherals and their connections. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20250307005712.16828-16-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai <wens@csie.org> [ upstream commit: f4a6b0f7200f8629f4138f1094ce654ab75df41e ] (cherry picked from commit 3a879d878553d57057ce0a7096bfbf1eb077f6dc)
2025-06-24arm64: dts: allwinner: a100: add Liontron H-A133L board supportAndre Przywara
The H-A133L board is an industrial development board made by Liontron. It contains a number of dedicated JST connectors, to connect external peripherals. It features: - Allwinner A133 SoC (4 * Arm Cortex-A53 cores at up to 1.6 GHz) - 1 GiB, 2 GiB or 4 GiB of LPDDR4 DRAM - between 16 and 128 GiB eMMC flash - AXP707 PMIC (compatible to AXP803) - 100 Mbit/s RJ45 Ethernet socket, using an JLSemi JL1101 PHY - XR829 WIFI+Bluetooth chip - 2 * USB 2.0 USB-A ports, plus three sets of USB pins on connectors (connected via a USB hub connected to USB1 on the SoC) - microSD card slot - 3.5mm A/V port - 12V power supply - connectors for an LVDS or MIPI-DSI panel Add the devicetree describing the board's peripherals and their connections. Despite being a devboard, the manufacturer does not publish a schematic (I asked), so the PMIC rail assignments were bases on BSP dumps, educated guesses and some experimentation. Dropping the always-on property from any of the rails carrying it will make the board hang as soon as the kernel turns off unused regulators. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Link: https://patch.msgid.link/20250505164729.18175-4-andre.przywara@arm.com [wens@csie.org: fix property in &usbphy; fix comment typo in &usb_otg] Signed-off-by: Chen-Yu Tsai <wens@csie.org> [ upstream commit: a3cd12acb7b74d9b243cd893209972fc657d0bd3 ] (cherry picked from commit 4062957c0797752dcf8b71f99c7aa47301c70aac)
2025-06-24arm64: dts: allwinner: a100: set maximum MMC frequencyAndre Przywara
The manual for the Allwinner A133 SoC mentions that the maximum supported MMC frequency is 150 MHz, for all of the MMC devices. Describe that in the DT entry, to help drivers setting the right interface frequency. Fixes: fcfbb8d9ec58 ("arm64: allwinner: a100: Add MMC related nodes") Signed-off-by: Andre Przywara <andre.przywara@arm.com> Link: https://patch.msgid.link/20250505202416.23753-1-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai <wens@csie.org> [ upstream commit: d8f10550448b03d3c5c6d9392119205c65ebfc89 ] (cherry picked from commit 85e37e6a8a002eb231df8209478d7ff2b134a451)
2025-06-19dtc: Add Kconfig option to pad device tree blobEric Schikschneit
This will allow arch(s) that use device tree blobs to pad the end of the device tree so they can be modified by board files at run time. This will help prevent errors such as FDT_ERR_NOSPACE from occurring. Signed-off-by: Eric Schikschneit <eric.schikschneit@novatechautomation.com> [trini: Change default order so that X86 && EFI_APP works correctly]
2025-06-16Merge tag 'u-boot-dfu-next-20250616' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-dfu into next u-boot-dfu-next-20250616 CI: https://source.denx.de/u-boot/custodians/u-boot-dfu/-/pipelines/26704 Usb gadget: - Fix ti_musb driver in gadget mode (with DM_USB_GADGET) DFU: - mmc/scsi backends when using 10 or more partitions
2025-06-12imx91: Drop OF_UPSTREAMPeng Fan
i.MX91 device tree still not landed in linux kernel, so drop OF_UPSTREAM and move the device tree files to arch/arm/dts Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
2025-06-11ARM: dts: stm32: support STM32h747i-disco boardDario Binacchi
The board includes an STM32H747XI SoC with the following resources: - 2 Mbytes Flash - 1 Mbyte SRAM - LCD-TFT controller - MIPI-DSI interface - FD-CAN - USB 2.0 high-speed/full-speed - Ethernet MAC - camera interface Detailed information can be found at: https://www.st.com/en/evaluation-tools/stm32h747i-disco.html Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Link: https://lore.kernel.org/r/20250427074404.3278732-9-dario.binacchi@amarulasolutions.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> [ upstream commit: 49ba8fc6eab63165639ffbb9f976222d39739cab ] (cherry picked from commit 19c508dc3d584dc81c0cc6a05576f436022db5b6)
2025-06-11ARM: dts: stm32: add an extra pin map for USART1 on stm32h743Dario Binacchi
Add an additional pin map configuration for using the USART1 controller on the stm32h743 MCU. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Link: https://lore.kernel.org/r/20250427074404.3278732-8-dario.binacchi@amarulasolutions.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> [ upstream commit: 8e71dfe46a4a1e9505b1a327470f879b63388968 ] (cherry picked from commit 9d5ec2c9c5d5131e701447c5c32aaf6c688c6e01)
2025-06-11ARM: dts: stm32: add pin map for UART8 controller on stm32h743Dario Binacchi
Add a pin map configuration for using the UART8 controller on the stm32h743 MCU. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Link: https://lore.kernel.org/r/20250427074404.3278732-7-dario.binacchi@amarulasolutions.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> [ upstream commit: 47d16ab94b8e5e85aedba3cd22cfdf3877bf1dfb ] (cherry picked from commit 59621a6472cd6eeb748ed6d6202a21d0f3cc5a83)
2025-06-11ARM: dts: stm32: add uart8 node for stm32h743 MCUDario Binacchi
Add support for UART8 by applying the settings specified in the reference manual RM0433. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Link: https://lore.kernel.org/r/20250427074404.3278732-6-dario.binacchi@amarulasolutions.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> [ upstream commit: 07aa43adae2363c3734055aeba0789536fa0f8f2 ] (cherry picked from commit 8fe35c381c7c6db1b95c80be551afada1e9f28e0)
2025-06-11ARM: dts: stm32h7-pinctrl: add _a suffix to u[s]art_pins phandlesDario Binacchi
Allow expanding possible configurations for the same peripheral, consistent with the scheme adopted in Linux. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Link: https://lore.kernel.org/r/20250427074404.3278732-2-dario.binacchi@amarulasolutions.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> [ upstream commit: 6a36dca4375fce51b627f5a985a79fc8b8bd7f55 ] (cherry picked from commit 9a72c83f2e670087ae2d6dc54d2926f16c6762d0)
2025-06-10arm64: dts: renesas: r8a779g3: Add Retronix R-Car V4H Sparrow Hawk board supportMarek Vasut
Add Retronix R-Car V4H Sparrow Hawk board based on Renesas R-Car V4H ES3.0 (R8A779G3) SoC. This is a single-board computer with single gigabit ethernet, DSI-to-eDP bridge, DSI and two CSI2 interfaces, audio codec, two CANFD ports, micro SD card slot, USB PD supply, USB 3.0 ports, M.2 Key-M slot for NVMe SSD, debug UART and JTAG. DT is imported from Linux next commit: a719915e76f2 ("arm64: dts: renesas: r8a779g3: Add Retronix R-Car V4H Sparrow Hawk board support") Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-05-27Subtree merge tag 'v6.15-dts' of dts repo [1] into dts/upstreamTom Rini
[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git Signed-off-by: Tom Rini <trini@konsulko.com>
2025-04-23arm64: dts: rockchip: Add devicetree for the ROC-RK3576-PCHeiko Stuebner
As the name implies, it is built around the RK3576 SoC with 4x Cortex-A72 cores, four Cortex-A53 cores and Mali-G52 MC3 GPU. Storage options are EMMC, SD-Card, a 2242 M.2 slot and the possibility to use UFS 2.0 storage. Video Output options are a HDMI port, a DSI connector as well as Display- Port via the TypeC connector (all of them not yet supported). Networking options are a Low-profile Gigabit Ethernet RJ45 port with Motorcomm YT8531 PHY as well as WiFi via an AMPAK AP6256 module. USB ports on the board are 1x USB 3.0 port, 1x USB 2.0 port, 1x USB Type-C and it comes with 40-pin GPIO header Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250210205126.1173631-3-heiko@sntech.de [ upstream commit: 887ff17cdd8f088a52e2b61e71f2b6c9b9678de6 ] (cherry picked from commit 388e7272d092bd20e414cd408bac39d8fd02d765) Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-04-23arm64: dts: rockchip: add rk3576 otp nodeHeiko Stuebner
This adds the otp node to the rk3576 soc devicetree including the individual fields we know about. Tested-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250210224510.1194963-7-heiko@sntech.de [ upstream commit: 8715d2eeb062f6859c252bb6c87b363230b66e9f ] (cherry picked from commit d67cf6de8aacb4abcdfb516eeb8a511a4a657bc1) Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-04-23arm64: dts: rockchip: Enable onboard eMMC on Radxa E20CJonas Karlman
The Radxa E20C may come with an onboard eMMC (8GB / 16GB / 32GB / 64GB). Enable support for the onboard eMMC on Radxa E20C. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250305214108.1327208-4-jonas@kwiboo.se Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: 3a01b5f14a8ae2d45aea5aeed30001ac1655de86 ] (cherry picked from commit bd4c8a1c08f92d863d89c0ddff59e5f5bc6a1e34) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-04-23arm64: dts: rockchip: Add maskrom button to Radxa E20CJonas Karlman
Radxa E20C has two buttons, one SARADC maskrom button and one GPIO user button. Add support for the maskrom button using a adc-keys node, also add the regulators used by SARADC controller. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250304201642.831218-5-jonas@kwiboo.se Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: 3a2819ee9c71d1c6388e456cc4eb042914d15d7e ] (cherry picked from commit 460ef5b623e5fa69843305faf50f6b1a8e81e1cd) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-04-23arm64: dts: rockchip: Add user button to Radxa E20CJonas Karlman
Radxa E20C has two buttons, one SARADC maskrom button and one GPIO user button. Add support for the user button using a gpio-keys node. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250304201642.831218-3-jonas@kwiboo.se Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: ad8afc8813567994164f2720189c819da8c22b99 ] (cherry picked from commit 6793b56b79df26ab3323e5293b97577d0786ddb3) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-04-23arm64: dts: rockchip: Add leds node to Radxa E20CJonas Karlman
Radxa E20C has three gpio controlled leds (sys, wan and lan). Add led nodes and set default trigger to heartbeat for the sys led and netdev for the lan and wan leds. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250304201642.831218-2-jonas@kwiboo.se Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: 6a709e003492e9878d5f1357be0b2e1162e1e6a6 ] (cherry picked from commit a3556ede6b48c7760ac3608ad77601fca26d2ce0) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-04-23arm64: dts: rockchip: Add uart0 pinctrl to Radxa E20CJonas Karlman
Radxa E20C route UART0 M0 pins (GPIO4_C7 and GPIO4_D0) to the onboard CH340B for debug console use. Add pinctrl for UART0 M0 pins used for serial console. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250228064024.3200000-6-jonas@kwiboo.se Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: 0d2312f0d3e4ce74af0977c1519a07dfc71a82ac ] (cherry picked from commit 9bcf6ccdd87c3be48fe7d75150c6e403c5c0a42d) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-04-23arm64: dts: rockchip: Add SDHCI controller for RK3528Jonas Karlman
The SDHCI controller in Rockchip RK3528 is similar to the one included in RK3588. Add device tree node for the SDHCI controller in RK3528. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250305214108.1327208-3-jonas@kwiboo.se Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: a98cc47f79ab5b8059b748bf0bd59335edfff7d9 ] (cherry picked from commit db7a99c423dea0ead19d6a18053d898a762a3b48) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-04-23arm64: dts: rockchip: Add SARADC node for RK3528Jonas Karlman
Add a device tree node for the SARADC controller used by RK3528. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250304201642.831218-4-jonas@kwiboo.se Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: 6e58302c84ce90aadbecd41efe1f69098a6f91e5 ] (cherry picked from commit 8ba64ba5cb301bca777ba7f0d2a2a72f49af5ff2) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-04-23arm64: dts: rockchip: enable SCMI clk for RK3528 SoCChukun Pan
Same as RK3568, RK3528 uses SCMI clk instead of ARMCLK. Add SCMI clk for CPU, GPU and RNG will also use it. Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Link: https://lore.kernel.org/r/20250307100008.789129-2-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: fbcbc1fb93e14729bd87ab386b7f62694dcc8b51 ] (cherry picked from commit 6e03c7e28e2d929a420809a24b0379305a9fb86a) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-04-23arm64: dts: rockchip: Add rk3528 QoS register nodeChukun Pan
The Quality-of-Service (QsS) node stores/restores specific register contents when the power domains is turned off/on. Add QoS node so that they can connect to the power domain. Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Link: https://lore.kernel.org/r/20250306123809.273655-3-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: 61a05d8ca3030a544175671f5fab7a8f29c24085 ] (cherry picked from commit 9ee90dfd6957fcc42ea94c43d195b01d1b286713) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-04-23arm64: dts: rockchip: Add pinctrl and gpio nodes for RK3528Jonas Karlman
Add pinctrl and gpio nodes for RK3528 and import rk3528-pinctrl.dtsi from vendor linux-6.1-stan-rkr5 kernel with the hdmi-pins-idle node removed due to missing label reference to pcfg_output_low_pull_down. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250228064024.3200000-5-jonas@kwiboo.se Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: a31fad19ae39ea27b5068e3b02bcbf30a905339b ] (cherry picked from commit 89a24fa2e923b68a42ccc8cc9cb2d5bdf291ac40) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-04-23arm64: dts: rockchip: Add UART clocks for RK3528 SoCYao Zi
Add missing clocks in UART nodes for RK3528 SoC. Signed-off-by: Yao Zi <ziyao@disroot.org> Link: https://lore.kernel.org/r/20250217061142.38480-10-ziyao@disroot.org Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: b9454434d0349223418f74fbfa7b902104da9bc5 ] (cherry picked from commit 12f69f638472dc9cf1b62816c7d4407de1846d12) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-04-23arm64: dts: rockchip: Add clock generators for RK3528 SoCYao Zi
Add dt node for RK3528 clock and reset unit. Clock "gmac0_clk" is generated by internal Ethernet phy, a fixed clock node is added as a placeholder to avoid orphans. Signed-off-by: Yao Zi <ziyao@disroot.org> Link: https://lore.kernel.org/r/20250217061142.38480-9-ziyao@disroot.org Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: 858cdcdd11cf9913756297d3869e4de0f01329ea ] (cherry picked from commit 60741472b42e92d2393327cb70669ab90e3b382f) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-04-23arm64: dts: rockchip: Add rng node to RK3588Nicolas Frattaroli
Add the RK3588's standalone hardware random number generator node to its device tree, and enable it. Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://lore.kernel.org/r/20250204-rk3588-trng-submission-v2-6-608172b6fd91@collabora.com [changed reset-id to its numeric value while the constant makes its way through the crypto tree] Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: 6ee0b9ad3995ee5fa229035c69013b7dd0d3634b ] (cherry picked from commit 4800c4aaad00ffdc053850f130e8504a04dd110d) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-04-22Merge patch series "MIPS: Boston: Various enhancements"Tom Rini
Jiaxun Yang <jiaxun.yang@flygoat.com> says: This is a huge series which promoted MIPS/Boston target into a usable state, with fixes to drivers and general framework issues I found in this process. I also converted the target to OF_UPSTREAM. This target is covered by QEMU, to test on QEMU: ``` make boston64r6el_defconfig make qemu-system-mips64el -M boston -cpu I6500 -bios ./u-boot.bin -nographic ``` Link: https://lore.kernel.org/r/20240517-boston-v3-0-1ea7d23f4a1d@flygoat.com
2025-04-22dts/upstream: Add Makefile for MIPSJiaxun Yang
It is required to make OF_UPSTREAM work. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2025-04-02Subtree merge tag 'v6.14-dts' of dts repo [1] into dts/upstreamTom Rini
[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git
2025-04-01arm64: dts: airoha: en7581: Add Clock Controller nodeChristian Marangi
Add Clock Controller node for EN7581 SoC to correctly expose supported clock for any user in the SoC. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20250105150328.15172-1-ansuelsmth@gmail.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> [ upstream commit: 7693017580e9be839fa5f27130bb6500f3597595 ]
2025-02-19arm64: dts: rockchip: Fix sdmmc access on rk3308-rock-s0 v1.1 boardsJonas Karlman
BootROM leave GPIO4_D6 configured as SDMMC_PWREN function and DW MCI driver set PRWEN high on MMC_POWER_UP and low on MMC_POWER_OFF. Similarly U-Boot also set PRWEN high before accessing mmc. However, HW revision prior to v1.2 must pull GPIO4_D6 low to access sdmmc. For HW revision v1.2 the state of GPIO4_D6 has no impact. Model an always-on active low fixed regulator using GPIO4_D6 to fix use of sdmmc on older HW revisions of the board. Fixes: adeb5d2a4ba4 ("arm64: dts: rockchip: Add Radxa ROCK S0") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20241119230838.4137130-1-jonas@kwiboo.se Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: 26c100232b09ced0857306ac9831a4fa9c9aa231 ] (cherry picked from commit ca8e0bedbc790b19b11efc223677d178b8eeb74e) Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2025-01-26Subtree merge tag 'v6.13-dts' of dts repo [1] into dts/upstreamTom Rini
[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git [rockchip fixes from Jonas Karlman via IRC]
2025-01-22arm64: dts: qcom: qcs9100: Add support for the QCS9100 Ride and Ride Rev3 boardsTengfei Fan
Add device tree support for the QCS9100 Ride and Ride Rev3 boards. The QCS9100 is a variant of the SA8775p, and they are fully compatible with each other. The QCS9100 Ride/Ride Rev3 board is essentially the same as the SA8775p Ride/Ride Rev3 board, with the QCS9100 SoC mounted instead of the SA8775p. Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com> Reviewed-by: Konrad Dybcio <konradybcio@kernel.org> Link: https://lore.kernel.org/r/20240911-add_qcs9100_support-v2-4-e43a71ceb017@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> [ upstream commit: 7dcc1dfaa3d1cd3aafed2beb7086ed34fdb22303 ] (cherry picked from commit db6231faa8ef46e5ff5d5ece0c930a07c6358562) Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Link: https://lore.kernel.org/r/20250110050817.3819282-2-quic_varada@quicinc.com Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2025-01-10arm64: dts: rockchip: add Radxa ROCK 5CFUKAUMI Naoki
Radxa ROCK 5C is a 8K computer for everything[1] using the Rockchip RK3588S2 chip: - Rockchip RK3588S2 - Quad A76 and Quad A55 CPU - 6 TOPS NPU - up to 32GB LPDDR4x RAM - eMMC / SPI flash connector - Micro SD Card slot - Gigabit ethernet port (supports PoE with add-on PoE HAT) - WiFi6 / BT5.4 - 1x USB 3.0 Type-A HOST port - 1x USB 3.0 Type-A OTG port - 2x USB 2.0 Type-A HOST port - 1x USB Type-C 5V power port [1] https://radxa.com/products/rock5/5c Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Link: https://lore.kernel.org/r/20241021090548.1052-2-naoki@radxa.com Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: 3ddf5cdb77e6efd6fe9b70f36dec935e324a3cd2 ] (cherry picked from commit f80689fcef4b9b07a97b629b4075cc1a4c21a68e) Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-01-10arm64: dts: rockchip: Add HDMI0 node to rk3588Cristian Ciocaltea
Add support for the HDMI0 output port found on RK3588 SoC. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20241019-rk3588-hdmi0-dt-v2-1-466cd80e8ff9@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: d7bb71e69f58c1b3665a9f926bf8d3855111bf8e ] (cherry picked from commit a839348380c2072e00a26bbdb80744982fe04c56) Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-01-10arm64: dts: rockchip: Split up RK3588's PCIe pinctrlsSam Edwards
These pinctrls manage the low-speed PCIe signals: - CLKREQ#: An output on the RK3588 (both RC or EP modes), used to request that external clock-generation circuitry provide a clock. - PERST#: An input on the RK3588 in EP mode, used to detect a reset signal from the RC. In RC mode, the hardware does not use this signal: Linux itself generates it by putting the pin in GPIO mode. - WAKE#: In EP mode, this is an output; in RC mode, this is an input. Each of these signals serves a distinct purpose, and more importantly, PERST# should not be muxed when the RK3588 is in the RC role. Bundling them together in pinctrl groups prevents proper use: indeed, almost none of the current board-specific .dts files make any use of them. (Exception: Rock 5A recently had a patch land that misuses _pins; this patch corrects that.) However, on some RK3588 boards, the PCIe 3 controller will indefinitely stall the boot if CLKREQ# is not muxed (details in the next patch). This patch unbundles the signals to allow them to be used. Signed-off-by: Sam Edwards <CFSworks@gmail.com> Link: https://lore.kernel.org/r/20240912025034.180233-2-CFSworks@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: 4294e32111781b3de4d73b944cbd1bc1662a9a7a ] (cherry picked from commit 8713425fa162b61bcf5f7a6dcd171fddfb12be36) Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-08 01:45:04 +0000