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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2024 NXP
*/
#include "imx91-pinfunc.h"
#include "imx93.dtsi"
/delete-node/ &A55_1;
/delete-node/ &mlmix;
/delete-node/ &mu1;
/delete-node/ &mu2;
&clk {
compatible = "fsl,imx91-ccm";
};
&eqos {
clocks = <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>,
<&clk IMX91_CLK_ENET1_QOS_TSN_GATE>,
<&clk IMX91_CLK_ENET_TIMER>,
<&clk IMX91_CLK_ENET1_QOS_TSN>,
<&clk IMX91_CLK_ENET1_QOS_TSN_GATE>;
assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>,
<&clk IMX91_CLK_ENET1_QOS_TSN>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
<&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
};
&fec {
clocks = <&clk IMX91_CLK_ENET2_REGULAR_GATE>,
<&clk IMX91_CLK_ENET2_REGULAR_GATE>,
<&clk IMX91_CLK_ENET_TIMER>,
<&clk IMX91_CLK_ENET2_REGULAR>,
<&clk IMX93_CLK_DUMMY>;
assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>,
<&clk IMX91_CLK_ENET2_REGULAR>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
<&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
assigned-clock-rates = <100000000>, <250000000>;
};
&iomuxc {
compatible = "fsl,imx91-iomuxc";
};
&tmu {
status = "disabled";
};
&{/thermal-zones/cpu-thermal/cooling-maps/map0} {
cooling-device = <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
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