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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#include "rockchip-u-boot.dtsi"
/ {
aliases {
mmc0 = &emmc;
mmc1 = &sdmmc;
};
chosen {
u-boot,spl-boot-order = &emmc, &sdmmc;
};
dmc {
bootph-all;
compatible = "rockchip,px30-dmc", "syscon";
reg = <0x0 0xff2a0000 0x0 0x1000>;
};
rng: rng@ff0b0000 {
compatible = "rockchip,cryptov2-rng";
reg = <0x0 0xff0b0000 0x0 0x4000>;
status = "disabled";
};
};
&uart2 {
clock-frequency = <24000000>;
bootph-all;
};
&uart2m0_xfer {
bootph-all;
};
&uart5 {
clock-frequency = <24000000>;
bootph-all;
};
&uart5_cts {
bootph-all;
};
&uart5_rts {
bootph-all;
};
&uart5_xfer {
bootph-all;
};
&sdmmc {
bootph-all;
/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
u-boot,spl-fifo-mode;
};
&emmc {
bootph-all;
/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
u-boot,spl-fifo-mode;
};
&grf {
bootph-all;
};
&pmugrf {
bootph-all;
};
&xin24m {
bootph-all;
};
&cru {
bootph-all;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-rates;
};
&pmucru {
bootph-all;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-rates;
};
&saradc {
bootph-all;
status = "okay";
};
&gpio0 {
bootph-all;
gpio-ranges = <&pinctrl 0 0 32>;
};
&gpio1 {
bootph-all;
gpio-ranges = <&pinctrl 0 32 32>;
};
&gpio2 {
bootph-all;
gpio-ranges = <&pinctrl 0 64 32>;
};
&gpio3 {
bootph-all;
gpio-ranges = <&pinctrl 0 96 32>;
};
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