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// SPDX-License-Identifier: GPL-2.0+
/*
* U-Boot additions
*
* Copyright (C) 2024 Intel Corporation <www.intel.com>
*/
#include "socfpga_agilex5-u-boot.dtsi"
/{
aliases {
spi0 = &qspi;
freeze_br0 = &freeze_controller;
};
soc {
freeze_controller: freeze_controller@0x20000450 {
compatible = "altr,freeze-bridge-controller";
reg = <0x20000450 0x00000010>;
status = "disabled";
};
};
memory {
/* 8GB */
reg = <0 0x80000000 0 0x80000000>,
<8 0x80000000 1 0x80000000>;
};
chosen {
stdout-path = "serial0:115200n8";
u-boot,spl-boot-order = &mmc,&flash0,"/memory";
};
};
&flash0 {
compatible = "jedec,spi-nor";
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
bootph-all;
/delete-property/ cdns,read-delay;
};
&i3c0 {
bootph-all;
};
&i3c1 {
bootph-all;
};
&mmc {
status = "okay";
bus-width = <4>;
sd-uhs-sdr50;
cap-mmc-highspeed;
bootph-all;
};
&combophy0 {
status = "okay";
bootph-all;
cdns,phy-use-ext-lpbk-dqs = <1>;
cdns,phy-use-lpbk-dqs = <1>;
cdns,phy-use-phony-dqs = <1>;
cdns,phy-use-phony-dqs-cmd = <1>;
cdns,phy-io-mask-always-on = <0>;
cdns,phy-io-mask-end = <5>;
cdns,phy-io-mask-start = <0>;
cdns,phy-data-select-oe-end = <1>;
cdns,phy-sync-method = <1>;
cdns,phy-sw-half-cycle-shift = <0>;
cdns,phy-rd-del-sel = <52>;
cdns,phy-underrun-suppress = <1>;
cdns,phy-gate-cfg-always-on = <1>;
cdns,phy-param-dll-bypass-mode = <1>;
cdns,phy-param-phase-detect-sel = <2>;
cdns,phy-param-dll-start-point = <254>;
cdns,phy-read-dqs-cmd-delay = <0>;
cdns,phy-clk-wrdqs-delay = <0>;
cdns,phy-clk-wr-delay = <0>;
cdns,phy-read-dqs-delay = <0>;
cdns,phy-phony-dqs-timing = <0>;
cdns,hrs09-rddata-en = <1>;
cdns,hrs09-rdcmd-en = <1>;
cdns,hrs09-extended-wr-mode = <1>;
cdns,hrs09-extended-rd-mode = <1>;
cdns,hrs10-hcsdclkadj = <3>;
cdns,hrs16-wrdata1-sdclk-dly = <0>;
cdns,hrs16-wrdata0-sdclk-dly = <0>;
cdns,hrs16-wrcmd1-sdclk-dly = <0>;
cdns,hrs16-wrcmd0-sdclk-dly = <0>;
cdns,hrs16-wrdata1-dly = <0>;
cdns,hrs16-wrdata0-dly = <0>;
cdns,hrs16-wrcmd1-dly = <0>;
cdns,hrs16-wrcmd0-dly = <0>;
cdns,hrs07-rw-compensate = <10>;
cdns,hrs07-idelay-val = <0>;
};
&qspi {
status = "okay";
};
&timer0 {
bootph-all;
};
&timer1 {
bootph-all;
};
&timer2 {
bootph-all;
};
&timer3 {
bootph-all;
};
&watchdog0 {
bootph-all;
};
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